1efeb5f99b0f1798fff5838bdee650532e723d42
8 time_sync_period=100000000000
9 time_sync_spin_threshold=100000000
13 children=clk_domain cpu dvfs_handler mem_ctrl membus
16 clk_domain=system.clk_domain
17 default_p_state=UNDEFINED
19 exit_on_work_items=false
22 kernel_addr_check=true
23 load_addr_mask=1099511627775
26 mem_ranges=0:536870911:0:0:0:0
27 memories=system.mem_ctrl
28 mmap_using_noreserve=false
31 p_state_clk_gate_bins=20
32 p_state_clk_gate_max=1000000000000
33 p_state_clk_gate_min=1000
39 work_begin_ckpt_count=0
40 work_begin_cpu_id_exit=-1
41 work_begin_exit_count=0
42 work_cpus_ckpt_count=0
46 system_port=system.membus.slave[2]
50 children=voltage_domain
55 voltage_domain=system.clk_domain.voltage_domain
57 [system.clk_domain.voltage_domain]
64 children=dtb interrupts isa itb tracer workload
67 clk_domain=system.clk_domain
69 default_p_state=UNDEFINED
70 do_checkpoint_insts=true
72 do_statistics_insts=true
76 function_trace_start=0
77 interrupts=system.cpu.interrupts
80 max_insts_all_threads=0
81 max_insts_any_thread=0
82 max_loads_all_threads=0
83 max_loads_any_thread=0
85 p_state_clk_gate_bins=20
86 p_state_clk_gate_max=1000000000000
87 p_state_clk_gate_min=1000
95 tracer=system.cpu.tracer
96 workload=system.cpu.workload
97 dcache_port=system.membus.slave[1]
98 icache_port=system.membus.slave[0]
105 [system.cpu.interrupts]
123 [system.cpu.workload]
125 cmd=tests/test-progs/hello/bin/alpha/linux/hello
137 max_stack_size=67108864
146 [system.dvfs_handler]
151 sys_clk_domain=system.clk_domain
152 transition_latency=100000000
181 addr_mapping=RoRaBaCoCh
182 bank_groups_per_rank=0
186 clk_domain=system.clk_domain
187 conf_table_reported=true
188 default_p_state=UNDEFINED
190 device_rowbuffer_size=1024
191 device_size=536870912
197 max_accesses_per_row=16
198 mem_sched_policy=frfcfs
199 min_writes_per_switch=16
201 p_state_clk_gate_bins=20
202 p_state_clk_gate_max=1000000000000
203 p_state_clk_gate_min=1000
204 page_policy=open_adaptive
206 range=0:536870911:0:0:0:0
209 static_backend_latency=10000
210 static_frontend_latency=10000
233 write_high_thresh_perc=85
234 write_low_thresh_perc=50
235 port=system.membus.master[0]
239 children=snoop_filter
240 clk_domain=system.clk_domain
241 default_p_state=UNDEFINED
245 p_state_clk_gate_bins=20
246 p_state_clk_gate_max=1000000000000
247 p_state_clk_gate_min=1000
248 point_of_coherency=true
251 snoop_filter=system.membus.snoop_filter
252 snoop_response_latency=4
254 use_default_range=false
256 master=system.mem_ctrl.port
257 slave=system.cpu.icache_port system.cpu.dcache_port system.system_port
259 [system.membus.snoop_filter]