tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 eventq_index=0
   5 full_system=false
   6 sim_quantum=0
   7 time_sync_enable=false
   8 time_sync_period=100000000000
   9 time_sync_spin_threshold=100000000
  10
  11 [system]
  12 type=System
  13 children=clk_domain cpu dvfs_handler l2bus l2cache mem_ctrl membus
  14 boot_osflags=a
  15 cache_line_size=64
  16 clk_domain=system.clk_domain
  17 eventq_index=0
  18 exit_on_work_items=false
  19 init_param=0
  20 kernel=
  21 kernel_addr_check=true
  22 load_addr_mask=1099511627775
  23 load_offset=0
  24 mem_mode=timing
  25 mem_ranges=0:536870911
  26 memories=system.mem_ctrl
  27 mmap_using_noreserve=false
  28 multi_thread=false
  29 num_work_ids=16
  30 readfile=
  31 symbolfile=
  32 work_begin_ckpt_count=0
  33 work_begin_cpu_id_exit=-1
  34 work_begin_exit_count=0
  35 work_cpus_ckpt_count=0
  36 work_end_ckpt_count=0
  37 work_end_exit_count=0
  38 work_item_id=-1
  39 system_port=system.membus.slave[1]
  40
  41 [system.clk_domain]
  42 type=SrcClockDomain
  43 children=voltage_domain
  44 clock=1000
  45 domain_id=-1
  46 eventq_index=0
  47 init_perf_level=0
  48 voltage_domain=system.clk_domain.voltage_domain
  49
  50 [system.clk_domain.voltage_domain]
  51 type=VoltageDomain
  52 eventq_index=0
  53 voltage=1.000000
  54
  55 [system.cpu]
  56 type=TimingSimpleCPU
  57 children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer workload
  58 branchPred=Null
  59 checker=Null
  60 clk_domain=system.clk_domain
  61 cpu_id=-1
  62 do_checkpoint_insts=true
  63 do_quiesce=true
  64 do_statistics_insts=true
  65 dstage2_mmu=system.cpu.dstage2_mmu
  66 dtb=system.cpu.dtb
  67 eventq_index=0
  68 function_trace=false
  69 function_trace_start=0
  70 interrupts=system.cpu.interrupts
  71 isa=system.cpu.isa
  72 istage2_mmu=system.cpu.istage2_mmu
  73 itb=system.cpu.itb
  74 max_insts_all_threads=0
  75 max_insts_any_thread=0
  76 max_loads_all_threads=0
  77 max_loads_any_thread=0
  78 numThreads=1
  79 profile=0
  80 progress_interval=0
  81 simpoint_start_insts=
  82 socket_id=0
  83 switched_out=false
  84 system=system
  85 tracer=system.cpu.tracer
  86 workload=system.cpu.workload
  87 dcache_port=system.cpu.dcache.cpu_side
  88 icache_port=system.cpu.icache.cpu_side
  89
  90 [system.cpu.dcache]
  91 type=Cache
  92 children=tags
  93 addr_ranges=0:18446744073709551615
  94 assoc=2
  95 clk_domain=system.clk_domain
  96 clusivity=mostly_incl
  97 demand_mshr_reserve=1
  98 eventq_index=0
  99 forward_snoops=true
 100 hit_latency=2
 101 is_read_only=false
 102 max_miss_count=0
 103 mshrs=4
 104 prefetch_on_access=false
 105 prefetcher=Null
 106 response_latency=2
 107 sequential_access=false
 108 size=65536
 109 system=system
 110 tags=system.cpu.dcache.tags
 111 tgts_per_mshr=20
 112 write_buffers=8
 113 writeback_clean=false
 114 cpu_side=system.cpu.dcache_port
 115 mem_side=system.l2bus.slave[1]
 116
 117 [system.cpu.dcache.tags]
 118 type=LRU
 119 assoc=2
 120 block_size=64
 121 clk_domain=system.clk_domain
 122 eventq_index=0
 123 hit_latency=2
 124 sequential_access=false
 125 size=65536
 126
 127 [system.cpu.dstage2_mmu]
 128 type=ArmStage2MMU
 129 children=stage2_tlb
 130 eventq_index=0
 131 stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
 132 sys=system
 133 tlb=system.cpu.dtb
 134
 135 [system.cpu.dstage2_mmu.stage2_tlb]
 136 type=ArmTLB
 137 children=walker
 138 eventq_index=0
 139 is_stage2=true
 140 size=32
 141 walker=system.cpu.dstage2_mmu.stage2_tlb.walker
 142
 143 [system.cpu.dstage2_mmu.stage2_tlb.walker]
 144 type=ArmTableWalker
 145 clk_domain=system.clk_domain
 146 eventq_index=0
 147 is_stage2=true
 148 num_squash_per_cycle=2
 149 sys=system
 150
 151 [system.cpu.dtb]
 152 type=ArmTLB
 153 children=walker
 154 eventq_index=0
 155 is_stage2=false
 156 size=64
 157 walker=system.cpu.dtb.walker
 158
 159 [system.cpu.dtb.walker]
 160 type=ArmTableWalker
 161 clk_domain=system.clk_domain
 162 eventq_index=0
 163 is_stage2=false
 164 num_squash_per_cycle=2
 165 sys=system
 166
 167 [system.cpu.icache]
 168 type=Cache
 169 children=tags
 170 addr_ranges=0:18446744073709551615
 171 assoc=2
 172 clk_domain=system.clk_domain
 173 clusivity=mostly_incl
 174 demand_mshr_reserve=1
 175 eventq_index=0
 176 forward_snoops=true
 177 hit_latency=2
 178 is_read_only=false
 179 max_miss_count=0
 180 mshrs=4
 181 prefetch_on_access=false
 182 prefetcher=Null
 183 response_latency=2
 184 sequential_access=false
 185 size=16384
 186 system=system
 187 tags=system.cpu.icache.tags
 188 tgts_per_mshr=20
 189 write_buffers=8
 190 writeback_clean=false
 191 cpu_side=system.cpu.icache_port
 192 mem_side=system.l2bus.slave[0]
 193
 194 [system.cpu.icache.tags]
 195 type=LRU
 196 assoc=2
 197 block_size=64
 198 clk_domain=system.clk_domain
 199 eventq_index=0
 200 hit_latency=2
 201 sequential_access=false
 202 size=16384
 203
 204 [system.cpu.interrupts]
 205 type=ArmInterrupts
 206 eventq_index=0
 207
 208 [system.cpu.isa]
 209 type=ArmISA
 210 decoderFlavour=Generic
 211 eventq_index=0
 212 fpsid=1090793632
 213 id_aa64afr0_el1=0
 214 id_aa64afr1_el1=0
 215 id_aa64dfr0_el1=1052678
 216 id_aa64dfr1_el1=0
 217 id_aa64isar0_el1=0
 218 id_aa64isar1_el1=0
 219 id_aa64mmfr0_el1=15728642
 220 id_aa64mmfr1_el1=0
 221 id_aa64pfr0_el1=17
 222 id_aa64pfr1_el1=0
 223 id_isar0=34607377
 224 id_isar1=34677009
 225 id_isar2=555950401
 226 id_isar3=17899825
 227 id_isar4=268501314
 228 id_isar5=0
 229 id_mmfr0=270536963
 230 id_mmfr1=0
 231 id_mmfr2=19070976
 232 id_mmfr3=34611729
 233 id_pfr0=49
 234 id_pfr1=4113
 235 midr=1091551472
 236 pmu=Null
 237 system=system
 238
 239 [system.cpu.istage2_mmu]
 240 type=ArmStage2MMU
 241 children=stage2_tlb
 242 eventq_index=0
 243 stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
 244 sys=system
 245 tlb=system.cpu.itb
 246
 247 [system.cpu.istage2_mmu.stage2_tlb]
 248 type=ArmTLB
 249 children=walker
 250 eventq_index=0
 251 is_stage2=true
 252 size=32
 253 walker=system.cpu.istage2_mmu.stage2_tlb.walker
 254
 255 [system.cpu.istage2_mmu.stage2_tlb.walker]
 256 type=ArmTableWalker
 257 clk_domain=system.clk_domain
 258 eventq_index=0
 259 is_stage2=true
 260 num_squash_per_cycle=2
 261 sys=system
 262
 263 [system.cpu.itb]
 264 type=ArmTLB
 265 children=walker
 266 eventq_index=0
 267 is_stage2=false
 268 size=64
 269 walker=system.cpu.itb.walker
 270
 271 [system.cpu.itb.walker]
 272 type=ArmTableWalker
 273 clk_domain=system.clk_domain
 274 eventq_index=0
 275 is_stage2=false
 276 num_squash_per_cycle=2
 277 sys=system
 278
 279 [system.cpu.tracer]
 280 type=ExeTracer
 281 eventq_index=0
 282
 283 [system.cpu.workload]
 284 type=LiveProcess
 285 cmd=tests/test-progs/hello/bin/arm/linux/hello
 286 cwd=
 287 drivers=
 288 egid=100
 289 env=
 290 errout=cerr
 291 euid=100
 292 eventq_index=0
 293 executable=
 294 gid=100
 295 input=cin
 296 kvmInSE=false
 297 max_stack_size=67108864
 298 output=cout
 299 pid=100
 300 ppid=99
 301 simpoint=0
 302 system=system
 303 uid=100
 304 useArchPT=false
 305
 306 [system.dvfs_handler]
 307 type=DVFSHandler
 308 domains=
 309 enable=false
 310 eventq_index=0
 311 sys_clk_domain=system.clk_domain
 312 transition_latency=100000000
 313
 314 [system.l2bus]
 315 type=CoherentXBar
 316 children=snoop_filter
 317 clk_domain=system.clk_domain
 318 eventq_index=0
 319 forward_latency=0
 320 frontend_latency=1
 321 response_latency=1
 322 snoop_filter=system.l2bus.snoop_filter
 323 snoop_response_latency=1
 324 system=system
 325 use_default_range=false
 326 width=32
 327 master=system.l2cache.cpu_side
 328 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 329
 330 [system.l2bus.snoop_filter]
 331 type=SnoopFilter
 332 eventq_index=0
 333 lookup_latency=0
 334 max_capacity=8388608
 335 system=system
 336
 337 [system.l2cache]
 338 type=Cache
 339 children=tags
 340 addr_ranges=0:18446744073709551615
 341 assoc=8
 342 clk_domain=system.clk_domain
 343 clusivity=mostly_incl
 344 demand_mshr_reserve=1
 345 eventq_index=0
 346 forward_snoops=true
 347 hit_latency=20
 348 is_read_only=false
 349 max_miss_count=0
 350 mshrs=20
 351 prefetch_on_access=false
 352 prefetcher=Null
 353 response_latency=20
 354 sequential_access=false
 355 size=262144
 356 system=system
 357 tags=system.l2cache.tags
 358 tgts_per_mshr=12
 359 write_buffers=8
 360 writeback_clean=false
 361 cpu_side=system.l2bus.master[0]
 362 mem_side=system.membus.slave[0]
 363
 364 [system.l2cache.tags]
 365 type=LRU
 366 assoc=8
 367 block_size=64
 368 clk_domain=system.clk_domain
 369 eventq_index=0
 370 hit_latency=20
 371 sequential_access=false
 372 size=262144
 373
 374 [system.mem_ctrl]
 375 type=DRAMCtrl
 376 IDD0=0.075000
 377 IDD02=0.000000
 378 IDD2N=0.050000
 379 IDD2N2=0.000000
 380 IDD2P0=0.000000
 381 IDD2P02=0.000000
 382 IDD2P1=0.000000
 383 IDD2P12=0.000000
 384 IDD3N=0.057000
 385 IDD3N2=0.000000
 386 IDD3P0=0.000000
 387 IDD3P02=0.000000
 388 IDD3P1=0.000000
 389 IDD3P12=0.000000
 390 IDD4R=0.187000
 391 IDD4R2=0.000000
 392 IDD4W=0.165000
 393 IDD4W2=0.000000
 394 IDD5=0.220000
 395 IDD52=0.000000
 396 IDD6=0.000000
 397 IDD62=0.000000
 398 VDD=1.500000
 399 VDD2=0.000000
 400 activation_limit=4
 401 addr_mapping=RoRaBaCoCh
 402 bank_groups_per_rank=0
 403 banks_per_rank=8
 404 burst_length=8
 405 channels=1
 406 clk_domain=system.clk_domain
 407 conf_table_reported=true
 408 device_bus_width=8
 409 device_rowbuffer_size=1024
 410 device_size=536870912
 411 devices_per_rank=8
 412 dll=true
 413 eventq_index=0
 414 in_addr_map=true
 415 max_accesses_per_row=16
 416 mem_sched_policy=frfcfs
 417 min_writes_per_switch=16
 418 null=false
 419 page_policy=open_adaptive
 420 range=0:536870911
 421 ranks_per_channel=2
 422 read_buffer_size=32
 423 static_backend_latency=10000
 424 static_frontend_latency=10000
 425 tBURST=5000
 426 tCCD_L=0
 427 tCK=1250
 428 tCL=13750
 429 tCS=2500
 430 tRAS=35000
 431 tRCD=13750
 432 tREFI=7800000
 433 tRFC=260000
 434 tRP=13750
 435 tRRD=6000
 436 tRRD_L=0
 437 tRTP=7500
 438 tRTW=2500
 439 tWR=15000
 440 tWTR=7500
 441 tXAW=30000
 442 tXP=0
 443 tXPDLL=0
 444 tXS=0
 445 tXSDLL=0
 446 write_buffer_size=64
 447 write_high_thresh_perc=85
 448 write_low_thresh_perc=50
 449 port=system.membus.master[0]
 450
 451 [system.membus]
 452 type=CoherentXBar
 453 clk_domain=system.clk_domain
 454 eventq_index=0
 455 forward_latency=4
 456 frontend_latency=3
 457 response_latency=2
 458 snoop_filter=Null
 459 snoop_response_latency=4
 460 system=system
 461 use_default_range=false
 462 width=16
 463 master=system.mem_ctrl.port
 464 slave=system.l2cache.mem_side system.system_port
 465