2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.147149 # Number of seconds simulated
4 sim_ticks 147148719500 # Number of ticks simulated
5 final_tick 147148719500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 682988 # Simulator instruction rate (inst/s)
8 host_op_rate 686382 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 1109563613 # Simulator tick rate (ticks/s)
10 host_mem_usage 443324 # Number of bytes of host memory used
11 host_seconds 132.62 # Real time elapsed on the host
12 sim_insts 90576862 # Number of instructions simulated
13 sim_ops 91026991 # Number of ops (including micro ops) simulated
14 system.voltage_domain.voltage 1 # Voltage in Volts
15 system.clk_domain.clock 1000 # Clock period in ticks
16 system.physmem.bytes_read::cpu.inst 36928 # Number of bytes read from this memory
17 system.physmem.bytes_read::cpu.data 944832 # Number of bytes read from this memory
18 system.physmem.bytes_read::total 981760 # Number of bytes read from this memory
19 system.physmem.bytes_inst_read::cpu.inst 36928 # Number of instructions bytes read from this memory
20 system.physmem.bytes_inst_read::total 36928 # Number of instructions bytes read from this memory
21 system.physmem.num_reads::cpu.inst 577 # Number of read requests responded to by this memory
22 system.physmem.num_reads::cpu.data 14763 # Number of read requests responded to by this memory
23 system.physmem.num_reads::total 15340 # Number of read requests responded to by this memory
24 system.physmem.bw_read::cpu.inst 250957 # Total read bandwidth from this memory (bytes/s)
25 system.physmem.bw_read::cpu.data 6420933 # Total read bandwidth from this memory (bytes/s)
26 system.physmem.bw_read::total 6671890 # Total read bandwidth from this memory (bytes/s)
27 system.physmem.bw_inst_read::cpu.inst 250957 # Instruction read bandwidth from this memory (bytes/s)
28 system.physmem.bw_inst_read::total 250957 # Instruction read bandwidth from this memory (bytes/s)
29 system.physmem.bw_total::cpu.inst 250957 # Total bandwidth to/from this memory (bytes/s)
30 system.physmem.bw_total::cpu.data 6420933 # Total bandwidth to/from this memory (bytes/s)
31 system.physmem.bw_total::total 6671890 # Total bandwidth to/from this memory (bytes/s)
32 system.cpu_clk_domain.clock 500 # Clock period in ticks
33 system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
34 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
35 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
36 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
37 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
38 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
39 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
40 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
41 system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
42 system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
43 system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
44 system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
45 system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
46 system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
47 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
48 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
49 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
50 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
51 system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
52 system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
53 system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
54 system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
55 system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
56 system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
57 system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
58 system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
59 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
60 system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
61 system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
62 system.cpu.dtb.walker.walks 0 # Table walker walks requested
63 system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
64 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
65 system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
66 system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
67 system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
68 system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
69 system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
70 system.cpu.dtb.inst_hits 0 # ITB inst hits
71 system.cpu.dtb.inst_misses 0 # ITB inst misses
72 system.cpu.dtb.read_hits 0 # DTB read hits
73 system.cpu.dtb.read_misses 0 # DTB read misses
74 system.cpu.dtb.write_hits 0 # DTB write hits
75 system.cpu.dtb.write_misses 0 # DTB write misses
76 system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
77 system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
78 system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
79 system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
80 system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
81 system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
82 system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
83 system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
84 system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
85 system.cpu.dtb.read_accesses 0 # DTB read accesses
86 system.cpu.dtb.write_accesses 0 # DTB write accesses
87 system.cpu.dtb.inst_accesses 0 # ITB inst accesses
88 system.cpu.dtb.hits 0 # DTB hits
89 system.cpu.dtb.misses 0 # DTB misses
90 system.cpu.dtb.accesses 0 # DTB accesses
91 system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
92 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
93 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
94 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
95 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
96 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
97 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
98 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
99 system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
100 system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
101 system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
102 system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
103 system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
104 system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
105 system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
106 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
107 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
108 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
109 system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
110 system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
111 system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
112 system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
113 system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
114 system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
115 system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
116 system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
117 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
118 system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
119 system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
120 system.cpu.itb.walker.walks 0 # Table walker walks requested
121 system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
122 system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
123 system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
124 system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
125 system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
126 system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
127 system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
128 system.cpu.itb.inst_hits 0 # ITB inst hits
129 system.cpu.itb.inst_misses 0 # ITB inst misses
130 system.cpu.itb.read_hits 0 # DTB read hits
131 system.cpu.itb.read_misses 0 # DTB read misses
132 system.cpu.itb.write_hits 0 # DTB write hits
133 system.cpu.itb.write_misses 0 # DTB write misses
134 system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
135 system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
136 system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
137 system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
138 system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
139 system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
140 system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
141 system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
142 system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
143 system.cpu.itb.read_accesses 0 # DTB read accesses
144 system.cpu.itb.write_accesses 0 # DTB write accesses
145 system.cpu.itb.inst_accesses 0 # ITB inst accesses
146 system.cpu.itb.hits 0 # DTB hits
147 system.cpu.itb.misses 0 # DTB misses
148 system.cpu.itb.accesses 0 # DTB accesses
149 system.cpu.workload.num_syscalls 442 # Number of system calls
150 system.cpu.numCycles 294297439 # number of cpu cycles simulated
151 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
152 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
153 system.cpu.committedInsts 90576862 # Number of instructions committed
154 system.cpu.committedOps 91026991 # Number of ops (including micro ops) committed
155 system.cpu.num_int_alu_accesses 72326352 # Number of integer alu accesses
156 system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses
157 system.cpu.num_func_calls 112245 # number of times a function call or return occured
158 system.cpu.num_conditional_control_insts 15520157 # number of instructions that are conditional controls
159 system.cpu.num_int_insts 72326352 # number of integer instructions
160 system.cpu.num_fp_insts 48 # number of float instructions
161 system.cpu.num_int_register_reads 124237033 # number of times the integer registers were read
162 system.cpu.num_int_register_writes 52782988 # number of times the integer registers were written
163 system.cpu.num_fp_register_reads 54 # number of times the floating registers were read
164 system.cpu.num_fp_register_writes 30 # number of times the floating registers were written
165 system.cpu.num_cc_register_reads 339191621 # number of times the CC registers were read
166 system.cpu.num_cc_register_writes 53956115 # number of times the CC registers were written
167 system.cpu.num_mem_refs 27220755 # number of memory refs
168 system.cpu.num_load_insts 22475911 # Number of load instructions
169 system.cpu.num_store_insts 4744844 # Number of store instructions
170 system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
171 system.cpu.num_busy_cycles 294297438.998000 # Number of busy cycles
172 system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
173 system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
174 system.cpu.Branches 18732305 # Number of branches fetched
175 system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
176 system.cpu.op_class::IntAlu 63822829 70.09% 70.09% # Class of executed instruction
177 system.cpu.op_class::IntMult 10474 0.01% 70.10% # Class of executed instruction
178 system.cpu.op_class::IntDiv 0 0.00% 70.10% # Class of executed instruction
179 system.cpu.op_class::FloatAdd 0 0.00% 70.10% # Class of executed instruction
180 system.cpu.op_class::FloatCmp 0 0.00% 70.10% # Class of executed instruction
181 system.cpu.op_class::FloatCvt 0 0.00% 70.10% # Class of executed instruction
182 system.cpu.op_class::FloatMult 0 0.00% 70.10% # Class of executed instruction
183 system.cpu.op_class::FloatDiv 0 0.00% 70.10% # Class of executed instruction
184 system.cpu.op_class::FloatSqrt 0 0.00% 70.10% # Class of executed instruction
185 system.cpu.op_class::SimdAdd 0 0.00% 70.10% # Class of executed instruction
186 system.cpu.op_class::SimdAddAcc 0 0.00% 70.10% # Class of executed instruction
187 system.cpu.op_class::SimdAlu 0 0.00% 70.10% # Class of executed instruction
188 system.cpu.op_class::SimdCmp 0 0.00% 70.10% # Class of executed instruction
189 system.cpu.op_class::SimdCvt 0 0.00% 70.10% # Class of executed instruction
190 system.cpu.op_class::SimdMisc 0 0.00% 70.10% # Class of executed instruction
191 system.cpu.op_class::SimdMult 0 0.00% 70.10% # Class of executed instruction
192 system.cpu.op_class::SimdMultAcc 0 0.00% 70.10% # Class of executed instruction
193 system.cpu.op_class::SimdShift 0 0.00% 70.10% # Class of executed instruction
194 system.cpu.op_class::SimdShiftAcc 0 0.00% 70.10% # Class of executed instruction
195 system.cpu.op_class::SimdSqrt 0 0.00% 70.10% # Class of executed instruction
196 system.cpu.op_class::SimdFloatAdd 0 0.00% 70.10% # Class of executed instruction
197 system.cpu.op_class::SimdFloatAlu 0 0.00% 70.10% # Class of executed instruction
198 system.cpu.op_class::SimdFloatCmp 0 0.00% 70.10% # Class of executed instruction
199 system.cpu.op_class::SimdFloatCvt 6 0.00% 70.10% # Class of executed instruction
200 system.cpu.op_class::SimdFloatDiv 0 0.00% 70.10% # Class of executed instruction
201 system.cpu.op_class::SimdFloatMisc 15 0.00% 70.10% # Class of executed instruction
202 system.cpu.op_class::SimdFloatMult 0 0.00% 70.10% # Class of executed instruction
203 system.cpu.op_class::SimdFloatMultAcc 2 0.00% 70.10% # Class of executed instruction
204 system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.10% # Class of executed instruction
205 system.cpu.op_class::MemRead 22475911 24.68% 94.79% # Class of executed instruction
206 system.cpu.op_class::MemWrite 4744844 5.21% 100.00% # Class of executed instruction
207 system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
208 system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
209 system.cpu.op_class::total 91054081 # Class of executed instruction
210 system.cpu.dcache.tags.replacements 942702 # number of replacements
211 system.cpu.dcache.tags.tagsinuse 3565.478025 # Cycle average of tags in use
212 system.cpu.dcache.tags.total_refs 26253601 # Total number of references to valid blocks.
213 system.cpu.dcache.tags.sampled_refs 946798 # Sample count of references to valid blocks.
214 system.cpu.dcache.tags.avg_refs 27.728830 # Average number of references to valid blocks.
215 system.cpu.dcache.tags.warmup_cycle 54453325500 # Cycle when the warmup percentage was hit.
216 system.cpu.dcache.tags.occ_blocks::cpu.data 3565.478025 # Average occupied blocks per requestor
217 system.cpu.dcache.tags.occ_percent::cpu.data 0.870478 # Average percentage of cache occupancy
218 system.cpu.dcache.tags.occ_percent::total 0.870478 # Average percentage of cache occupancy
219 system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
220 system.cpu.dcache.tags.age_task_id_blocks_1024::0 120 # Occupied blocks per task id
221 system.cpu.dcache.tags.age_task_id_blocks_1024::1 1357 # Occupied blocks per task id
222 system.cpu.dcache.tags.age_task_id_blocks_1024::2 2563 # Occupied blocks per task id
223 system.cpu.dcache.tags.age_task_id_blocks_1024::3 56 # Occupied blocks per task id
224 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
225 system.cpu.dcache.tags.tag_accesses 55347598 # Number of tag accesses
226 system.cpu.dcache.tags.data_accesses 55347598 # Number of data accesses
227 system.cpu.dcache.ReadReq_hits::cpu.data 21556948 # number of ReadReq hits
228 system.cpu.dcache.ReadReq_hits::total 21556948 # number of ReadReq hits
229 system.cpu.dcache.WriteReq_hits::cpu.data 4688372 # number of WriteReq hits
230 system.cpu.dcache.WriteReq_hits::total 4688372 # number of WriteReq hits
231 system.cpu.dcache.SoftPFReq_hits::cpu.data 507 # number of SoftPFReq hits
232 system.cpu.dcache.SoftPFReq_hits::total 507 # number of SoftPFReq hits
233 system.cpu.dcache.LoadLockedReq_hits::cpu.data 3887 # number of LoadLockedReq hits
234 system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits
235 system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits
236 system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits
237 system.cpu.dcache.demand_hits::cpu.data 26245320 # number of demand (read+write) hits
238 system.cpu.dcache.demand_hits::total 26245320 # number of demand (read+write) hits
239 system.cpu.dcache.overall_hits::cpu.data 26245827 # number of overall hits
240 system.cpu.dcache.overall_hits::total 26245827 # number of overall hits
241 system.cpu.dcache.ReadReq_misses::cpu.data 900187 # number of ReadReq misses
242 system.cpu.dcache.ReadReq_misses::total 900187 # number of ReadReq misses
243 system.cpu.dcache.WriteReq_misses::cpu.data 46609 # number of WriteReq misses
244 system.cpu.dcache.WriteReq_misses::total 46609 # number of WriteReq misses
245 system.cpu.dcache.SoftPFReq_misses::cpu.data 3 # number of SoftPFReq misses
246 system.cpu.dcache.SoftPFReq_misses::total 3 # number of SoftPFReq misses
247 system.cpu.dcache.demand_misses::cpu.data 946796 # number of demand (read+write) misses
248 system.cpu.dcache.demand_misses::total 946796 # number of demand (read+write) misses
249 system.cpu.dcache.overall_misses::cpu.data 946799 # number of overall misses
250 system.cpu.dcache.overall_misses::total 946799 # number of overall misses
251 system.cpu.dcache.ReadReq_miss_latency::cpu.data 11713009000 # number of ReadReq miss cycles
252 system.cpu.dcache.ReadReq_miss_latency::total 11713009000 # number of ReadReq miss cycles
253 system.cpu.dcache.WriteReq_miss_latency::cpu.data 1319019500 # number of WriteReq miss cycles
254 system.cpu.dcache.WriteReq_miss_latency::total 1319019500 # number of WriteReq miss cycles
255 system.cpu.dcache.demand_miss_latency::cpu.data 13032028500 # number of demand (read+write) miss cycles
256 system.cpu.dcache.demand_miss_latency::total 13032028500 # number of demand (read+write) miss cycles
257 system.cpu.dcache.overall_miss_latency::cpu.data 13032028500 # number of overall miss cycles
258 system.cpu.dcache.overall_miss_latency::total 13032028500 # number of overall miss cycles
259 system.cpu.dcache.ReadReq_accesses::cpu.data 22457135 # number of ReadReq accesses(hits+misses)
260 system.cpu.dcache.ReadReq_accesses::total 22457135 # number of ReadReq accesses(hits+misses)
261 system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses)
262 system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses)
263 system.cpu.dcache.SoftPFReq_accesses::cpu.data 510 # number of SoftPFReq accesses(hits+misses)
264 system.cpu.dcache.SoftPFReq_accesses::total 510 # number of SoftPFReq accesses(hits+misses)
265 system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 # number of LoadLockedReq accesses(hits+misses)
266 system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses)
267 system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses)
268 system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses)
269 system.cpu.dcache.demand_accesses::cpu.data 27192116 # number of demand (read+write) accesses
270 system.cpu.dcache.demand_accesses::total 27192116 # number of demand (read+write) accesses
271 system.cpu.dcache.overall_accesses::cpu.data 27192626 # number of overall (read+write) accesses
272 system.cpu.dcache.overall_accesses::total 27192626 # number of overall (read+write) accesses
273 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040085 # miss rate for ReadReq accesses
274 system.cpu.dcache.ReadReq_miss_rate::total 0.040085 # miss rate for ReadReq accesses
275 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009844 # miss rate for WriteReq accesses
276 system.cpu.dcache.WriteReq_miss_rate::total 0.009844 # miss rate for WriteReq accesses
277 system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.005882 # miss rate for SoftPFReq accesses
278 system.cpu.dcache.SoftPFReq_miss_rate::total 0.005882 # miss rate for SoftPFReq accesses
279 system.cpu.dcache.demand_miss_rate::cpu.data 0.034819 # miss rate for demand accesses
280 system.cpu.dcache.demand_miss_rate::total 0.034819 # miss rate for demand accesses
281 system.cpu.dcache.overall_miss_rate::cpu.data 0.034818 # miss rate for overall accesses
282 system.cpu.dcache.overall_miss_rate::total 0.034818 # miss rate for overall accesses
283 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13011.750892 # average ReadReq miss latency
284 system.cpu.dcache.ReadReq_avg_miss_latency::total 13011.750892 # average ReadReq miss latency
285 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28299.673883 # average WriteReq miss latency
286 system.cpu.dcache.WriteReq_avg_miss_latency::total 28299.673883 # average WriteReq miss latency
287 system.cpu.dcache.demand_avg_miss_latency::cpu.data 13764.346808 # average overall miss latency
288 system.cpu.dcache.demand_avg_miss_latency::total 13764.346808 # average overall miss latency
289 system.cpu.dcache.overall_avg_miss_latency::cpu.data 13764.303194 # average overall miss latency
290 system.cpu.dcache.overall_avg_miss_latency::total 13764.303194 # average overall miss latency
291 system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
292 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
293 system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
294 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
295 system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
296 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
297 system.cpu.dcache.fast_writes 0 # number of fast writes performed
298 system.cpu.dcache.cache_copies 0 # number of cache copies performed
299 system.cpu.dcache.writebacks::writebacks 942334 # number of writebacks
300 system.cpu.dcache.writebacks::total 942334 # number of writebacks
301 system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits
302 system.cpu.dcache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits
303 system.cpu.dcache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits
304 system.cpu.dcache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits
305 system.cpu.dcache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits
306 system.cpu.dcache.overall_mshr_hits::total 1 # number of overall MSHR hits
307 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 900186 # number of ReadReq MSHR misses
308 system.cpu.dcache.ReadReq_mshr_misses::total 900186 # number of ReadReq MSHR misses
309 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46609 # number of WriteReq MSHR misses
310 system.cpu.dcache.WriteReq_mshr_misses::total 46609 # number of WriteReq MSHR misses
311 system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 3 # number of SoftPFReq MSHR misses
312 system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses
313 system.cpu.dcache.demand_mshr_misses::cpu.data 946795 # number of demand (read+write) MSHR misses
314 system.cpu.dcache.demand_mshr_misses::total 946795 # number of demand (read+write) MSHR misses
315 system.cpu.dcache.overall_mshr_misses::cpu.data 946798 # number of overall MSHR misses
316 system.cpu.dcache.overall_mshr_misses::total 946798 # number of overall MSHR misses
317 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10812776000 # number of ReadReq MSHR miss cycles
318 system.cpu.dcache.ReadReq_mshr_miss_latency::total 10812776000 # number of ReadReq MSHR miss cycles
319 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1272410500 # number of WriteReq MSHR miss cycles
320 system.cpu.dcache.WriteReq_mshr_miss_latency::total 1272410500 # number of WriteReq MSHR miss cycles
321 system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 134000 # number of SoftPFReq MSHR miss cycles
322 system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 134000 # number of SoftPFReq MSHR miss cycles
323 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12085186500 # number of demand (read+write) MSHR miss cycles
324 system.cpu.dcache.demand_mshr_miss_latency::total 12085186500 # number of demand (read+write) MSHR miss cycles
325 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12085320500 # number of overall MSHR miss cycles
326 system.cpu.dcache.overall_mshr_miss_latency::total 12085320500 # number of overall MSHR miss cycles
327 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040085 # mshr miss rate for ReadReq accesses
328 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040085 # mshr miss rate for ReadReq accesses
329 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009844 # mshr miss rate for WriteReq accesses
330 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009844 # mshr miss rate for WriteReq accesses
331 system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.005882 # mshr miss rate for SoftPFReq accesses
332 system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.005882 # mshr miss rate for SoftPFReq accesses
333 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034819 # mshr miss rate for demand accesses
334 system.cpu.dcache.demand_mshr_miss_rate::total 0.034819 # mshr miss rate for demand accesses
335 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034818 # mshr miss rate for overall accesses
336 system.cpu.dcache.overall_mshr_miss_rate::total 0.034818 # mshr miss rate for overall accesses
337 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12011.713135 # average ReadReq mshr miss latency
338 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12011.713135 # average ReadReq mshr miss latency
339 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27299.673883 # average WriteReq mshr miss latency
340 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27299.673883 # average WriteReq mshr miss latency
341 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 44666.666667 # average SoftPFReq mshr miss latency
342 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 44666.666667 # average SoftPFReq mshr miss latency
343 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12764.311704 # average overall mshr miss latency
344 system.cpu.dcache.demand_avg_mshr_miss_latency::total 12764.311704 # average overall mshr miss latency
345 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12764.412789 # average overall mshr miss latency
346 system.cpu.dcache.overall_avg_mshr_miss_latency::total 12764.412789 # average overall mshr miss latency
347 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
348 system.cpu.icache.tags.replacements 2 # number of replacements
349 system.cpu.icache.tags.tagsinuse 510.111710 # Cycle average of tags in use
350 system.cpu.icache.tags.total_refs 107830173 # Total number of references to valid blocks.
351 system.cpu.icache.tags.sampled_refs 599 # Sample count of references to valid blocks.
352 system.cpu.icache.tags.avg_refs 180016.983306 # Average number of references to valid blocks.
353 system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
354 system.cpu.icache.tags.occ_blocks::cpu.inst 510.111710 # Average occupied blocks per requestor
355 system.cpu.icache.tags.occ_percent::cpu.inst 0.249078 # Average percentage of cache occupancy
356 system.cpu.icache.tags.occ_percent::total 0.249078 # Average percentage of cache occupancy
357 system.cpu.icache.tags.occ_task_id_blocks::1024 597 # Occupied blocks per task id
358 system.cpu.icache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id
359 system.cpu.icache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id
360 system.cpu.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id
361 system.cpu.icache.tags.age_task_id_blocks_1024::4 552 # Occupied blocks per task id
362 system.cpu.icache.tags.occ_task_id_percent::1024 0.291504 # Percentage of cache occupancy per task id
363 system.cpu.icache.tags.tag_accesses 215662143 # Number of tag accesses
364 system.cpu.icache.tags.data_accesses 215662143 # Number of data accesses
365 system.cpu.icache.ReadReq_hits::cpu.inst 107830173 # number of ReadReq hits
366 system.cpu.icache.ReadReq_hits::total 107830173 # number of ReadReq hits
367 system.cpu.icache.demand_hits::cpu.inst 107830173 # number of demand (read+write) hits
368 system.cpu.icache.demand_hits::total 107830173 # number of demand (read+write) hits
369 system.cpu.icache.overall_hits::cpu.inst 107830173 # number of overall hits
370 system.cpu.icache.overall_hits::total 107830173 # number of overall hits
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372 system.cpu.icache.ReadReq_misses::total 599 # number of ReadReq misses
373 system.cpu.icache.demand_misses::cpu.inst 599 # number of demand (read+write) misses
374 system.cpu.icache.demand_misses::total 599 # number of demand (read+write) misses
375 system.cpu.icache.overall_misses::cpu.inst 599 # number of overall misses
376 system.cpu.icache.overall_misses::total 599 # number of overall misses
377 system.cpu.icache.ReadReq_miss_latency::cpu.inst 36093000 # number of ReadReq miss cycles
378 system.cpu.icache.ReadReq_miss_latency::total 36093000 # number of ReadReq miss cycles
379 system.cpu.icache.demand_miss_latency::cpu.inst 36093000 # number of demand (read+write) miss cycles
380 system.cpu.icache.demand_miss_latency::total 36093000 # number of demand (read+write) miss cycles
381 system.cpu.icache.overall_miss_latency::cpu.inst 36093000 # number of overall miss cycles
382 system.cpu.icache.overall_miss_latency::total 36093000 # number of overall miss cycles
383 system.cpu.icache.ReadReq_accesses::cpu.inst 107830772 # number of ReadReq accesses(hits+misses)
384 system.cpu.icache.ReadReq_accesses::total 107830772 # number of ReadReq accesses(hits+misses)
385 system.cpu.icache.demand_accesses::cpu.inst 107830772 # number of demand (read+write) accesses
386 system.cpu.icache.demand_accesses::total 107830772 # number of demand (read+write) accesses
387 system.cpu.icache.overall_accesses::cpu.inst 107830772 # number of overall (read+write) accesses
388 system.cpu.icache.overall_accesses::total 107830772 # number of overall (read+write) accesses
389 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000006 # miss rate for ReadReq accesses
390 system.cpu.icache.ReadReq_miss_rate::total 0.000006 # miss rate for ReadReq accesses
391 system.cpu.icache.demand_miss_rate::cpu.inst 0.000006 # miss rate for demand accesses
392 system.cpu.icache.demand_miss_rate::total 0.000006 # miss rate for demand accesses
393 system.cpu.icache.overall_miss_rate::cpu.inst 0.000006 # miss rate for overall accesses
394 system.cpu.icache.overall_miss_rate::total 0.000006 # miss rate for overall accesses
395 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 60255.425710 # average ReadReq miss latency
396 system.cpu.icache.ReadReq_avg_miss_latency::total 60255.425710 # average ReadReq miss latency
397 system.cpu.icache.demand_avg_miss_latency::cpu.inst 60255.425710 # average overall miss latency
398 system.cpu.icache.demand_avg_miss_latency::total 60255.425710 # average overall miss latency
399 system.cpu.icache.overall_avg_miss_latency::cpu.inst 60255.425710 # average overall miss latency
400 system.cpu.icache.overall_avg_miss_latency::total 60255.425710 # average overall miss latency
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402 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
403 system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
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405 system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
406 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
407 system.cpu.icache.fast_writes 0 # number of fast writes performed
408 system.cpu.icache.cache_copies 0 # number of cache copies performed
409 system.cpu.icache.writebacks::writebacks 2 # number of writebacks
410 system.cpu.icache.writebacks::total 2 # number of writebacks
411 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 599 # number of ReadReq MSHR misses
412 system.cpu.icache.ReadReq_mshr_misses::total 599 # number of ReadReq MSHR misses
413 system.cpu.icache.demand_mshr_misses::cpu.inst 599 # number of demand (read+write) MSHR misses
414 system.cpu.icache.demand_mshr_misses::total 599 # number of demand (read+write) MSHR misses
415 system.cpu.icache.overall_mshr_misses::cpu.inst 599 # number of overall MSHR misses
416 system.cpu.icache.overall_mshr_misses::total 599 # number of overall MSHR misses
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418 system.cpu.icache.ReadReq_mshr_miss_latency::total 35494000 # number of ReadReq MSHR miss cycles
419 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 35494000 # number of demand (read+write) MSHR miss cycles
420 system.cpu.icache.demand_mshr_miss_latency::total 35494000 # number of demand (read+write) MSHR miss cycles
421 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 35494000 # number of overall MSHR miss cycles
422 system.cpu.icache.overall_mshr_miss_latency::total 35494000 # number of overall MSHR miss cycles
423 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for ReadReq accesses
424 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000006 # mshr miss rate for ReadReq accesses
425 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for demand accesses
426 system.cpu.icache.demand_mshr_miss_rate::total 0.000006 # mshr miss rate for demand accesses
427 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for overall accesses
428 system.cpu.icache.overall_mshr_miss_rate::total 0.000006 # mshr miss rate for overall accesses
429 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 59255.425710 # average ReadReq mshr miss latency
430 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 59255.425710 # average ReadReq mshr miss latency
431 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 59255.425710 # average overall mshr miss latency
432 system.cpu.icache.demand_avg_mshr_miss_latency::total 59255.425710 # average overall mshr miss latency
433 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 59255.425710 # average overall mshr miss latency
434 system.cpu.icache.overall_avg_mshr_miss_latency::total 59255.425710 # average overall mshr miss latency
435 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
436 system.cpu.l2cache.tags.replacements 0 # number of replacements
437 system.cpu.l2cache.tags.tagsinuse 9564.658425 # Cycle average of tags in use
438 system.cpu.l2cache.tags.total_refs 1827433 # Total number of references to valid blocks.
439 system.cpu.l2cache.tags.sampled_refs 15323 # Sample count of references to valid blocks.
440 system.cpu.l2cache.tags.avg_refs 119.260784 # Average number of references to valid blocks.
441 system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
442 system.cpu.l2cache.tags.occ_blocks::writebacks 8876.269803 # Average occupied blocks per requestor
443 system.cpu.l2cache.tags.occ_blocks::cpu.inst 494.164592 # Average occupied blocks per requestor
444 system.cpu.l2cache.tags.occ_blocks::cpu.data 194.224030 # Average occupied blocks per requestor
445 system.cpu.l2cache.tags.occ_percent::writebacks 0.270882 # Average percentage of cache occupancy
446 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.015081 # Average percentage of cache occupancy
447 system.cpu.l2cache.tags.occ_percent::cpu.data 0.005927 # Average percentage of cache occupancy
448 system.cpu.l2cache.tags.occ_percent::total 0.291890 # Average percentage of cache occupancy
449 system.cpu.l2cache.tags.occ_task_id_blocks::1024 15323 # Occupied blocks per task id
450 system.cpu.l2cache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id
451 system.cpu.l2cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id
452 system.cpu.l2cache.tags.age_task_id_blocks_1024::2 100 # Occupied blocks per task id
453 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1473 # Occupied blocks per task id
454 system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13704 # Occupied blocks per task id
455 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.467621 # Percentage of cache occupancy per task id
456 system.cpu.l2cache.tags.tag_accesses 15181828 # Number of tag accesses
457 system.cpu.l2cache.tags.data_accesses 15181828 # Number of data accesses
458 system.cpu.l2cache.WritebackDirty_hits::writebacks 942334 # number of WritebackDirty hits
459 system.cpu.l2cache.WritebackDirty_hits::total 942334 # number of WritebackDirty hits
460 system.cpu.l2cache.WritebackClean_hits::writebacks 1 # number of WritebackClean hits
461 system.cpu.l2cache.WritebackClean_hits::total 1 # number of WritebackClean hits
462 system.cpu.l2cache.ReadExReq_hits::cpu.data 32061 # number of ReadExReq hits
463 system.cpu.l2cache.ReadExReq_hits::total 32061 # number of ReadExReq hits
464 system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 22 # number of ReadCleanReq hits
465 system.cpu.l2cache.ReadCleanReq_hits::total 22 # number of ReadCleanReq hits
466 system.cpu.l2cache.ReadSharedReq_hits::cpu.data 899974 # number of ReadSharedReq hits
467 system.cpu.l2cache.ReadSharedReq_hits::total 899974 # number of ReadSharedReq hits
468 system.cpu.l2cache.demand_hits::cpu.inst 22 # number of demand (read+write) hits
469 system.cpu.l2cache.demand_hits::cpu.data 932035 # number of demand (read+write) hits
470 system.cpu.l2cache.demand_hits::total 932057 # number of demand (read+write) hits
471 system.cpu.l2cache.overall_hits::cpu.inst 22 # number of overall hits
472 system.cpu.l2cache.overall_hits::cpu.data 932035 # number of overall hits
473 system.cpu.l2cache.overall_hits::total 932057 # number of overall hits
474 system.cpu.l2cache.ReadExReq_misses::cpu.data 14548 # number of ReadExReq misses
475 system.cpu.l2cache.ReadExReq_misses::total 14548 # number of ReadExReq misses
476 system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 577 # number of ReadCleanReq misses
477 system.cpu.l2cache.ReadCleanReq_misses::total 577 # number of ReadCleanReq misses
478 system.cpu.l2cache.ReadSharedReq_misses::cpu.data 215 # number of ReadSharedReq misses
479 system.cpu.l2cache.ReadSharedReq_misses::total 215 # number of ReadSharedReq misses
480 system.cpu.l2cache.demand_misses::cpu.inst 577 # number of demand (read+write) misses
481 system.cpu.l2cache.demand_misses::cpu.data 14763 # number of demand (read+write) misses
482 system.cpu.l2cache.demand_misses::total 15340 # number of demand (read+write) misses
483 system.cpu.l2cache.overall_misses::cpu.inst 577 # number of overall misses
484 system.cpu.l2cache.overall_misses::cpu.data 14763 # number of overall misses
485 system.cpu.l2cache.overall_misses::total 15340 # number of overall misses
486 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 865856500 # number of ReadExReq miss cycles
487 system.cpu.l2cache.ReadExReq_miss_latency::total 865856500 # number of ReadExReq miss cycles
488 system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 34343500 # number of ReadCleanReq miss cycles
489 system.cpu.l2cache.ReadCleanReq_miss_latency::total 34343500 # number of ReadCleanReq miss cycles
490 system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 12794500 # number of ReadSharedReq miss cycles
491 system.cpu.l2cache.ReadSharedReq_miss_latency::total 12794500 # number of ReadSharedReq miss cycles
492 system.cpu.l2cache.demand_miss_latency::cpu.inst 34343500 # number of demand (read+write) miss cycles
493 system.cpu.l2cache.demand_miss_latency::cpu.data 878651000 # number of demand (read+write) miss cycles
494 system.cpu.l2cache.demand_miss_latency::total 912994500 # number of demand (read+write) miss cycles
495 system.cpu.l2cache.overall_miss_latency::cpu.inst 34343500 # number of overall miss cycles
496 system.cpu.l2cache.overall_miss_latency::cpu.data 878651000 # number of overall miss cycles
497 system.cpu.l2cache.overall_miss_latency::total 912994500 # number of overall miss cycles
498 system.cpu.l2cache.WritebackDirty_accesses::writebacks 942334 # number of WritebackDirty accesses(hits+misses)
499 system.cpu.l2cache.WritebackDirty_accesses::total 942334 # number of WritebackDirty accesses(hits+misses)
500 system.cpu.l2cache.WritebackClean_accesses::writebacks 1 # number of WritebackClean accesses(hits+misses)
501 system.cpu.l2cache.WritebackClean_accesses::total 1 # number of WritebackClean accesses(hits+misses)
502 system.cpu.l2cache.ReadExReq_accesses::cpu.data 46609 # number of ReadExReq accesses(hits+misses)
503 system.cpu.l2cache.ReadExReq_accesses::total 46609 # number of ReadExReq accesses(hits+misses)
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505 system.cpu.l2cache.ReadCleanReq_accesses::total 599 # number of ReadCleanReq accesses(hits+misses)
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507 system.cpu.l2cache.ReadSharedReq_accesses::total 900189 # number of ReadSharedReq accesses(hits+misses)
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512 system.cpu.l2cache.overall_accesses::cpu.data 946798 # number of overall (read+write) accesses
513 system.cpu.l2cache.overall_accesses::total 947397 # number of overall (read+write) accesses
514 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.312129 # miss rate for ReadExReq accesses
515 system.cpu.l2cache.ReadExReq_miss_rate::total 0.312129 # miss rate for ReadExReq accesses
516 system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.963272 # miss rate for ReadCleanReq accesses
517 system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.963272 # miss rate for ReadCleanReq accesses
518 system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000239 # miss rate for ReadSharedReq accesses
519 system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000239 # miss rate for ReadSharedReq accesses
520 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.963272 # miss rate for demand accesses
521 system.cpu.l2cache.demand_miss_rate::cpu.data 0.015593 # miss rate for demand accesses
522 system.cpu.l2cache.demand_miss_rate::total 0.016192 # miss rate for demand accesses
523 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.963272 # miss rate for overall accesses
524 system.cpu.l2cache.overall_miss_rate::cpu.data 0.015593 # miss rate for overall accesses
525 system.cpu.l2cache.overall_miss_rate::total 0.016192 # miss rate for overall accesses
526 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59517.218862 # average ReadExReq miss latency
527 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59517.218862 # average ReadExReq miss latency
528 system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59520.797227 # average ReadCleanReq miss latency
529 system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59520.797227 # average ReadCleanReq miss latency
530 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59509.302326 # average ReadSharedReq miss latency
531 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59509.302326 # average ReadSharedReq miss latency
532 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59520.797227 # average overall miss latency
533 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59517.103570 # average overall miss latency
534 system.cpu.l2cache.demand_avg_miss_latency::total 59517.242503 # average overall miss latency
535 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59520.797227 # average overall miss latency
536 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59517.103570 # average overall miss latency
537 system.cpu.l2cache.overall_avg_miss_latency::total 59517.242503 # average overall miss latency
538 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
539 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
540 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
541 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
542 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
543 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
544 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
545 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
546 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14548 # number of ReadExReq MSHR misses
547 system.cpu.l2cache.ReadExReq_mshr_misses::total 14548 # number of ReadExReq MSHR misses
548 system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 577 # number of ReadCleanReq MSHR misses
549 system.cpu.l2cache.ReadCleanReq_mshr_misses::total 577 # number of ReadCleanReq MSHR misses
550 system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 215 # number of ReadSharedReq MSHR misses
551 system.cpu.l2cache.ReadSharedReq_mshr_misses::total 215 # number of ReadSharedReq MSHR misses
552 system.cpu.l2cache.demand_mshr_misses::cpu.inst 577 # number of demand (read+write) MSHR misses
553 system.cpu.l2cache.demand_mshr_misses::cpu.data 14763 # number of demand (read+write) MSHR misses
554 system.cpu.l2cache.demand_mshr_misses::total 15340 # number of demand (read+write) MSHR misses
555 system.cpu.l2cache.overall_mshr_misses::cpu.inst 577 # number of overall MSHR misses
556 system.cpu.l2cache.overall_mshr_misses::cpu.data 14763 # number of overall MSHR misses
557 system.cpu.l2cache.overall_mshr_misses::total 15340 # number of overall MSHR misses
558 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 720376500 # number of ReadExReq MSHR miss cycles
559 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 720376500 # number of ReadExReq MSHR miss cycles
560 system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 28573500 # number of ReadCleanReq MSHR miss cycles
561 system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 28573500 # number of ReadCleanReq MSHR miss cycles
562 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 10644500 # number of ReadSharedReq MSHR miss cycles
563 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 10644500 # number of ReadSharedReq MSHR miss cycles
564 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 28573500 # number of demand (read+write) MSHR miss cycles
565 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 731021000 # number of demand (read+write) MSHR miss cycles
566 system.cpu.l2cache.demand_mshr_miss_latency::total 759594500 # number of demand (read+write) MSHR miss cycles
567 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 28573500 # number of overall MSHR miss cycles
568 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 731021000 # number of overall MSHR miss cycles
569 system.cpu.l2cache.overall_mshr_miss_latency::total 759594500 # number of overall MSHR miss cycles
570 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.312129 # mshr miss rate for ReadExReq accesses
571 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.312129 # mshr miss rate for ReadExReq accesses
572 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.963272 # mshr miss rate for ReadCleanReq accesses
573 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.963272 # mshr miss rate for ReadCleanReq accesses
574 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000239 # mshr miss rate for ReadSharedReq accesses
575 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000239 # mshr miss rate for ReadSharedReq accesses
576 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.963272 # mshr miss rate for demand accesses
577 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015593 # mshr miss rate for demand accesses
578 system.cpu.l2cache.demand_mshr_miss_rate::total 0.016192 # mshr miss rate for demand accesses
579 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.963272 # mshr miss rate for overall accesses
580 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015593 # mshr miss rate for overall accesses
581 system.cpu.l2cache.overall_mshr_miss_rate::total 0.016192 # mshr miss rate for overall accesses
582 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49517.218862 # average ReadExReq mshr miss latency
583 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49517.218862 # average ReadExReq mshr miss latency
584 system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49520.797227 # average ReadCleanReq mshr miss latency
585 system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49520.797227 # average ReadCleanReq mshr miss latency
586 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49509.302326 # average ReadSharedReq mshr miss latency
587 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49509.302326 # average ReadSharedReq mshr miss latency
588 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49520.797227 # average overall mshr miss latency
589 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49517.103570 # average overall mshr miss latency
590 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49517.242503 # average overall mshr miss latency
591 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49520.797227 # average overall mshr miss latency
592 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49517.103570 # average overall mshr miss latency
593 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49517.242503 # average overall mshr miss latency
594 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
595 system.cpu.toL2Bus.snoop_filter.tot_requests 1890101 # Total number of requests made to the snoop filter.
596 system.cpu.toL2Bus.snoop_filter.hit_single_requests 942715 # Number of requests hitting in the snoop filter with a single holder of the requested data.
597 system.cpu.toL2Bus.snoop_filter.hit_multi_requests 114 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
598 system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
599 system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
600 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
601 system.cpu.toL2Bus.trans_dist::ReadResp 900788 # Transaction distribution
602 system.cpu.toL2Bus.trans_dist::WritebackDirty 942334 # Transaction distribution
603 system.cpu.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution
604 system.cpu.toL2Bus.trans_dist::CleanEvict 255 # Transaction distribution
605 system.cpu.toL2Bus.trans_dist::ReadExReq 46609 # Transaction distribution
606 system.cpu.toL2Bus.trans_dist::ReadExResp 46609 # Transaction distribution
607 system.cpu.toL2Bus.trans_dist::ReadCleanReq 599 # Transaction distribution
608 system.cpu.toL2Bus.trans_dist::ReadSharedReq 900189 # Transaction distribution
609 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1199 # Packet count per connected master and slave (bytes)
610 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2836185 # Packet count per connected master and slave (bytes)
611 system.cpu.toL2Bus.pkt_count::total 2837384 # Packet count per connected master and slave (bytes)
612 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 38400 # Cumulative packet size per connected master and slave (bytes)
613 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 120904448 # Cumulative packet size per connected master and slave (bytes)
614 system.cpu.toL2Bus.pkt_size::total 120942848 # Cumulative packet size per connected master and slave (bytes)
615 system.cpu.toL2Bus.snoops 0 # Total snoops (count)
616 system.cpu.toL2Bus.snoop_fanout::samples 947397 # Request fanout histogram
617 system.cpu.toL2Bus.snoop_fanout::mean 0.000132 # Request fanout histogram
618 system.cpu.toL2Bus.snoop_fanout::stdev 0.011486 # Request fanout histogram
619 system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
620 system.cpu.toL2Bus.snoop_fanout::0 947272 99.99% 99.99% # Request fanout histogram
621 system.cpu.toL2Bus.snoop_fanout::1 125 0.01% 100.00% # Request fanout histogram
622 system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
623 system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
624 system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
625 system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
626 system.cpu.toL2Bus.snoop_fanout::total 947397 # Request fanout histogram
627 system.cpu.toL2Bus.reqLayer0.occupancy 1887386500 # Layer occupancy (ticks)
628 system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%)
629 system.cpu.toL2Bus.respLayer0.occupancy 898500 # Layer occupancy (ticks)
630 system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
631 system.cpu.toL2Bus.respLayer1.occupancy 1420197000 # Layer occupancy (ticks)
632 system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%)
633 system.membus.trans_dist::ReadResp 792 # Transaction distribution
634 system.membus.trans_dist::ReadExReq 14548 # Transaction distribution
635 system.membus.trans_dist::ReadExResp 14548 # Transaction distribution
636 system.membus.trans_dist::ReadSharedReq 792 # Transaction distribution
637 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 30680 # Packet count per connected master and slave (bytes)
638 system.membus.pkt_count::total 30680 # Packet count per connected master and slave (bytes)
639 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 981760 # Cumulative packet size per connected master and slave (bytes)
640 system.membus.pkt_size::total 981760 # Cumulative packet size per connected master and slave (bytes)
641 system.membus.snoops 0 # Total snoops (count)
642 system.membus.snoop_fanout::samples 15340 # Request fanout histogram
643 system.membus.snoop_fanout::mean 0 # Request fanout histogram
644 system.membus.snoop_fanout::stdev 0 # Request fanout histogram
645 system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
646 system.membus.snoop_fanout::0 15340 100.00% 100.00% # Request fanout histogram
647 system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
648 system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
649 system.membus.snoop_fanout::min_value 0 # Request fanout histogram
650 system.membus.snoop_fanout::max_value 0 # Request fanout histogram
651 system.membus.snoop_fanout::total 15340 # Request fanout histogram
652 system.membus.reqLayer0.occupancy 15604500 # Layer occupancy (ticks)
653 system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
654 system.membus.respLayer1.occupancy 76700000 # Layer occupancy (ticks)
655 system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
657 ---------- End Simulation Statistics ----------
projects / gem5.git / blob