tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.json

   1 {
   2     "name": null,
   3     "sim_quantum": 0,
   4     "system": {
   5         "kernel": "",
   6         "mmap_using_noreserve": false,
   7         "kernel_addr_check": true,
   8         "membus": {
   9             "slave": {
  10                 "peer": [
  11                     "system.system_port",
  12                     "system.cpu.l2cache.mem_side"
  13                 ],
  14                 "role": "SLAVE"
  15             },
  16             "name": "membus",
  17             "snoop_filter": null,
  18             "forward_latency": 4,
  19             "clk_domain": "system.clk_domain",
  20             "system": "system",
  21             "width": 16,
  22             "eventq_index": 0,
  23             "master": {
  24                 "peer": [
  25                     "system.physmem.port"
  26                 ],
  27                 "role": "MASTER"
  28             },
  29             "response_latency": 2,
  30             "cxx_class": "CoherentXBar",
  31             "path": "system.membus",
  32             "snoop_response_latency": 4,
  33             "type": "CoherentXBar",
  34             "use_default_range": false,
  35             "frontend_latency": 3
  36         },
  37         "symbolfile": "",
  38         "readfile": "",
  39         "cxx_class": "System",
  40         "load_offset": 0,
  41         "work_end_ckpt_count": 0,
  42         "memories": [
  43             "system.physmem"
  44         ],
  45         "work_begin_ckpt_count": 0,
  46         "clk_domain": {
  47             "name": "clk_domain",
  48             "clock": [
  49                 1000
  50             ],
  51             "init_perf_level": 0,
  52             "voltage_domain": "system.voltage_domain",
  53             "eventq_index": 0,
  54             "cxx_class": "SrcClockDomain",
  55             "path": "system.clk_domain",
  56             "type": "SrcClockDomain",
  57             "domain_id": -1
  58         },
  59         "mem_ranges": [],
  60         "eventq_index": 0,
  61         "dvfs_handler": {
  62             "enable": false,
  63             "name": "dvfs_handler",
  64             "sys_clk_domain": "system.clk_domain",
  65             "transition_latency": 100000000,
  66             "eventq_index": 0,
  67             "cxx_class": "DVFSHandler",
  68             "domains": [],
  69             "path": "system.dvfs_handler",
  70             "type": "DVFSHandler"
  71         },
  72         "work_end_exit_count": 0,
  73         "type": "System",
  74         "voltage_domain": {
  75             "name": "voltage_domain",
  76             "eventq_index": 0,
  77             "voltage": [
  78                 "1.0"
  79             ],
  80             "cxx_class": "VoltageDomain",
  81             "path": "system.voltage_domain",
  82             "type": "VoltageDomain"
  83         },
  84         "cache_line_size": 64,
  85         "boot_osflags": "a",
  86         "physmem": {
  87             "range": "0:134217727",
  88             "latency": 30000,
  89             "name": "physmem",
  90             "eventq_index": 0,
  91             "clk_domain": "system.clk_domain",
  92             "latency_var": 0,
  93             "bandwidth": "73.000000",
  94             "conf_table_reported": true,
  95             "cxx_class": "SimpleMemory",
  96             "path": "system.physmem",
  97             "null": false,
  98             "type": "SimpleMemory",
  99             "port": {
 100                 "peer": "system.membus.master[0]",
 101                 "role": "SLAVE"
 102             },
 103             "in_addr_map": true
 104         },
 105         "work_cpus_ckpt_count": 0,
 106         "work_begin_exit_count": 0,
 107         "path": "system",
 108         "cpu_clk_domain": {
 109             "name": "cpu_clk_domain",
 110             "clock": [
 111                 500
 112             ],
 113             "init_perf_level": 0,
 114             "voltage_domain": "system.voltage_domain",
 115             "eventq_index": 0,
 116             "cxx_class": "SrcClockDomain",
 117             "path": "system.cpu_clk_domain",
 118             "type": "SrcClockDomain",
 119             "domain_id": -1
 120         },
 121         "mem_mode": "timing",
 122         "name": "system",
 123         "init_param": 0,
 124         "system_port": {
 125             "peer": "system.membus.slave[0]",
 126             "role": "MASTER"
 127         },
 128         "load_addr_mask": 1099511627775,
 129         "cpu": [
 130             {
 131                 "do_statistics_insts": true,
 132                 "numThreads": 1,
 133                 "itb": {
 134                     "name": "itb",
 135                     "eventq_index": 0,
 136                     "cxx_class": "AlphaISA::TLB",
 137                     "path": "system.cpu.itb",
 138                     "type": "AlphaTLB",
 139                     "size": 48
 140                 },
 141                 "system": "system",
 142                 "function_trace": false,
 143                 "do_checkpoint_insts": true,
 144                 "cxx_class": "TimingSimpleCPU",
 145                 "max_loads_all_threads": 0,
 146                 "clk_domain": "system.cpu_clk_domain",
 147                 "function_trace_start": 0,
 148                 "cpu_id": 0,
 149                 "checker": null,
 150                 "eventq_index": 0,
 151                 "toL2Bus": {
 152                     "slave": {
 153                         "peer": [
 154                             "system.cpu.icache.mem_side",
 155                             "system.cpu.dcache.mem_side"
 156                         ],
 157                         "role": "SLAVE"
 158                     },
 159                     "name": "toL2Bus",
 160                     "snoop_filter": {
 161                         "name": "snoop_filter",
 162                         "system": "system",
 163                         "max_capacity": 8388608,
 164                         "eventq_index": 0,
 165                         "cxx_class": "SnoopFilter",
 166                         "path": "system.cpu.toL2Bus.snoop_filter",
 167                         "type": "SnoopFilter",
 168                         "lookup_latency": 0
 169                     },
 170                     "forward_latency": 0,
 171                     "clk_domain": "system.cpu_clk_domain",
 172                     "system": "system",
 173                     "width": 32,
 174                     "eventq_index": 0,
 175                     "master": {
 176                         "peer": [
 177                             "system.cpu.l2cache.cpu_side"
 178                         ],
 179                         "role": "MASTER"
 180                     },
 181                     "response_latency": 1,
 182                     "cxx_class": "CoherentXBar",
 183                     "path": "system.cpu.toL2Bus",
 184                     "snoop_response_latency": 1,
 185                     "type": "CoherentXBar",
 186                     "use_default_range": false,
 187                     "frontend_latency": 1
 188                 },
 189                 "do_quiesce": true,
 190                 "type": "TimingSimpleCPU",
 191                 "profile": 0,
 192                 "icache_port": {
 193                     "peer": "system.cpu.icache.cpu_side",
 194                     "role": "MASTER"
 195                 },
 196                 "icache": {
 197                     "cpu_side": {
 198                         "peer": "system.cpu.icache_port",
 199                         "role": "SLAVE"
 200                     },
 201                     "prefetcher": null,
 202                     "clk_domain": "system.cpu_clk_domain",
 203                     "write_buffers": 8,
 204                     "response_latency": 2,
 205                     "cxx_class": "Cache",
 206                     "size": 131072,
 207                     "tags": {
 208                         "name": "tags",
 209                         "eventq_index": 0,
 210                         "hit_latency": 2,
 211                         "clk_domain": "system.cpu_clk_domain",
 212                         "sequential_access": false,
 213                         "assoc": 2,
 214                         "cxx_class": "LRU",
 215                         "path": "system.cpu.icache.tags",
 216                         "block_size": 64,
 217                         "type": "LRU",
 218                         "size": 131072
 219                     },
 220                     "system": "system",
 221                     "max_miss_count": 0,
 222                     "eventq_index": 0,
 223                     "mem_side": {
 224                         "peer": "system.cpu.toL2Bus.slave[0]",
 225                         "role": "MASTER"
 226                     },
 227                     "mshrs": 4,
 228                     "forward_snoops": true,
 229                     "hit_latency": 2,
 230                     "demand_mshr_reserve": 1,
 231                     "tgts_per_mshr": 20,
 232                     "addr_ranges": [
 233                         "0:18446744073709551615"
 234                     ],
 235                     "is_read_only": true,
 236                     "prefetch_on_access": false,
 237                     "path": "system.cpu.icache",
 238                     "name": "icache",
 239                     "type": "Cache",
 240                     "sequential_access": false,
 241                     "assoc": 2
 242                 },
 243                 "interrupts": [
 244                     {
 245                         "eventq_index": 0,
 246                         "path": "system.cpu.interrupts",
 247                         "type": "AlphaInterrupts",
 248                         "name": "interrupts",
 249                         "cxx_class": "AlphaISA::Interrupts"
 250                     }
 251                 ],
 252                 "dcache_port": {
 253                     "peer": "system.cpu.dcache.cpu_side",
 254                     "role": "MASTER"
 255                 },
 256                 "socket_id": 0,
 257                 "max_insts_all_threads": 0,
 258                 "l2cache": {
 259                     "cpu_side": {
 260                         "peer": "system.cpu.toL2Bus.master[0]",
 261                         "role": "SLAVE"
 262                     },
 263                     "prefetcher": null,
 264                     "clk_domain": "system.cpu_clk_domain",
 265                     "write_buffers": 8,
 266                     "response_latency": 20,
 267                     "cxx_class": "Cache",
 268                     "size": 2097152,
 269                     "tags": {
 270                         "name": "tags",
 271                         "eventq_index": 0,
 272                         "hit_latency": 20,
 273                         "clk_domain": "system.cpu_clk_domain",
 274                         "sequential_access": false,
 275                         "assoc": 8,
 276                         "cxx_class": "LRU",
 277                         "path": "system.cpu.l2cache.tags",
 278                         "block_size": 64,
 279                         "type": "LRU",
 280                         "size": 2097152
 281                     },
 282                     "system": "system",
 283                     "max_miss_count": 0,
 284                     "eventq_index": 0,
 285                     "mem_side": {
 286                         "peer": "system.membus.slave[1]",
 287                         "role": "MASTER"
 288                     },
 289                     "mshrs": 20,
 290                     "forward_snoops": true,
 291                     "hit_latency": 20,
 292                     "demand_mshr_reserve": 1,
 293                     "tgts_per_mshr": 12,
 294                     "addr_ranges": [
 295                         "0:18446744073709551615"
 296                     ],
 297                     "is_read_only": false,
 298                     "prefetch_on_access": false,
 299                     "path": "system.cpu.l2cache",
 300                     "name": "l2cache",
 301                     "type": "Cache",
 302                     "sequential_access": false,
 303                     "assoc": 8
 304                 },
 305                 "path": "system.cpu",
 306                 "max_loads_any_thread": 0,
 307                 "switched_out": false,
 308                 "workload": [
 309                     {
 310                         "name": "workload",
 311                         "output": "cout",
 312                         "chkpt": "",
 313                         "errout": "cerr",
 314                         "kvmInSE": false,
 315                         "system": "system",
 316                         "useArchPT": false,
 317                         "eventq_index": 0,
 318                         "file": "/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz",
 319                         "cxx_class": "EioProcess",
 320                         "path": "system.cpu.workload",
 321                         "max_stack_size": 67108864,
 322                         "type": "EioProcess",
 323                         "input": "cin"
 324                     }
 325                 ],
 326                 "name": "cpu",
 327                 "dtb": {
 328                     "name": "dtb",
 329                     "eventq_index": 0,
 330                     "cxx_class": "AlphaISA::TLB",
 331                     "path": "system.cpu.dtb",
 332                     "type": "AlphaTLB",
 333                     "size": 64
 334                 },
 335                 "simpoint_start_insts": [],
 336                 "max_insts_any_thread": 500000,
 337                 "progress_interval": 0,
 338                 "branchPred": null,
 339                 "dcache": {
 340                     "cpu_side": {
 341                         "peer": "system.cpu.dcache_port",
 342                         "role": "SLAVE"
 343                     },
 344                     "prefetcher": null,
 345                     "clk_domain": "system.cpu_clk_domain",
 346                     "write_buffers": 8,
 347                     "response_latency": 2,
 348                     "cxx_class": "Cache",
 349                     "size": 262144,
 350                     "tags": {
 351                         "name": "tags",
 352                         "eventq_index": 0,
 353                         "hit_latency": 2,
 354                         "clk_domain": "system.cpu_clk_domain",
 355                         "sequential_access": false,
 356                         "assoc": 2,
 357                         "cxx_class": "LRU",
 358                         "path": "system.cpu.dcache.tags",
 359                         "block_size": 64,
 360                         "type": "LRU",
 361                         "size": 262144
 362                     },
 363                     "system": "system",
 364                     "max_miss_count": 0,
 365                     "eventq_index": 0,
 366                     "mem_side": {
 367                         "peer": "system.cpu.toL2Bus.slave[1]",
 368                         "role": "MASTER"
 369                     },
 370                     "mshrs": 4,
 371                     "forward_snoops": true,
 372                     "hit_latency": 2,
 373                     "demand_mshr_reserve": 1,
 374                     "tgts_per_mshr": 20,
 375                     "addr_ranges": [
 376                         "0:18446744073709551615"
 377                     ],
 378                     "is_read_only": false,
 379                     "prefetch_on_access": false,
 380                     "path": "system.cpu.dcache",
 381                     "name": "dcache",
 382                     "type": "Cache",
 383                     "sequential_access": false,
 384                     "assoc": 2
 385                 },
 386                 "isa": [
 387                     {
 388                         "name": "isa",
 389                         "system": "system",
 390                         "eventq_index": 0,
 391                         "cxx_class": "AlphaISA::ISA",
 392                         "path": "system.cpu.isa",
 393                         "type": "AlphaISA"
 394                     }
 395                 ],
 396                 "tracer": {
 397                     "eventq_index": 0,
 398                     "path": "system.cpu.tracer",
 399                     "type": "ExeTracer",
 400                     "name": "tracer",
 401                     "cxx_class": "Trace::ExeTracer"
 402                 }
 403             }
 404         ],
 405         "multi_thread": false,
 406         "work_begin_cpu_id_exit": -1,
 407         "work_item_id": -1,
 408         "num_work_ids": 16
 409     },
 410     "time_sync_period": 100000000000,
 411     "eventq_index": 0,
 412     "time_sync_spin_threshold": 100000000,
 413     "cxx_class": "Root",
 414     "path": "root",
 415     "time_sync_enable": false,
 416     "type": "Root",
 417     "full_system": false
 418 }