2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.000729 # Number of seconds simulated
4 sim_ticks 729024000 # Number of ticks simulated
5 final_tick 729024000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 1420709 # Simulator instruction rate (inst/s)
8 host_op_rate 1420692 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 517863701 # Simulator tick rate (ticks/s)
10 host_mem_usage 236964 # Number of bytes of host memory used
11 host_seconds 1.41 # Real time elapsed on the host
12 sim_insts 1999959 # Number of instructions simulated
13 sim_ops 1999959 # Number of ops (including micro ops) simulated
14 system.physmem.bytes_read::cpu0.inst 25792 # Number of bytes read from this memory
15 system.physmem.bytes_read::cpu0.data 29056 # Number of bytes read from this memory
16 system.physmem.bytes_read::cpu1.inst 25792 # Number of bytes read from this memory
17 system.physmem.bytes_read::cpu1.data 29056 # Number of bytes read from this memory
18 system.physmem.bytes_read::cpu2.inst 25792 # Number of bytes read from this memory
19 system.physmem.bytes_read::cpu2.data 29056 # Number of bytes read from this memory
20 system.physmem.bytes_read::cpu3.inst 25792 # Number of bytes read from this memory
21 system.physmem.bytes_read::cpu3.data 29056 # Number of bytes read from this memory
22 system.physmem.bytes_read::total 219392 # Number of bytes read from this memory
23 system.physmem.bytes_inst_read::cpu0.inst 25792 # Number of instructions bytes read from this memory
24 system.physmem.bytes_inst_read::cpu1.inst 25792 # Number of instructions bytes read from this memory
25 system.physmem.bytes_inst_read::cpu2.inst 25792 # Number of instructions bytes read from this memory
26 system.physmem.bytes_inst_read::cpu3.inst 25792 # Number of instructions bytes read from this memory
27 system.physmem.bytes_inst_read::total 103168 # Number of instructions bytes read from this memory
28 system.physmem.num_reads::cpu0.inst 403 # Number of read requests responded to by this memory
29 system.physmem.num_reads::cpu0.data 454 # Number of read requests responded to by this memory
30 system.physmem.num_reads::cpu1.inst 403 # Number of read requests responded to by this memory
31 system.physmem.num_reads::cpu1.data 454 # Number of read requests responded to by this memory
32 system.physmem.num_reads::cpu2.inst 403 # Number of read requests responded to by this memory
33 system.physmem.num_reads::cpu2.data 454 # Number of read requests responded to by this memory
34 system.physmem.num_reads::cpu3.inst 403 # Number of read requests responded to by this memory
35 system.physmem.num_reads::cpu3.data 454 # Number of read requests responded to by this memory
36 system.physmem.num_reads::total 3428 # Number of read requests responded to by this memory
37 system.physmem.bw_read::cpu0.inst 35378808 # Total read bandwidth from this memory (bytes/s)
38 system.physmem.bw_read::cpu0.data 39856027 # Total read bandwidth from this memory (bytes/s)
39 system.physmem.bw_read::cpu1.inst 35378808 # Total read bandwidth from this memory (bytes/s)
40 system.physmem.bw_read::cpu1.data 39856027 # Total read bandwidth from this memory (bytes/s)
41 system.physmem.bw_read::cpu2.inst 35378808 # Total read bandwidth from this memory (bytes/s)
42 system.physmem.bw_read::cpu2.data 39856027 # Total read bandwidth from this memory (bytes/s)
43 system.physmem.bw_read::cpu3.inst 35378808 # Total read bandwidth from this memory (bytes/s)
44 system.physmem.bw_read::cpu3.data 39856027 # Total read bandwidth from this memory (bytes/s)
45 system.physmem.bw_read::total 300939338 # Total read bandwidth from this memory (bytes/s)
46 system.physmem.bw_inst_read::cpu0.inst 35378808 # Instruction read bandwidth from this memory (bytes/s)
47 system.physmem.bw_inst_read::cpu1.inst 35378808 # Instruction read bandwidth from this memory (bytes/s)
48 system.physmem.bw_inst_read::cpu2.inst 35378808 # Instruction read bandwidth from this memory (bytes/s)
49 system.physmem.bw_inst_read::cpu3.inst 35378808 # Instruction read bandwidth from this memory (bytes/s)
50 system.physmem.bw_inst_read::total 141515231 # Instruction read bandwidth from this memory (bytes/s)
51 system.physmem.bw_total::cpu0.inst 35378808 # Total bandwidth to/from this memory (bytes/s)
52 system.physmem.bw_total::cpu0.data 39856027 # Total bandwidth to/from this memory (bytes/s)
53 system.physmem.bw_total::cpu1.inst 35378808 # Total bandwidth to/from this memory (bytes/s)
54 system.physmem.bw_total::cpu1.data 39856027 # Total bandwidth to/from this memory (bytes/s)
55 system.physmem.bw_total::cpu2.inst 35378808 # Total bandwidth to/from this memory (bytes/s)
56 system.physmem.bw_total::cpu2.data 39856027 # Total bandwidth to/from this memory (bytes/s)
57 system.physmem.bw_total::cpu3.inst 35378808 # Total bandwidth to/from this memory (bytes/s)
58 system.physmem.bw_total::cpu3.data 39856027 # Total bandwidth to/from this memory (bytes/s)
59 system.physmem.bw_total::total 300939338 # Total bandwidth to/from this memory (bytes/s)
60 system.membus.throughput 300939338 # Throughput (bytes/s)
61 system.membus.trans_dist::ReadReq 2872 # Transaction distribution
62 system.membus.trans_dist::ReadResp 2872 # Transaction distribution
63 system.membus.trans_dist::ReadExReq 556 # Transaction distribution
64 system.membus.trans_dist::ReadExResp 556 # Transaction distribution
65 system.membus.pkt_count_system.l2c.mem_side 6856 # Packet count per connected master and slave (bytes)
66 system.membus.pkt_count 6856 # Packet count per connected master and slave (bytes)
67 system.membus.tot_pkt_size_system.l2c.mem_side 219392 # Cumulative packet size per connected master and slave (bytes)
68 system.membus.tot_pkt_size 219392 # Cumulative packet size per connected master and slave (bytes)
69 system.membus.data_through_bus 219392 # Total data (bytes)
70 system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
71 system.membus.reqLayer0.occupancy 4229968 # Layer occupancy (ticks)
72 system.membus.reqLayer0.utilization 0.6 # Layer utilization (%)
73 system.membus.respLayer0.occupancy 31051500 # Layer occupancy (ticks)
74 system.membus.respLayer0.utilization 4.3 # Layer utilization (%)
75 system.toL2Bus.throughput 335352471 # Throughput (bytes/s)
76 system.toL2Bus.trans_dist::ReadReq 3148 # Transaction distribution
77 system.toL2Bus.trans_dist::ReadResp 3148 # Transaction distribution
78 system.toL2Bus.trans_dist::Writeback 116 # Transaction distribution
79 system.toL2Bus.trans_dist::ReadExReq 556 # Transaction distribution
80 system.toL2Bus.trans_dist::ReadExResp 556 # Transaction distribution
81 system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 926 # Packet count per connected master and slave (bytes)
82 system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 955 # Packet count per connected master and slave (bytes)
83 system.toL2Bus.pkt_count_system.cpu1.icache.mem_side 926 # Packet count per connected master and slave (bytes)
84 system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side 955 # Packet count per connected master and slave (bytes)
85 system.toL2Bus.pkt_count_system.cpu2.icache.mem_side 926 # Packet count per connected master and slave (bytes)
86 system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side 955 # Packet count per connected master and slave (bytes)
87 system.toL2Bus.pkt_count_system.cpu3.icache.mem_side 926 # Packet count per connected master and slave (bytes)
88 system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side 955 # Packet count per connected master and slave (bytes)
89 system.toL2Bus.pkt_count 7524 # Packet count per connected master and slave (bytes)
90 system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 29632 # Cumulative packet size per connected master and slave (bytes)
91 system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 31488 # Cumulative packet size per connected master and slave (bytes)
92 system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side 29632 # Cumulative packet size per connected master and slave (bytes)
93 system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side 31488 # Cumulative packet size per connected master and slave (bytes)
94 system.toL2Bus.tot_pkt_size_system.cpu2.icache.mem_side 29632 # Cumulative packet size per connected master and slave (bytes)
95 system.toL2Bus.tot_pkt_size_system.cpu2.dcache.mem_side 31488 # Cumulative packet size per connected master and slave (bytes)
96 system.toL2Bus.tot_pkt_size_system.cpu3.icache.mem_side 29632 # Cumulative packet size per connected master and slave (bytes)
97 system.toL2Bus.tot_pkt_size_system.cpu3.dcache.mem_side 31488 # Cumulative packet size per connected master and slave (bytes)
98 system.toL2Bus.tot_pkt_size 244480 # Cumulative packet size per connected master and slave (bytes)
99 system.toL2Bus.data_through_bus 244480 # Total data (bytes)
100 system.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
101 system.toL2Bus.reqLayer0.occupancy 2374000 # Layer occupancy (ticks)
102 system.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)
103 system.toL2Bus.respLayer0.occupancy 2083500 # Layer occupancy (ticks)
104 system.toL2Bus.respLayer0.utilization 0.3 # Layer utilization (%)
105 system.toL2Bus.respLayer1.occupancy 2083500 # Layer occupancy (ticks)
106 system.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%)
107 system.toL2Bus.respLayer2.occupancy 2083500 # Layer occupancy (ticks)
108 system.toL2Bus.respLayer2.utilization 0.3 # Layer utilization (%)
109 system.toL2Bus.respLayer3.occupancy 2083500 # Layer occupancy (ticks)
110 system.toL2Bus.respLayer3.utilization 0.3 # Layer utilization (%)
111 system.toL2Bus.respLayer4.occupancy 2083500 # Layer occupancy (ticks)
112 system.toL2Bus.respLayer4.utilization 0.3 # Layer utilization (%)
113 system.toL2Bus.respLayer5.occupancy 2083500 # Layer occupancy (ticks)
114 system.toL2Bus.respLayer5.utilization 0.3 # Layer utilization (%)
115 system.toL2Bus.respLayer6.occupancy 2083500 # Layer occupancy (ticks)
116 system.toL2Bus.respLayer6.utilization 0.3 # Layer utilization (%)
117 system.toL2Bus.respLayer7.occupancy 2083500 # Layer occupancy (ticks)
118 system.toL2Bus.respLayer7.utilization 0.3 # Layer utilization (%)
119 system.cpu0.dtb.fetch_hits 0 # ITB hits
120 system.cpu0.dtb.fetch_misses 0 # ITB misses
121 system.cpu0.dtb.fetch_acv 0 # ITB acv
122 system.cpu0.dtb.fetch_accesses 0 # ITB accesses
123 system.cpu0.dtb.read_hits 124435 # DTB read hits
124 system.cpu0.dtb.read_misses 8 # DTB read misses
125 system.cpu0.dtb.read_acv 0 # DTB read access violations
126 system.cpu0.dtb.read_accesses 124443 # DTB read accesses
127 system.cpu0.dtb.write_hits 56340 # DTB write hits
128 system.cpu0.dtb.write_misses 10 # DTB write misses
129 system.cpu0.dtb.write_acv 0 # DTB write access violations
130 system.cpu0.dtb.write_accesses 56350 # DTB write accesses
131 system.cpu0.dtb.data_hits 180775 # DTB hits
132 system.cpu0.dtb.data_misses 18 # DTB misses
133 system.cpu0.dtb.data_acv 0 # DTB access violations
134 system.cpu0.dtb.data_accesses 180793 # DTB accesses
135 system.cpu0.itb.fetch_hits 500020 # ITB hits
136 system.cpu0.itb.fetch_misses 13 # ITB misses
137 system.cpu0.itb.fetch_acv 0 # ITB acv
138 system.cpu0.itb.fetch_accesses 500033 # ITB accesses
139 system.cpu0.itb.read_hits 0 # DTB read hits
140 system.cpu0.itb.read_misses 0 # DTB read misses
141 system.cpu0.itb.read_acv 0 # DTB read access violations
142 system.cpu0.itb.read_accesses 0 # DTB read accesses
143 system.cpu0.itb.write_hits 0 # DTB write hits
144 system.cpu0.itb.write_misses 0 # DTB write misses
145 system.cpu0.itb.write_acv 0 # DTB write access violations
146 system.cpu0.itb.write_accesses 0 # DTB write accesses
147 system.cpu0.itb.data_hits 0 # DTB hits
148 system.cpu0.itb.data_misses 0 # DTB misses
149 system.cpu0.itb.data_acv 0 # DTB access violations
150 system.cpu0.itb.data_accesses 0 # DTB accesses
151 system.cpu0.workload.num_syscalls 18 # Number of system calls
152 system.cpu0.numCycles 1458048 # number of cpu cycles simulated
153 system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
154 system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
155 system.cpu0.committedInsts 500001 # Number of instructions committed
156 system.cpu0.committedOps 500001 # Number of ops (including micro ops) committed
157 system.cpu0.num_int_alu_accesses 474689 # Number of integer alu accesses
158 system.cpu0.num_fp_alu_accesses 32 # Number of float alu accesses
159 system.cpu0.num_func_calls 14357 # number of times a function call or return occured
160 system.cpu0.num_conditional_control_insts 38180 # number of instructions that are conditional controls
161 system.cpu0.num_int_insts 474689 # number of integer instructions
162 system.cpu0.num_fp_insts 32 # number of float instructions
163 system.cpu0.num_int_register_reads 654286 # number of times the integer registers were read
164 system.cpu0.num_int_register_writes 371542 # number of times the integer registers were written
165 system.cpu0.num_fp_register_reads 32 # number of times the floating registers were read
166 system.cpu0.num_fp_register_writes 16 # number of times the floating registers were written
167 system.cpu0.num_mem_refs 180793 # number of memory refs
168 system.cpu0.num_load_insts 124443 # Number of load instructions
169 system.cpu0.num_store_insts 56350 # Number of store instructions
170 system.cpu0.num_idle_cycles 0 # Number of idle cycles
171 system.cpu0.num_busy_cycles 1458048 # Number of busy cycles
172 system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles
173 system.cpu0.idle_fraction 0 # Percentage of idle cycles
174 system.cpu0.icache.replacements 152 # number of replacements
175 system.cpu0.icache.tagsinuse 216.376897 # Cycle average of tags in use
176 system.cpu0.icache.total_refs 499557 # Total number of references to valid blocks.
177 system.cpu0.icache.sampled_refs 463 # Sample count of references to valid blocks.
178 system.cpu0.icache.avg_refs 1078.956803 # Average number of references to valid blocks.
179 system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
180 system.cpu0.icache.occ_blocks::cpu0.inst 216.376897 # Average occupied blocks per requestor
181 system.cpu0.icache.occ_percent::cpu0.inst 0.422611 # Average percentage of cache occupancy
182 system.cpu0.icache.occ_percent::total 0.422611 # Average percentage of cache occupancy
183 system.cpu0.icache.ReadReq_hits::cpu0.inst 499557 # number of ReadReq hits
184 system.cpu0.icache.ReadReq_hits::total 499557 # number of ReadReq hits
185 system.cpu0.icache.demand_hits::cpu0.inst 499557 # number of demand (read+write) hits
186 system.cpu0.icache.demand_hits::total 499557 # number of demand (read+write) hits
187 system.cpu0.icache.overall_hits::cpu0.inst 499557 # number of overall hits
188 system.cpu0.icache.overall_hits::total 499557 # number of overall hits
189 system.cpu0.icache.ReadReq_misses::cpu0.inst 463 # number of ReadReq misses
190 system.cpu0.icache.ReadReq_misses::total 463 # number of ReadReq misses
191 system.cpu0.icache.demand_misses::cpu0.inst 463 # number of demand (read+write) misses
192 system.cpu0.icache.demand_misses::total 463 # number of demand (read+write) misses
193 system.cpu0.icache.overall_misses::cpu0.inst 463 # number of overall misses
194 system.cpu0.icache.overall_misses::total 463 # number of overall misses
195 system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 23096000 # number of ReadReq miss cycles
196 system.cpu0.icache.ReadReq_miss_latency::total 23096000 # number of ReadReq miss cycles
197 system.cpu0.icache.demand_miss_latency::cpu0.inst 23096000 # number of demand (read+write) miss cycles
198 system.cpu0.icache.demand_miss_latency::total 23096000 # number of demand (read+write) miss cycles
199 system.cpu0.icache.overall_miss_latency::cpu0.inst 23096000 # number of overall miss cycles
200 system.cpu0.icache.overall_miss_latency::total 23096000 # number of overall miss cycles
201 system.cpu0.icache.ReadReq_accesses::cpu0.inst 500020 # number of ReadReq accesses(hits+misses)
202 system.cpu0.icache.ReadReq_accesses::total 500020 # number of ReadReq accesses(hits+misses)
203 system.cpu0.icache.demand_accesses::cpu0.inst 500020 # number of demand (read+write) accesses
204 system.cpu0.icache.demand_accesses::total 500020 # number of demand (read+write) accesses
205 system.cpu0.icache.overall_accesses::cpu0.inst 500020 # number of overall (read+write) accesses
206 system.cpu0.icache.overall_accesses::total 500020 # number of overall (read+write) accesses
207 system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.000926 # miss rate for ReadReq accesses
208 system.cpu0.icache.ReadReq_miss_rate::total 0.000926 # miss rate for ReadReq accesses
209 system.cpu0.icache.demand_miss_rate::cpu0.inst 0.000926 # miss rate for demand accesses
210 system.cpu0.icache.demand_miss_rate::total 0.000926 # miss rate for demand accesses
211 system.cpu0.icache.overall_miss_rate::cpu0.inst 0.000926 # miss rate for overall accesses
212 system.cpu0.icache.overall_miss_rate::total 0.000926 # miss rate for overall accesses
213 system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 49883.369330 # average ReadReq miss latency
214 system.cpu0.icache.ReadReq_avg_miss_latency::total 49883.369330 # average ReadReq miss latency
215 system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 49883.369330 # average overall miss latency
216 system.cpu0.icache.demand_avg_miss_latency::total 49883.369330 # average overall miss latency
217 system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 49883.369330 # average overall miss latency
218 system.cpu0.icache.overall_avg_miss_latency::total 49883.369330 # average overall miss latency
219 system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
220 system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
221 system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
222 system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
223 system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
224 system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
225 system.cpu0.icache.fast_writes 0 # number of fast writes performed
226 system.cpu0.icache.cache_copies 0 # number of cache copies performed
227 system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 463 # number of ReadReq MSHR misses
228 system.cpu0.icache.ReadReq_mshr_misses::total 463 # number of ReadReq MSHR misses
229 system.cpu0.icache.demand_mshr_misses::cpu0.inst 463 # number of demand (read+write) MSHR misses
230 system.cpu0.icache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses
231 system.cpu0.icache.overall_mshr_misses::cpu0.inst 463 # number of overall MSHR misses
232 system.cpu0.icache.overall_mshr_misses::total 463 # number of overall MSHR misses
233 system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 22170000 # number of ReadReq MSHR miss cycles
234 system.cpu0.icache.ReadReq_mshr_miss_latency::total 22170000 # number of ReadReq MSHR miss cycles
235 system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 22170000 # number of demand (read+write) MSHR miss cycles
236 system.cpu0.icache.demand_mshr_miss_latency::total 22170000 # number of demand (read+write) MSHR miss cycles
237 system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 22170000 # number of overall MSHR miss cycles
238 system.cpu0.icache.overall_mshr_miss_latency::total 22170000 # number of overall MSHR miss cycles
239 system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.000926 # mshr miss rate for ReadReq accesses
240 system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.000926 # mshr miss rate for ReadReq accesses
241 system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.000926 # mshr miss rate for demand accesses
242 system.cpu0.icache.demand_mshr_miss_rate::total 0.000926 # mshr miss rate for demand accesses
243 system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.000926 # mshr miss rate for overall accesses
244 system.cpu0.icache.overall_mshr_miss_rate::total 0.000926 # mshr miss rate for overall accesses
245 system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 47883.369330 # average ReadReq mshr miss latency
246 system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 47883.369330 # average ReadReq mshr miss latency
247 system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 47883.369330 # average overall mshr miss latency
248 system.cpu0.icache.demand_avg_mshr_miss_latency::total 47883.369330 # average overall mshr miss latency
249 system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 47883.369330 # average overall mshr miss latency
250 system.cpu0.icache.overall_avg_mshr_miss_latency::total 47883.369330 # average overall mshr miss latency
251 system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
252 system.cpu0.dcache.replacements 61 # number of replacements
253 system.cpu0.dcache.tagsinuse 273.500146 # Cycle average of tags in use
254 system.cpu0.dcache.total_refs 180312 # Total number of references to valid blocks.
255 system.cpu0.dcache.sampled_refs 463 # Sample count of references to valid blocks.
256 system.cpu0.dcache.avg_refs 389.442765 # Average number of references to valid blocks.
257 system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
258 system.cpu0.dcache.occ_blocks::cpu0.data 273.500146 # Average occupied blocks per requestor
259 system.cpu0.dcache.occ_percent::cpu0.data 0.534180 # Average percentage of cache occupancy
260 system.cpu0.dcache.occ_percent::total 0.534180 # Average percentage of cache occupancy
261 system.cpu0.dcache.ReadReq_hits::cpu0.data 124111 # number of ReadReq hits
262 system.cpu0.dcache.ReadReq_hits::total 124111 # number of ReadReq hits
263 system.cpu0.dcache.WriteReq_hits::cpu0.data 56201 # number of WriteReq hits
264 system.cpu0.dcache.WriteReq_hits::total 56201 # number of WriteReq hits
265 system.cpu0.dcache.demand_hits::cpu0.data 180312 # number of demand (read+write) hits
266 system.cpu0.dcache.demand_hits::total 180312 # number of demand (read+write) hits
267 system.cpu0.dcache.overall_hits::cpu0.data 180312 # number of overall hits
268 system.cpu0.dcache.overall_hits::total 180312 # number of overall hits
269 system.cpu0.dcache.ReadReq_misses::cpu0.data 324 # number of ReadReq misses
270 system.cpu0.dcache.ReadReq_misses::total 324 # number of ReadReq misses
271 system.cpu0.dcache.WriteReq_misses::cpu0.data 139 # number of WriteReq misses
272 system.cpu0.dcache.WriteReq_misses::total 139 # number of WriteReq misses
273 system.cpu0.dcache.demand_misses::cpu0.data 463 # number of demand (read+write) misses
274 system.cpu0.dcache.demand_misses::total 463 # number of demand (read+write) misses
275 system.cpu0.dcache.overall_misses::cpu0.data 463 # number of overall misses
276 system.cpu0.dcache.overall_misses::total 463 # number of overall misses
277 system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 17474500 # number of ReadReq miss cycles
278 system.cpu0.dcache.ReadReq_miss_latency::total 17474500 # number of ReadReq miss cycles
279 system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7669500 # number of WriteReq miss cycles
280 system.cpu0.dcache.WriteReq_miss_latency::total 7669500 # number of WriteReq miss cycles
281 system.cpu0.dcache.demand_miss_latency::cpu0.data 25144000 # number of demand (read+write) miss cycles
282 system.cpu0.dcache.demand_miss_latency::total 25144000 # number of demand (read+write) miss cycles
283 system.cpu0.dcache.overall_miss_latency::cpu0.data 25144000 # number of overall miss cycles
284 system.cpu0.dcache.overall_miss_latency::total 25144000 # number of overall miss cycles
285 system.cpu0.dcache.ReadReq_accesses::cpu0.data 124435 # number of ReadReq accesses(hits+misses)
286 system.cpu0.dcache.ReadReq_accesses::total 124435 # number of ReadReq accesses(hits+misses)
287 system.cpu0.dcache.WriteReq_accesses::cpu0.data 56340 # number of WriteReq accesses(hits+misses)
288 system.cpu0.dcache.WriteReq_accesses::total 56340 # number of WriteReq accesses(hits+misses)
289 system.cpu0.dcache.demand_accesses::cpu0.data 180775 # number of demand (read+write) accesses
290 system.cpu0.dcache.demand_accesses::total 180775 # number of demand (read+write) accesses
291 system.cpu0.dcache.overall_accesses::cpu0.data 180775 # number of overall (read+write) accesses
292 system.cpu0.dcache.overall_accesses::total 180775 # number of overall (read+write) accesses
293 system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.002604 # miss rate for ReadReq accesses
294 system.cpu0.dcache.ReadReq_miss_rate::total 0.002604 # miss rate for ReadReq accesses
295 system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.002467 # miss rate for WriteReq accesses
296 system.cpu0.dcache.WriteReq_miss_rate::total 0.002467 # miss rate for WriteReq accesses
297 system.cpu0.dcache.demand_miss_rate::cpu0.data 0.002561 # miss rate for demand accesses
298 system.cpu0.dcache.demand_miss_rate::total 0.002561 # miss rate for demand accesses
299 system.cpu0.dcache.overall_miss_rate::cpu0.data 0.002561 # miss rate for overall accesses
300 system.cpu0.dcache.overall_miss_rate::total 0.002561 # miss rate for overall accesses
301 system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 53933.641975 # average ReadReq miss latency
302 system.cpu0.dcache.ReadReq_avg_miss_latency::total 53933.641975 # average ReadReq miss latency
303 system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 55176.258993 # average WriteReq miss latency
304 system.cpu0.dcache.WriteReq_avg_miss_latency::total 55176.258993 # average WriteReq miss latency
305 system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 54306.695464 # average overall miss latency
306 system.cpu0.dcache.demand_avg_miss_latency::total 54306.695464 # average overall miss latency
307 system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 54306.695464 # average overall miss latency
308 system.cpu0.dcache.overall_avg_miss_latency::total 54306.695464 # average overall miss latency
309 system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
310 system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
311 system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
312 system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
313 system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
314 system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
315 system.cpu0.dcache.fast_writes 0 # number of fast writes performed
316 system.cpu0.dcache.cache_copies 0 # number of cache copies performed
317 system.cpu0.dcache.writebacks::writebacks 29 # number of writebacks
318 system.cpu0.dcache.writebacks::total 29 # number of writebacks
319 system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 324 # number of ReadReq MSHR misses
320 system.cpu0.dcache.ReadReq_mshr_misses::total 324 # number of ReadReq MSHR misses
321 system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 139 # number of WriteReq MSHR misses
322 system.cpu0.dcache.WriteReq_mshr_misses::total 139 # number of WriteReq MSHR misses
323 system.cpu0.dcache.demand_mshr_misses::cpu0.data 463 # number of demand (read+write) MSHR misses
324 system.cpu0.dcache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses
325 system.cpu0.dcache.overall_mshr_misses::cpu0.data 463 # number of overall MSHR misses
326 system.cpu0.dcache.overall_mshr_misses::total 463 # number of overall MSHR misses
327 system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 16826500 # number of ReadReq MSHR miss cycles
328 system.cpu0.dcache.ReadReq_mshr_miss_latency::total 16826500 # number of ReadReq MSHR miss cycles
329 system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7391500 # number of WriteReq MSHR miss cycles
330 system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7391500 # number of WriteReq MSHR miss cycles
331 system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 24218000 # number of demand (read+write) MSHR miss cycles
332 system.cpu0.dcache.demand_mshr_miss_latency::total 24218000 # number of demand (read+write) MSHR miss cycles
333 system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 24218000 # number of overall MSHR miss cycles
334 system.cpu0.dcache.overall_mshr_miss_latency::total 24218000 # number of overall MSHR miss cycles
335 system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002604 # mshr miss rate for ReadReq accesses
336 system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002604 # mshr miss rate for ReadReq accesses
337 system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002467 # mshr miss rate for WriteReq accesses
338 system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002467 # mshr miss rate for WriteReq accesses
339 system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002561 # mshr miss rate for demand accesses
340 system.cpu0.dcache.demand_mshr_miss_rate::total 0.002561 # mshr miss rate for demand accesses
341 system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002561 # mshr miss rate for overall accesses
342 system.cpu0.dcache.overall_mshr_miss_rate::total 0.002561 # mshr miss rate for overall accesses
343 system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 51933.641975 # average ReadReq mshr miss latency
344 system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 51933.641975 # average ReadReq mshr miss latency
345 system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 53176.258993 # average WriteReq mshr miss latency
346 system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 53176.258993 # average WriteReq mshr miss latency
347 system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 52306.695464 # average overall mshr miss latency
348 system.cpu0.dcache.demand_avg_mshr_miss_latency::total 52306.695464 # average overall mshr miss latency
349 system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 52306.695464 # average overall mshr miss latency
350 system.cpu0.dcache.overall_avg_mshr_miss_latency::total 52306.695464 # average overall mshr miss latency
351 system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
352 system.cpu1.dtb.fetch_hits 0 # ITB hits
353 system.cpu1.dtb.fetch_misses 0 # ITB misses
354 system.cpu1.dtb.fetch_acv 0 # ITB acv
355 system.cpu1.dtb.fetch_accesses 0 # ITB accesses
356 system.cpu1.dtb.read_hits 124435 # DTB read hits
357 system.cpu1.dtb.read_misses 8 # DTB read misses
358 system.cpu1.dtb.read_acv 0 # DTB read access violations
359 system.cpu1.dtb.read_accesses 124443 # DTB read accesses
360 system.cpu1.dtb.write_hits 56339 # DTB write hits
361 system.cpu1.dtb.write_misses 10 # DTB write misses
362 system.cpu1.dtb.write_acv 0 # DTB write access violations
363 system.cpu1.dtb.write_accesses 56349 # DTB write accesses
364 system.cpu1.dtb.data_hits 180774 # DTB hits
365 system.cpu1.dtb.data_misses 18 # DTB misses
366 system.cpu1.dtb.data_acv 0 # DTB access violations
367 system.cpu1.dtb.data_accesses 180792 # DTB accesses
368 system.cpu1.itb.fetch_hits 500012 # ITB hits
369 system.cpu1.itb.fetch_misses 13 # ITB misses
370 system.cpu1.itb.fetch_acv 0 # ITB acv
371 system.cpu1.itb.fetch_accesses 500025 # ITB accesses
372 system.cpu1.itb.read_hits 0 # DTB read hits
373 system.cpu1.itb.read_misses 0 # DTB read misses
374 system.cpu1.itb.read_acv 0 # DTB read access violations
375 system.cpu1.itb.read_accesses 0 # DTB read accesses
376 system.cpu1.itb.write_hits 0 # DTB write hits
377 system.cpu1.itb.write_misses 0 # DTB write misses
378 system.cpu1.itb.write_acv 0 # DTB write access violations
379 system.cpu1.itb.write_accesses 0 # DTB write accesses
380 system.cpu1.itb.data_hits 0 # DTB hits
381 system.cpu1.itb.data_misses 0 # DTB misses
382 system.cpu1.itb.data_acv 0 # DTB access violations
383 system.cpu1.itb.data_accesses 0 # DTB accesses
384 system.cpu1.workload.num_syscalls 18 # Number of system calls
385 system.cpu1.numCycles 1458048 # number of cpu cycles simulated
386 system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
387 system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
388 system.cpu1.committedInsts 499993 # Number of instructions committed
389 system.cpu1.committedOps 499993 # Number of ops (including micro ops) committed
390 system.cpu1.num_int_alu_accesses 474681 # Number of integer alu accesses
391 system.cpu1.num_fp_alu_accesses 32 # Number of float alu accesses
392 system.cpu1.num_func_calls 14357 # number of times a function call or return occured
393 system.cpu1.num_conditional_control_insts 38179 # number of instructions that are conditional controls
394 system.cpu1.num_int_insts 474681 # number of integer instructions
395 system.cpu1.num_fp_insts 32 # number of float instructions
396 system.cpu1.num_int_register_reads 654273 # number of times the integer registers were read
397 system.cpu1.num_int_register_writes 371536 # number of times the integer registers were written
398 system.cpu1.num_fp_register_reads 32 # number of times the floating registers were read
399 system.cpu1.num_fp_register_writes 16 # number of times the floating registers were written
400 system.cpu1.num_mem_refs 180792 # number of memory refs
401 system.cpu1.num_load_insts 124443 # Number of load instructions
402 system.cpu1.num_store_insts 56349 # Number of store instructions
403 system.cpu1.num_idle_cycles 0 # Number of idle cycles
404 system.cpu1.num_busy_cycles 1458048 # Number of busy cycles
405 system.cpu1.not_idle_fraction 1 # Percentage of non-idle cycles
406 system.cpu1.idle_fraction 0 # Percentage of idle cycles
407 system.cpu1.icache.replacements 152 # number of replacements
408 system.cpu1.icache.tagsinuse 216.373058 # Cycle average of tags in use
409 system.cpu1.icache.total_refs 499549 # Total number of references to valid blocks.
410 system.cpu1.icache.sampled_refs 463 # Sample count of references to valid blocks.
411 system.cpu1.icache.avg_refs 1078.939525 # Average number of references to valid blocks.
412 system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
413 system.cpu1.icache.occ_blocks::cpu1.inst 216.373058 # Average occupied blocks per requestor
414 system.cpu1.icache.occ_percent::cpu1.inst 0.422604 # Average percentage of cache occupancy
415 system.cpu1.icache.occ_percent::total 0.422604 # Average percentage of cache occupancy
416 system.cpu1.icache.ReadReq_hits::cpu1.inst 499549 # number of ReadReq hits
417 system.cpu1.icache.ReadReq_hits::total 499549 # number of ReadReq hits
418 system.cpu1.icache.demand_hits::cpu1.inst 499549 # number of demand (read+write) hits
419 system.cpu1.icache.demand_hits::total 499549 # number of demand (read+write) hits
420 system.cpu1.icache.overall_hits::cpu1.inst 499549 # number of overall hits
421 system.cpu1.icache.overall_hits::total 499549 # number of overall hits
422 system.cpu1.icache.ReadReq_misses::cpu1.inst 463 # number of ReadReq misses
423 system.cpu1.icache.ReadReq_misses::total 463 # number of ReadReq misses
424 system.cpu1.icache.demand_misses::cpu1.inst 463 # number of demand (read+write) misses
425 system.cpu1.icache.demand_misses::total 463 # number of demand (read+write) misses
426 system.cpu1.icache.overall_misses::cpu1.inst 463 # number of overall misses
427 system.cpu1.icache.overall_misses::total 463 # number of overall misses
428 system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 23105000 # number of ReadReq miss cycles
429 system.cpu1.icache.ReadReq_miss_latency::total 23105000 # number of ReadReq miss cycles
430 system.cpu1.icache.demand_miss_latency::cpu1.inst 23105000 # number of demand (read+write) miss cycles
431 system.cpu1.icache.demand_miss_latency::total 23105000 # number of demand (read+write) miss cycles
432 system.cpu1.icache.overall_miss_latency::cpu1.inst 23105000 # number of overall miss cycles
433 system.cpu1.icache.overall_miss_latency::total 23105000 # number of overall miss cycles
434 system.cpu1.icache.ReadReq_accesses::cpu1.inst 500012 # number of ReadReq accesses(hits+misses)
435 system.cpu1.icache.ReadReq_accesses::total 500012 # number of ReadReq accesses(hits+misses)
436 system.cpu1.icache.demand_accesses::cpu1.inst 500012 # number of demand (read+write) accesses
437 system.cpu1.icache.demand_accesses::total 500012 # number of demand (read+write) accesses
438 system.cpu1.icache.overall_accesses::cpu1.inst 500012 # number of overall (read+write) accesses
439 system.cpu1.icache.overall_accesses::total 500012 # number of overall (read+write) accesses
440 system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.000926 # miss rate for ReadReq accesses
441 system.cpu1.icache.ReadReq_miss_rate::total 0.000926 # miss rate for ReadReq accesses
442 system.cpu1.icache.demand_miss_rate::cpu1.inst 0.000926 # miss rate for demand accesses
443 system.cpu1.icache.demand_miss_rate::total 0.000926 # miss rate for demand accesses
444 system.cpu1.icache.overall_miss_rate::cpu1.inst 0.000926 # miss rate for overall accesses
445 system.cpu1.icache.overall_miss_rate::total 0.000926 # miss rate for overall accesses
446 system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 49902.807775 # average ReadReq miss latency
447 system.cpu1.icache.ReadReq_avg_miss_latency::total 49902.807775 # average ReadReq miss latency
448 system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 49902.807775 # average overall miss latency
449 system.cpu1.icache.demand_avg_miss_latency::total 49902.807775 # average overall miss latency
450 system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 49902.807775 # average overall miss latency
451 system.cpu1.icache.overall_avg_miss_latency::total 49902.807775 # average overall miss latency
452 system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
453 system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
454 system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
455 system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
456 system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
457 system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
458 system.cpu1.icache.fast_writes 0 # number of fast writes performed
459 system.cpu1.icache.cache_copies 0 # number of cache copies performed
460 system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 463 # number of ReadReq MSHR misses
461 system.cpu1.icache.ReadReq_mshr_misses::total 463 # number of ReadReq MSHR misses
462 system.cpu1.icache.demand_mshr_misses::cpu1.inst 463 # number of demand (read+write) MSHR misses
463 system.cpu1.icache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses
464 system.cpu1.icache.overall_mshr_misses::cpu1.inst 463 # number of overall MSHR misses
465 system.cpu1.icache.overall_mshr_misses::total 463 # number of overall MSHR misses
466 system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 22179000 # number of ReadReq MSHR miss cycles
467 system.cpu1.icache.ReadReq_mshr_miss_latency::total 22179000 # number of ReadReq MSHR miss cycles
468 system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 22179000 # number of demand (read+write) MSHR miss cycles
469 system.cpu1.icache.demand_mshr_miss_latency::total 22179000 # number of demand (read+write) MSHR miss cycles
470 system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 22179000 # number of overall MSHR miss cycles
471 system.cpu1.icache.overall_mshr_miss_latency::total 22179000 # number of overall MSHR miss cycles
472 system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.000926 # mshr miss rate for ReadReq accesses
473 system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.000926 # mshr miss rate for ReadReq accesses
474 system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.000926 # mshr miss rate for demand accesses
475 system.cpu1.icache.demand_mshr_miss_rate::total 0.000926 # mshr miss rate for demand accesses
476 system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.000926 # mshr miss rate for overall accesses
477 system.cpu1.icache.overall_mshr_miss_rate::total 0.000926 # mshr miss rate for overall accesses
478 system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 47902.807775 # average ReadReq mshr miss latency
479 system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 47902.807775 # average ReadReq mshr miss latency
480 system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 47902.807775 # average overall mshr miss latency
481 system.cpu1.icache.demand_avg_mshr_miss_latency::total 47902.807775 # average overall mshr miss latency
482 system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 47902.807775 # average overall mshr miss latency
483 system.cpu1.icache.overall_avg_mshr_miss_latency::total 47902.807775 # average overall mshr miss latency
484 system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
485 system.cpu1.dcache.replacements 61 # number of replacements
486 system.cpu1.dcache.tagsinuse 273.495183 # Cycle average of tags in use
487 system.cpu1.dcache.total_refs 180311 # Total number of references to valid blocks.
488 system.cpu1.dcache.sampled_refs 463 # Sample count of references to valid blocks.
489 system.cpu1.dcache.avg_refs 389.440605 # Average number of references to valid blocks.
490 system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
491 system.cpu1.dcache.occ_blocks::cpu1.data 273.495183 # Average occupied blocks per requestor
492 system.cpu1.dcache.occ_percent::cpu1.data 0.534170 # Average percentage of cache occupancy
493 system.cpu1.dcache.occ_percent::total 0.534170 # Average percentage of cache occupancy
494 system.cpu1.dcache.ReadReq_hits::cpu1.data 124111 # number of ReadReq hits
495 system.cpu1.dcache.ReadReq_hits::total 124111 # number of ReadReq hits
496 system.cpu1.dcache.WriteReq_hits::cpu1.data 56200 # number of WriteReq hits
497 system.cpu1.dcache.WriteReq_hits::total 56200 # number of WriteReq hits
498 system.cpu1.dcache.demand_hits::cpu1.data 180311 # number of demand (read+write) hits
499 system.cpu1.dcache.demand_hits::total 180311 # number of demand (read+write) hits
500 system.cpu1.dcache.overall_hits::cpu1.data 180311 # number of overall hits
501 system.cpu1.dcache.overall_hits::total 180311 # number of overall hits
502 system.cpu1.dcache.ReadReq_misses::cpu1.data 324 # number of ReadReq misses
503 system.cpu1.dcache.ReadReq_misses::total 324 # number of ReadReq misses
504 system.cpu1.dcache.WriteReq_misses::cpu1.data 139 # number of WriteReq misses
505 system.cpu1.dcache.WriteReq_misses::total 139 # number of WriteReq misses
506 system.cpu1.dcache.demand_misses::cpu1.data 463 # number of demand (read+write) misses
507 system.cpu1.dcache.demand_misses::total 463 # number of demand (read+write) misses
508 system.cpu1.dcache.overall_misses::cpu1.data 463 # number of overall misses
509 system.cpu1.dcache.overall_misses::total 463 # number of overall misses
510 system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 17474500 # number of ReadReq miss cycles
511 system.cpu1.dcache.ReadReq_miss_latency::total 17474500 # number of ReadReq miss cycles
512 system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 7669500 # number of WriteReq miss cycles
513 system.cpu1.dcache.WriteReq_miss_latency::total 7669500 # number of WriteReq miss cycles
514 system.cpu1.dcache.demand_miss_latency::cpu1.data 25144000 # number of demand (read+write) miss cycles
515 system.cpu1.dcache.demand_miss_latency::total 25144000 # number of demand (read+write) miss cycles
516 system.cpu1.dcache.overall_miss_latency::cpu1.data 25144000 # number of overall miss cycles
517 system.cpu1.dcache.overall_miss_latency::total 25144000 # number of overall miss cycles
518 system.cpu1.dcache.ReadReq_accesses::cpu1.data 124435 # number of ReadReq accesses(hits+misses)
519 system.cpu1.dcache.ReadReq_accesses::total 124435 # number of ReadReq accesses(hits+misses)
520 system.cpu1.dcache.WriteReq_accesses::cpu1.data 56339 # number of WriteReq accesses(hits+misses)
521 system.cpu1.dcache.WriteReq_accesses::total 56339 # number of WriteReq accesses(hits+misses)
522 system.cpu1.dcache.demand_accesses::cpu1.data 180774 # number of demand (read+write) accesses
523 system.cpu1.dcache.demand_accesses::total 180774 # number of demand (read+write) accesses
524 system.cpu1.dcache.overall_accesses::cpu1.data 180774 # number of overall (read+write) accesses
525 system.cpu1.dcache.overall_accesses::total 180774 # number of overall (read+write) accesses
526 system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.002604 # miss rate for ReadReq accesses
527 system.cpu1.dcache.ReadReq_miss_rate::total 0.002604 # miss rate for ReadReq accesses
528 system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.002467 # miss rate for WriteReq accesses
529 system.cpu1.dcache.WriteReq_miss_rate::total 0.002467 # miss rate for WriteReq accesses
530 system.cpu1.dcache.demand_miss_rate::cpu1.data 0.002561 # miss rate for demand accesses
531 system.cpu1.dcache.demand_miss_rate::total 0.002561 # miss rate for demand accesses
532 system.cpu1.dcache.overall_miss_rate::cpu1.data 0.002561 # miss rate for overall accesses
533 system.cpu1.dcache.overall_miss_rate::total 0.002561 # miss rate for overall accesses
534 system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 53933.641975 # average ReadReq miss latency
535 system.cpu1.dcache.ReadReq_avg_miss_latency::total 53933.641975 # average ReadReq miss latency
536 system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 55176.258993 # average WriteReq miss latency
537 system.cpu1.dcache.WriteReq_avg_miss_latency::total 55176.258993 # average WriteReq miss latency
538 system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 54306.695464 # average overall miss latency
539 system.cpu1.dcache.demand_avg_miss_latency::total 54306.695464 # average overall miss latency
540 system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 54306.695464 # average overall miss latency
541 system.cpu1.dcache.overall_avg_miss_latency::total 54306.695464 # average overall miss latency
542 system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
543 system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
544 system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
545 system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
546 system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
547 system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
548 system.cpu1.dcache.fast_writes 0 # number of fast writes performed
549 system.cpu1.dcache.cache_copies 0 # number of cache copies performed
550 system.cpu1.dcache.writebacks::writebacks 29 # number of writebacks
551 system.cpu1.dcache.writebacks::total 29 # number of writebacks
552 system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 324 # number of ReadReq MSHR misses
553 system.cpu1.dcache.ReadReq_mshr_misses::total 324 # number of ReadReq MSHR misses
554 system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 139 # number of WriteReq MSHR misses
555 system.cpu1.dcache.WriteReq_mshr_misses::total 139 # number of WriteReq MSHR misses
556 system.cpu1.dcache.demand_mshr_misses::cpu1.data 463 # number of demand (read+write) MSHR misses
557 system.cpu1.dcache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses
558 system.cpu1.dcache.overall_mshr_misses::cpu1.data 463 # number of overall MSHR misses
559 system.cpu1.dcache.overall_mshr_misses::total 463 # number of overall MSHR misses
560 system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 16826500 # number of ReadReq MSHR miss cycles
561 system.cpu1.dcache.ReadReq_mshr_miss_latency::total 16826500 # number of ReadReq MSHR miss cycles
562 system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 7391500 # number of WriteReq MSHR miss cycles
563 system.cpu1.dcache.WriteReq_mshr_miss_latency::total 7391500 # number of WriteReq MSHR miss cycles
564 system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 24218000 # number of demand (read+write) MSHR miss cycles
565 system.cpu1.dcache.demand_mshr_miss_latency::total 24218000 # number of demand (read+write) MSHR miss cycles
566 system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 24218000 # number of overall MSHR miss cycles
567 system.cpu1.dcache.overall_mshr_miss_latency::total 24218000 # number of overall MSHR miss cycles
568 system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.002604 # mshr miss rate for ReadReq accesses
569 system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.002604 # mshr miss rate for ReadReq accesses
570 system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002467 # mshr miss rate for WriteReq accesses
571 system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.002467 # mshr miss rate for WriteReq accesses
572 system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.002561 # mshr miss rate for demand accesses
573 system.cpu1.dcache.demand_mshr_miss_rate::total 0.002561 # mshr miss rate for demand accesses
574 system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.002561 # mshr miss rate for overall accesses
575 system.cpu1.dcache.overall_mshr_miss_rate::total 0.002561 # mshr miss rate for overall accesses
576 system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 51933.641975 # average ReadReq mshr miss latency
577 system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 51933.641975 # average ReadReq mshr miss latency
578 system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 53176.258993 # average WriteReq mshr miss latency
579 system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 53176.258993 # average WriteReq mshr miss latency
580 system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 52306.695464 # average overall mshr miss latency
581 system.cpu1.dcache.demand_avg_mshr_miss_latency::total 52306.695464 # average overall mshr miss latency
582 system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 52306.695464 # average overall mshr miss latency
583 system.cpu1.dcache.overall_avg_mshr_miss_latency::total 52306.695464 # average overall mshr miss latency
584 system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
585 system.cpu2.dtb.fetch_hits 0 # ITB hits
586 system.cpu2.dtb.fetch_misses 0 # ITB misses
587 system.cpu2.dtb.fetch_acv 0 # ITB acv
588 system.cpu2.dtb.fetch_accesses 0 # ITB accesses
589 system.cpu2.dtb.read_hits 124433 # DTB read hits
590 system.cpu2.dtb.read_misses 8 # DTB read misses
591 system.cpu2.dtb.read_acv 0 # DTB read access violations
592 system.cpu2.dtb.read_accesses 124441 # DTB read accesses
593 system.cpu2.dtb.write_hits 56339 # DTB write hits
594 system.cpu2.dtb.write_misses 10 # DTB write misses
595 system.cpu2.dtb.write_acv 0 # DTB write access violations
596 system.cpu2.dtb.write_accesses 56349 # DTB write accesses
597 system.cpu2.dtb.data_hits 180772 # DTB hits
598 system.cpu2.dtb.data_misses 18 # DTB misses
599 system.cpu2.dtb.data_acv 0 # DTB access violations
600 system.cpu2.dtb.data_accesses 180790 # DTB accesses
601 system.cpu2.itb.fetch_hits 500005 # ITB hits
602 system.cpu2.itb.fetch_misses 13 # ITB misses
603 system.cpu2.itb.fetch_acv 0 # ITB acv
604 system.cpu2.itb.fetch_accesses 500018 # ITB accesses
605 system.cpu2.itb.read_hits 0 # DTB read hits
606 system.cpu2.itb.read_misses 0 # DTB read misses
607 system.cpu2.itb.read_acv 0 # DTB read access violations
608 system.cpu2.itb.read_accesses 0 # DTB read accesses
609 system.cpu2.itb.write_hits 0 # DTB write hits
610 system.cpu2.itb.write_misses 0 # DTB write misses
611 system.cpu2.itb.write_acv 0 # DTB write access violations
612 system.cpu2.itb.write_accesses 0 # DTB write accesses
613 system.cpu2.itb.data_hits 0 # DTB hits
614 system.cpu2.itb.data_misses 0 # DTB misses
615 system.cpu2.itb.data_acv 0 # DTB access violations
616 system.cpu2.itb.data_accesses 0 # DTB accesses
617 system.cpu2.workload.num_syscalls 18 # Number of system calls
618 system.cpu2.numCycles 1458048 # number of cpu cycles simulated
619 system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
620 system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
621 system.cpu2.committedInsts 499986 # Number of instructions committed
622 system.cpu2.committedOps 499986 # Number of ops (including micro ops) committed
623 system.cpu2.num_int_alu_accesses 474674 # Number of integer alu accesses
624 system.cpu2.num_fp_alu_accesses 32 # Number of float alu accesses
625 system.cpu2.num_func_calls 14357 # number of times a function call or return occured
626 system.cpu2.num_conditional_control_insts 38179 # number of instructions that are conditional controls
627 system.cpu2.num_int_insts 474674 # number of integer instructions
628 system.cpu2.num_fp_insts 32 # number of float instructions
629 system.cpu2.num_int_register_reads 654263 # number of times the integer registers were read
630 system.cpu2.num_int_register_writes 371529 # number of times the integer registers were written
631 system.cpu2.num_fp_register_reads 32 # number of times the floating registers were read
632 system.cpu2.num_fp_register_writes 16 # number of times the floating registers were written
633 system.cpu2.num_mem_refs 180790 # number of memory refs
634 system.cpu2.num_load_insts 124441 # Number of load instructions
635 system.cpu2.num_store_insts 56349 # Number of store instructions
636 system.cpu2.num_idle_cycles 0 # Number of idle cycles
637 system.cpu2.num_busy_cycles 1458048 # Number of busy cycles
638 system.cpu2.not_idle_fraction 1 # Percentage of non-idle cycles
639 system.cpu2.idle_fraction 0 # Percentage of idle cycles
640 system.cpu2.icache.replacements 152 # number of replacements
641 system.cpu2.icache.tagsinuse 216.369218 # Cycle average of tags in use
642 system.cpu2.icache.total_refs 499542 # Total number of references to valid blocks.
643 system.cpu2.icache.sampled_refs 463 # Sample count of references to valid blocks.
644 system.cpu2.icache.avg_refs 1078.924406 # Average number of references to valid blocks.
645 system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
646 system.cpu2.icache.occ_blocks::cpu2.inst 216.369218 # Average occupied blocks per requestor
647 system.cpu2.icache.occ_percent::cpu2.inst 0.422596 # Average percentage of cache occupancy
648 system.cpu2.icache.occ_percent::total 0.422596 # Average percentage of cache occupancy
649 system.cpu2.icache.ReadReq_hits::cpu2.inst 499542 # number of ReadReq hits
650 system.cpu2.icache.ReadReq_hits::total 499542 # number of ReadReq hits
651 system.cpu2.icache.demand_hits::cpu2.inst 499542 # number of demand (read+write) hits
652 system.cpu2.icache.demand_hits::total 499542 # number of demand (read+write) hits
653 system.cpu2.icache.overall_hits::cpu2.inst 499542 # number of overall hits
654 system.cpu2.icache.overall_hits::total 499542 # number of overall hits
655 system.cpu2.icache.ReadReq_misses::cpu2.inst 463 # number of ReadReq misses
656 system.cpu2.icache.ReadReq_misses::total 463 # number of ReadReq misses
657 system.cpu2.icache.demand_misses::cpu2.inst 463 # number of demand (read+write) misses
658 system.cpu2.icache.demand_misses::total 463 # number of demand (read+write) misses
659 system.cpu2.icache.overall_misses::cpu2.inst 463 # number of overall misses
660 system.cpu2.icache.overall_misses::total 463 # number of overall misses
661 system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 23114000 # number of ReadReq miss cycles
662 system.cpu2.icache.ReadReq_miss_latency::total 23114000 # number of ReadReq miss cycles
663 system.cpu2.icache.demand_miss_latency::cpu2.inst 23114000 # number of demand (read+write) miss cycles
664 system.cpu2.icache.demand_miss_latency::total 23114000 # number of demand (read+write) miss cycles
665 system.cpu2.icache.overall_miss_latency::cpu2.inst 23114000 # number of overall miss cycles
666 system.cpu2.icache.overall_miss_latency::total 23114000 # number of overall miss cycles
667 system.cpu2.icache.ReadReq_accesses::cpu2.inst 500005 # number of ReadReq accesses(hits+misses)
668 system.cpu2.icache.ReadReq_accesses::total 500005 # number of ReadReq accesses(hits+misses)
669 system.cpu2.icache.demand_accesses::cpu2.inst 500005 # number of demand (read+write) accesses
670 system.cpu2.icache.demand_accesses::total 500005 # number of demand (read+write) accesses
671 system.cpu2.icache.overall_accesses::cpu2.inst 500005 # number of overall (read+write) accesses
672 system.cpu2.icache.overall_accesses::total 500005 # number of overall (read+write) accesses
673 system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.000926 # miss rate for ReadReq accesses
674 system.cpu2.icache.ReadReq_miss_rate::total 0.000926 # miss rate for ReadReq accesses
675 system.cpu2.icache.demand_miss_rate::cpu2.inst 0.000926 # miss rate for demand accesses
676 system.cpu2.icache.demand_miss_rate::total 0.000926 # miss rate for demand accesses
677 system.cpu2.icache.overall_miss_rate::cpu2.inst 0.000926 # miss rate for overall accesses
678 system.cpu2.icache.overall_miss_rate::total 0.000926 # miss rate for overall accesses
679 system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 49922.246220 # average ReadReq miss latency
680 system.cpu2.icache.ReadReq_avg_miss_latency::total 49922.246220 # average ReadReq miss latency
681 system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 49922.246220 # average overall miss latency
682 system.cpu2.icache.demand_avg_miss_latency::total 49922.246220 # average overall miss latency
683 system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 49922.246220 # average overall miss latency
684 system.cpu2.icache.overall_avg_miss_latency::total 49922.246220 # average overall miss latency
685 system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
686 system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
687 system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked
688 system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked
689 system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
690 system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
691 system.cpu2.icache.fast_writes 0 # number of fast writes performed
692 system.cpu2.icache.cache_copies 0 # number of cache copies performed
693 system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 463 # number of ReadReq MSHR misses
694 system.cpu2.icache.ReadReq_mshr_misses::total 463 # number of ReadReq MSHR misses
695 system.cpu2.icache.demand_mshr_misses::cpu2.inst 463 # number of demand (read+write) MSHR misses
696 system.cpu2.icache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses
697 system.cpu2.icache.overall_mshr_misses::cpu2.inst 463 # number of overall MSHR misses
698 system.cpu2.icache.overall_mshr_misses::total 463 # number of overall MSHR misses
699 system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 22188000 # number of ReadReq MSHR miss cycles
700 system.cpu2.icache.ReadReq_mshr_miss_latency::total 22188000 # number of ReadReq MSHR miss cycles
701 system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 22188000 # number of demand (read+write) MSHR miss cycles
702 system.cpu2.icache.demand_mshr_miss_latency::total 22188000 # number of demand (read+write) MSHR miss cycles
703 system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 22188000 # number of overall MSHR miss cycles
704 system.cpu2.icache.overall_mshr_miss_latency::total 22188000 # number of overall MSHR miss cycles
705 system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.000926 # mshr miss rate for ReadReq accesses
706 system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.000926 # mshr miss rate for ReadReq accesses
707 system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.000926 # mshr miss rate for demand accesses
708 system.cpu2.icache.demand_mshr_miss_rate::total 0.000926 # mshr miss rate for demand accesses
709 system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.000926 # mshr miss rate for overall accesses
710 system.cpu2.icache.overall_mshr_miss_rate::total 0.000926 # mshr miss rate for overall accesses
711 system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 47922.246220 # average ReadReq mshr miss latency
712 system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 47922.246220 # average ReadReq mshr miss latency
713 system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 47922.246220 # average overall mshr miss latency
714 system.cpu2.icache.demand_avg_mshr_miss_latency::total 47922.246220 # average overall mshr miss latency
715 system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 47922.246220 # average overall mshr miss latency
716 system.cpu2.icache.overall_avg_mshr_miss_latency::total 47922.246220 # average overall mshr miss latency
717 system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate
718 system.cpu2.dcache.replacements 61 # number of replacements
719 system.cpu2.dcache.tagsinuse 273.490220 # Cycle average of tags in use
720 system.cpu2.dcache.total_refs 180309 # Total number of references to valid blocks.
721 system.cpu2.dcache.sampled_refs 463 # Sample count of references to valid blocks.
722 system.cpu2.dcache.avg_refs 389.436285 # Average number of references to valid blocks.
723 system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
724 system.cpu2.dcache.occ_blocks::cpu2.data 273.490220 # Average occupied blocks per requestor
725 system.cpu2.dcache.occ_percent::cpu2.data 0.534161 # Average percentage of cache occupancy
726 system.cpu2.dcache.occ_percent::total 0.534161 # Average percentage of cache occupancy
727 system.cpu2.dcache.ReadReq_hits::cpu2.data 124109 # number of ReadReq hits
728 system.cpu2.dcache.ReadReq_hits::total 124109 # number of ReadReq hits
729 system.cpu2.dcache.WriteReq_hits::cpu2.data 56200 # number of WriteReq hits
730 system.cpu2.dcache.WriteReq_hits::total 56200 # number of WriteReq hits
731 system.cpu2.dcache.demand_hits::cpu2.data 180309 # number of demand (read+write) hits
732 system.cpu2.dcache.demand_hits::total 180309 # number of demand (read+write) hits
733 system.cpu2.dcache.overall_hits::cpu2.data 180309 # number of overall hits
734 system.cpu2.dcache.overall_hits::total 180309 # number of overall hits
735 system.cpu2.dcache.ReadReq_misses::cpu2.data 324 # number of ReadReq misses
736 system.cpu2.dcache.ReadReq_misses::total 324 # number of ReadReq misses
737 system.cpu2.dcache.WriteReq_misses::cpu2.data 139 # number of WriteReq misses
738 system.cpu2.dcache.WriteReq_misses::total 139 # number of WriteReq misses
739 system.cpu2.dcache.demand_misses::cpu2.data 463 # number of demand (read+write) misses
740 system.cpu2.dcache.demand_misses::total 463 # number of demand (read+write) misses
741 system.cpu2.dcache.overall_misses::cpu2.data 463 # number of overall misses
742 system.cpu2.dcache.overall_misses::total 463 # number of overall misses
743 system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 17474500 # number of ReadReq miss cycles
744 system.cpu2.dcache.ReadReq_miss_latency::total 17474500 # number of ReadReq miss cycles
745 system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 7669500 # number of WriteReq miss cycles
746 system.cpu2.dcache.WriteReq_miss_latency::total 7669500 # number of WriteReq miss cycles
747 system.cpu2.dcache.demand_miss_latency::cpu2.data 25144000 # number of demand (read+write) miss cycles
748 system.cpu2.dcache.demand_miss_latency::total 25144000 # number of demand (read+write) miss cycles
749 system.cpu2.dcache.overall_miss_latency::cpu2.data 25144000 # number of overall miss cycles
750 system.cpu2.dcache.overall_miss_latency::total 25144000 # number of overall miss cycles
751 system.cpu2.dcache.ReadReq_accesses::cpu2.data 124433 # number of ReadReq accesses(hits+misses)
752 system.cpu2.dcache.ReadReq_accesses::total 124433 # number of ReadReq accesses(hits+misses)
753 system.cpu2.dcache.WriteReq_accesses::cpu2.data 56339 # number of WriteReq accesses(hits+misses)
754 system.cpu2.dcache.WriteReq_accesses::total 56339 # number of WriteReq accesses(hits+misses)
755 system.cpu2.dcache.demand_accesses::cpu2.data 180772 # number of demand (read+write) accesses
756 system.cpu2.dcache.demand_accesses::total 180772 # number of demand (read+write) accesses
757 system.cpu2.dcache.overall_accesses::cpu2.data 180772 # number of overall (read+write) accesses
758 system.cpu2.dcache.overall_accesses::total 180772 # number of overall (read+write) accesses
759 system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.002604 # miss rate for ReadReq accesses
760 system.cpu2.dcache.ReadReq_miss_rate::total 0.002604 # miss rate for ReadReq accesses
761 system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.002467 # miss rate for WriteReq accesses
762 system.cpu2.dcache.WriteReq_miss_rate::total 0.002467 # miss rate for WriteReq accesses
763 system.cpu2.dcache.demand_miss_rate::cpu2.data 0.002561 # miss rate for demand accesses
764 system.cpu2.dcache.demand_miss_rate::total 0.002561 # miss rate for demand accesses
765 system.cpu2.dcache.overall_miss_rate::cpu2.data 0.002561 # miss rate for overall accesses
766 system.cpu2.dcache.overall_miss_rate::total 0.002561 # miss rate for overall accesses
767 system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 53933.641975 # average ReadReq miss latency
768 system.cpu2.dcache.ReadReq_avg_miss_latency::total 53933.641975 # average ReadReq miss latency
769 system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 55176.258993 # average WriteReq miss latency
770 system.cpu2.dcache.WriteReq_avg_miss_latency::total 55176.258993 # average WriteReq miss latency
771 system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 54306.695464 # average overall miss latency
772 system.cpu2.dcache.demand_avg_miss_latency::total 54306.695464 # average overall miss latency
773 system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 54306.695464 # average overall miss latency
774 system.cpu2.dcache.overall_avg_miss_latency::total 54306.695464 # average overall miss latency
775 system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
776 system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
777 system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
778 system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked
779 system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
780 system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
781 system.cpu2.dcache.fast_writes 0 # number of fast writes performed
782 system.cpu2.dcache.cache_copies 0 # number of cache copies performed
783 system.cpu2.dcache.writebacks::writebacks 29 # number of writebacks
784 system.cpu2.dcache.writebacks::total 29 # number of writebacks
785 system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 324 # number of ReadReq MSHR misses
786 system.cpu2.dcache.ReadReq_mshr_misses::total 324 # number of ReadReq MSHR misses
787 system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 139 # number of WriteReq MSHR misses
788 system.cpu2.dcache.WriteReq_mshr_misses::total 139 # number of WriteReq MSHR misses
789 system.cpu2.dcache.demand_mshr_misses::cpu2.data 463 # number of demand (read+write) MSHR misses
790 system.cpu2.dcache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses
791 system.cpu2.dcache.overall_mshr_misses::cpu2.data 463 # number of overall MSHR misses
792 system.cpu2.dcache.overall_mshr_misses::total 463 # number of overall MSHR misses
793 system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 16826500 # number of ReadReq MSHR miss cycles
794 system.cpu2.dcache.ReadReq_mshr_miss_latency::total 16826500 # number of ReadReq MSHR miss cycles
795 system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 7391500 # number of WriteReq MSHR miss cycles
796 system.cpu2.dcache.WriteReq_mshr_miss_latency::total 7391500 # number of WriteReq MSHR miss cycles
797 system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 24218000 # number of demand (read+write) MSHR miss cycles
798 system.cpu2.dcache.demand_mshr_miss_latency::total 24218000 # number of demand (read+write) MSHR miss cycles
799 system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 24218000 # number of overall MSHR miss cycles
800 system.cpu2.dcache.overall_mshr_miss_latency::total 24218000 # number of overall MSHR miss cycles
801 system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.002604 # mshr miss rate for ReadReq accesses
802 system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.002604 # mshr miss rate for ReadReq accesses
803 system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.002467 # mshr miss rate for WriteReq accesses
804 system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.002467 # mshr miss rate for WriteReq accesses
805 system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.002561 # mshr miss rate for demand accesses
806 system.cpu2.dcache.demand_mshr_miss_rate::total 0.002561 # mshr miss rate for demand accesses
807 system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.002561 # mshr miss rate for overall accesses
808 system.cpu2.dcache.overall_mshr_miss_rate::total 0.002561 # mshr miss rate for overall accesses
809 system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 51933.641975 # average ReadReq mshr miss latency
810 system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 51933.641975 # average ReadReq mshr miss latency
811 system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 53176.258993 # average WriteReq mshr miss latency
812 system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 53176.258993 # average WriteReq mshr miss latency
813 system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 52306.695464 # average overall mshr miss latency
814 system.cpu2.dcache.demand_avg_mshr_miss_latency::total 52306.695464 # average overall mshr miss latency
815 system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 52306.695464 # average overall mshr miss latency
816 system.cpu2.dcache.overall_avg_mshr_miss_latency::total 52306.695464 # average overall mshr miss latency
817 system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
818 system.cpu3.dtb.fetch_hits 0 # ITB hits
819 system.cpu3.dtb.fetch_misses 0 # ITB misses
820 system.cpu3.dtb.fetch_acv 0 # ITB acv
821 system.cpu3.dtb.fetch_accesses 0 # ITB accesses
822 system.cpu3.dtb.read_hits 124431 # DTB read hits
823 system.cpu3.dtb.read_misses 8 # DTB read misses
824 system.cpu3.dtb.read_acv 0 # DTB read access violations
825 system.cpu3.dtb.read_accesses 124439 # DTB read accesses
826 system.cpu3.dtb.write_hits 56339 # DTB write hits
827 system.cpu3.dtb.write_misses 10 # DTB write misses
828 system.cpu3.dtb.write_acv 0 # DTB write access violations
829 system.cpu3.dtb.write_accesses 56349 # DTB write accesses
830 system.cpu3.dtb.data_hits 180770 # DTB hits
831 system.cpu3.dtb.data_misses 18 # DTB misses
832 system.cpu3.dtb.data_acv 0 # DTB access violations
833 system.cpu3.dtb.data_accesses 180788 # DTB accesses
834 system.cpu3.itb.fetch_hits 499998 # ITB hits
835 system.cpu3.itb.fetch_misses 13 # ITB misses
836 system.cpu3.itb.fetch_acv 0 # ITB acv
837 system.cpu3.itb.fetch_accesses 500011 # ITB accesses
838 system.cpu3.itb.read_hits 0 # DTB read hits
839 system.cpu3.itb.read_misses 0 # DTB read misses
840 system.cpu3.itb.read_acv 0 # DTB read access violations
841 system.cpu3.itb.read_accesses 0 # DTB read accesses
842 system.cpu3.itb.write_hits 0 # DTB write hits
843 system.cpu3.itb.write_misses 0 # DTB write misses
844 system.cpu3.itb.write_acv 0 # DTB write access violations
845 system.cpu3.itb.write_accesses 0 # DTB write accesses
846 system.cpu3.itb.data_hits 0 # DTB hits
847 system.cpu3.itb.data_misses 0 # DTB misses
848 system.cpu3.itb.data_acv 0 # DTB access violations
849 system.cpu3.itb.data_accesses 0 # DTB accesses
850 system.cpu3.workload.num_syscalls 18 # Number of system calls
851 system.cpu3.numCycles 1458048 # number of cpu cycles simulated
852 system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
853 system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed
854 system.cpu3.committedInsts 499979 # Number of instructions committed
855 system.cpu3.committedOps 499979 # Number of ops (including micro ops) committed
856 system.cpu3.num_int_alu_accesses 474668 # Number of integer alu accesses
857 system.cpu3.num_fp_alu_accesses 32 # Number of float alu accesses
858 system.cpu3.num_func_calls 14357 # number of times a function call or return occured
859 system.cpu3.num_conditional_control_insts 38178 # number of instructions that are conditional controls
860 system.cpu3.num_int_insts 474668 # number of integer instructions
861 system.cpu3.num_fp_insts 32 # number of float instructions
862 system.cpu3.num_int_register_reads 654256 # number of times the integer registers were read
863 system.cpu3.num_int_register_writes 371524 # number of times the integer registers were written
864 system.cpu3.num_fp_register_reads 32 # number of times the floating registers were read
865 system.cpu3.num_fp_register_writes 16 # number of times the floating registers were written
866 system.cpu3.num_mem_refs 180788 # number of memory refs
867 system.cpu3.num_load_insts 124439 # Number of load instructions
868 system.cpu3.num_store_insts 56349 # Number of store instructions
869 system.cpu3.num_idle_cycles 0 # Number of idle cycles
870 system.cpu3.num_busy_cycles 1458048 # Number of busy cycles
871 system.cpu3.not_idle_fraction 1 # Percentage of non-idle cycles
872 system.cpu3.idle_fraction 0 # Percentage of idle cycles
873 system.cpu3.icache.replacements 152 # number of replacements
874 system.cpu3.icache.tagsinuse 216.365379 # Cycle average of tags in use
875 system.cpu3.icache.total_refs 499535 # Total number of references to valid blocks.
876 system.cpu3.icache.sampled_refs 463 # Sample count of references to valid blocks.
877 system.cpu3.icache.avg_refs 1078.909287 # Average number of references to valid blocks.
878 system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
879 system.cpu3.icache.occ_blocks::cpu3.inst 216.365379 # Average occupied blocks per requestor
880 system.cpu3.icache.occ_percent::cpu3.inst 0.422589 # Average percentage of cache occupancy
881 system.cpu3.icache.occ_percent::total 0.422589 # Average percentage of cache occupancy
882 system.cpu3.icache.ReadReq_hits::cpu3.inst 499535 # number of ReadReq hits
883 system.cpu3.icache.ReadReq_hits::total 499535 # number of ReadReq hits
884 system.cpu3.icache.demand_hits::cpu3.inst 499535 # number of demand (read+write) hits
885 system.cpu3.icache.demand_hits::total 499535 # number of demand (read+write) hits
886 system.cpu3.icache.overall_hits::cpu3.inst 499535 # number of overall hits
887 system.cpu3.icache.overall_hits::total 499535 # number of overall hits
888 system.cpu3.icache.ReadReq_misses::cpu3.inst 463 # number of ReadReq misses
889 system.cpu3.icache.ReadReq_misses::total 463 # number of ReadReq misses
890 system.cpu3.icache.demand_misses::cpu3.inst 463 # number of demand (read+write) misses
891 system.cpu3.icache.demand_misses::total 463 # number of demand (read+write) misses
892 system.cpu3.icache.overall_misses::cpu3.inst 463 # number of overall misses
893 system.cpu3.icache.overall_misses::total 463 # number of overall misses
894 system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 23123000 # number of ReadReq miss cycles
895 system.cpu3.icache.ReadReq_miss_latency::total 23123000 # number of ReadReq miss cycles
896 system.cpu3.icache.demand_miss_latency::cpu3.inst 23123000 # number of demand (read+write) miss cycles
897 system.cpu3.icache.demand_miss_latency::total 23123000 # number of demand (read+write) miss cycles
898 system.cpu3.icache.overall_miss_latency::cpu3.inst 23123000 # number of overall miss cycles
899 system.cpu3.icache.overall_miss_latency::total 23123000 # number of overall miss cycles
900 system.cpu3.icache.ReadReq_accesses::cpu3.inst 499998 # number of ReadReq accesses(hits+misses)
901 system.cpu3.icache.ReadReq_accesses::total 499998 # number of ReadReq accesses(hits+misses)
902 system.cpu3.icache.demand_accesses::cpu3.inst 499998 # number of demand (read+write) accesses
903 system.cpu3.icache.demand_accesses::total 499998 # number of demand (read+write) accesses
904 system.cpu3.icache.overall_accesses::cpu3.inst 499998 # number of overall (read+write) accesses
905 system.cpu3.icache.overall_accesses::total 499998 # number of overall (read+write) accesses
906 system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.000926 # miss rate for ReadReq accesses
907 system.cpu3.icache.ReadReq_miss_rate::total 0.000926 # miss rate for ReadReq accesses
908 system.cpu3.icache.demand_miss_rate::cpu3.inst 0.000926 # miss rate for demand accesses
909 system.cpu3.icache.demand_miss_rate::total 0.000926 # miss rate for demand accesses
910 system.cpu3.icache.overall_miss_rate::cpu3.inst 0.000926 # miss rate for overall accesses
911 system.cpu3.icache.overall_miss_rate::total 0.000926 # miss rate for overall accesses
912 system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 49941.684665 # average ReadReq miss latency
913 system.cpu3.icache.ReadReq_avg_miss_latency::total 49941.684665 # average ReadReq miss latency
914 system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 49941.684665 # average overall miss latency
915 system.cpu3.icache.demand_avg_miss_latency::total 49941.684665 # average overall miss latency
916 system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 49941.684665 # average overall miss latency
917 system.cpu3.icache.overall_avg_miss_latency::total 49941.684665 # average overall miss latency
918 system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
919 system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
920 system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked
921 system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked
922 system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
923 system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
924 system.cpu3.icache.fast_writes 0 # number of fast writes performed
925 system.cpu3.icache.cache_copies 0 # number of cache copies performed
926 system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 463 # number of ReadReq MSHR misses
927 system.cpu3.icache.ReadReq_mshr_misses::total 463 # number of ReadReq MSHR misses
928 system.cpu3.icache.demand_mshr_misses::cpu3.inst 463 # number of demand (read+write) MSHR misses
929 system.cpu3.icache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses
930 system.cpu3.icache.overall_mshr_misses::cpu3.inst 463 # number of overall MSHR misses
931 system.cpu3.icache.overall_mshr_misses::total 463 # number of overall MSHR misses
932 system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 22197000 # number of ReadReq MSHR miss cycles
933 system.cpu3.icache.ReadReq_mshr_miss_latency::total 22197000 # number of ReadReq MSHR miss cycles
934 system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 22197000 # number of demand (read+write) MSHR miss cycles
935 system.cpu3.icache.demand_mshr_miss_latency::total 22197000 # number of demand (read+write) MSHR miss cycles
936 system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 22197000 # number of overall MSHR miss cycles
937 system.cpu3.icache.overall_mshr_miss_latency::total 22197000 # number of overall MSHR miss cycles
938 system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.000926 # mshr miss rate for ReadReq accesses
939 system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.000926 # mshr miss rate for ReadReq accesses
940 system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.000926 # mshr miss rate for demand accesses
941 system.cpu3.icache.demand_mshr_miss_rate::total 0.000926 # mshr miss rate for demand accesses
942 system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.000926 # mshr miss rate for overall accesses
943 system.cpu3.icache.overall_mshr_miss_rate::total 0.000926 # mshr miss rate for overall accesses
944 system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 47941.684665 # average ReadReq mshr miss latency
945 system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 47941.684665 # average ReadReq mshr miss latency
946 system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 47941.684665 # average overall mshr miss latency
947 system.cpu3.icache.demand_avg_mshr_miss_latency::total 47941.684665 # average overall mshr miss latency
948 system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 47941.684665 # average overall mshr miss latency
949 system.cpu3.icache.overall_avg_mshr_miss_latency::total 47941.684665 # average overall mshr miss latency
950 system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate
951 system.cpu3.dcache.replacements 61 # number of replacements
952 system.cpu3.dcache.tagsinuse 273.485257 # Cycle average of tags in use
953 system.cpu3.dcache.total_refs 180307 # Total number of references to valid blocks.
954 system.cpu3.dcache.sampled_refs 463 # Sample count of references to valid blocks.
955 system.cpu3.dcache.avg_refs 389.431965 # Average number of references to valid blocks.
956 system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
957 system.cpu3.dcache.occ_blocks::cpu3.data 273.485257 # Average occupied blocks per requestor
958 system.cpu3.dcache.occ_percent::cpu3.data 0.534151 # Average percentage of cache occupancy
959 system.cpu3.dcache.occ_percent::total 0.534151 # Average percentage of cache occupancy
960 system.cpu3.dcache.ReadReq_hits::cpu3.data 124107 # number of ReadReq hits
961 system.cpu3.dcache.ReadReq_hits::total 124107 # number of ReadReq hits
962 system.cpu3.dcache.WriteReq_hits::cpu3.data 56200 # number of WriteReq hits
963 system.cpu3.dcache.WriteReq_hits::total 56200 # number of WriteReq hits
964 system.cpu3.dcache.demand_hits::cpu3.data 180307 # number of demand (read+write) hits
965 system.cpu3.dcache.demand_hits::total 180307 # number of demand (read+write) hits
966 system.cpu3.dcache.overall_hits::cpu3.data 180307 # number of overall hits
967 system.cpu3.dcache.overall_hits::total 180307 # number of overall hits
968 system.cpu3.dcache.ReadReq_misses::cpu3.data 324 # number of ReadReq misses
969 system.cpu3.dcache.ReadReq_misses::total 324 # number of ReadReq misses
970 system.cpu3.dcache.WriteReq_misses::cpu3.data 139 # number of WriteReq misses
971 system.cpu3.dcache.WriteReq_misses::total 139 # number of WriteReq misses
972 system.cpu3.dcache.demand_misses::cpu3.data 463 # number of demand (read+write) misses
973 system.cpu3.dcache.demand_misses::total 463 # number of demand (read+write) misses
974 system.cpu3.dcache.overall_misses::cpu3.data 463 # number of overall misses
975 system.cpu3.dcache.overall_misses::total 463 # number of overall misses
976 system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 17474500 # number of ReadReq miss cycles
977 system.cpu3.dcache.ReadReq_miss_latency::total 17474500 # number of ReadReq miss cycles
978 system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 7669500 # number of WriteReq miss cycles
979 system.cpu3.dcache.WriteReq_miss_latency::total 7669500 # number of WriteReq miss cycles
980 system.cpu3.dcache.demand_miss_latency::cpu3.data 25144000 # number of demand (read+write) miss cycles
981 system.cpu3.dcache.demand_miss_latency::total 25144000 # number of demand (read+write) miss cycles
982 system.cpu3.dcache.overall_miss_latency::cpu3.data 25144000 # number of overall miss cycles
983 system.cpu3.dcache.overall_miss_latency::total 25144000 # number of overall miss cycles
984 system.cpu3.dcache.ReadReq_accesses::cpu3.data 124431 # number of ReadReq accesses(hits+misses)
985 system.cpu3.dcache.ReadReq_accesses::total 124431 # number of ReadReq accesses(hits+misses)
986 system.cpu3.dcache.WriteReq_accesses::cpu3.data 56339 # number of WriteReq accesses(hits+misses)
987 system.cpu3.dcache.WriteReq_accesses::total 56339 # number of WriteReq accesses(hits+misses)
988 system.cpu3.dcache.demand_accesses::cpu3.data 180770 # number of demand (read+write) accesses
989 system.cpu3.dcache.demand_accesses::total 180770 # number of demand (read+write) accesses
990 system.cpu3.dcache.overall_accesses::cpu3.data 180770 # number of overall (read+write) accesses
991 system.cpu3.dcache.overall_accesses::total 180770 # number of overall (read+write) accesses
992 system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.002604 # miss rate for ReadReq accesses
993 system.cpu3.dcache.ReadReq_miss_rate::total 0.002604 # miss rate for ReadReq accesses
994 system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.002467 # miss rate for WriteReq accesses
995 system.cpu3.dcache.WriteReq_miss_rate::total 0.002467 # miss rate for WriteReq accesses
996 system.cpu3.dcache.demand_miss_rate::cpu3.data 0.002561 # miss rate for demand accesses
997 system.cpu3.dcache.demand_miss_rate::total 0.002561 # miss rate for demand accesses
998 system.cpu3.dcache.overall_miss_rate::cpu3.data 0.002561 # miss rate for overall accesses
999 system.cpu3.dcache.overall_miss_rate::total 0.002561 # miss rate for overall accesses
1000 system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 53933.641975 # average ReadReq miss latency
1001 system.cpu3.dcache.ReadReq_avg_miss_latency::total 53933.641975 # average ReadReq miss latency
1002 system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 55176.258993 # average WriteReq miss latency
1003 system.cpu3.dcache.WriteReq_avg_miss_latency::total 55176.258993 # average WriteReq miss latency
1004 system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 54306.695464 # average overall miss latency
1005 system.cpu3.dcache.demand_avg_miss_latency::total 54306.695464 # average overall miss latency
1006 system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 54306.695464 # average overall miss latency
1007 system.cpu3.dcache.overall_avg_miss_latency::total 54306.695464 # average overall miss latency
1008 system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1009 system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1010 system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
1011 system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked
1012 system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1013 system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1014 system.cpu3.dcache.fast_writes 0 # number of fast writes performed
1015 system.cpu3.dcache.cache_copies 0 # number of cache copies performed
1016 system.cpu3.dcache.writebacks::writebacks 29 # number of writebacks
1017 system.cpu3.dcache.writebacks::total 29 # number of writebacks
1018 system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 324 # number of ReadReq MSHR misses
1019 system.cpu3.dcache.ReadReq_mshr_misses::total 324 # number of ReadReq MSHR misses
1020 system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 139 # number of WriteReq MSHR misses
1021 system.cpu3.dcache.WriteReq_mshr_misses::total 139 # number of WriteReq MSHR misses
1022 system.cpu3.dcache.demand_mshr_misses::cpu3.data 463 # number of demand (read+write) MSHR misses
1023 system.cpu3.dcache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses
1024 system.cpu3.dcache.overall_mshr_misses::cpu3.data 463 # number of overall MSHR misses
1025 system.cpu3.dcache.overall_mshr_misses::total 463 # number of overall MSHR misses
1026 system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 16826500 # number of ReadReq MSHR miss cycles
1027 system.cpu3.dcache.ReadReq_mshr_miss_latency::total 16826500 # number of ReadReq MSHR miss cycles
1028 system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 7391500 # number of WriteReq MSHR miss cycles
1029 system.cpu3.dcache.WriteReq_mshr_miss_latency::total 7391500 # number of WriteReq MSHR miss cycles
1030 system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 24218000 # number of demand (read+write) MSHR miss cycles
1031 system.cpu3.dcache.demand_mshr_miss_latency::total 24218000 # number of demand (read+write) MSHR miss cycles
1032 system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 24218000 # number of overall MSHR miss cycles
1033 system.cpu3.dcache.overall_mshr_miss_latency::total 24218000 # number of overall MSHR miss cycles
1034 system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.002604 # mshr miss rate for ReadReq accesses
1035 system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.002604 # mshr miss rate for ReadReq accesses
1036 system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.002467 # mshr miss rate for WriteReq accesses
1037 system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.002467 # mshr miss rate for WriteReq accesses
1038 system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.002561 # mshr miss rate for demand accesses
1039 system.cpu3.dcache.demand_mshr_miss_rate::total 0.002561 # mshr miss rate for demand accesses
1040 system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.002561 # mshr miss rate for overall accesses
1041 system.cpu3.dcache.overall_mshr_miss_rate::total 0.002561 # mshr miss rate for overall accesses
1042 system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 51933.641975 # average ReadReq mshr miss latency
1043 system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 51933.641975 # average ReadReq mshr miss latency
1044 system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 53176.258993 # average WriteReq mshr miss latency
1045 system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 53176.258993 # average WriteReq mshr miss latency
1046 system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 52306.695464 # average overall mshr miss latency
1047 system.cpu3.dcache.demand_avg_mshr_miss_latency::total 52306.695464 # average overall mshr miss latency
1048 system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 52306.695464 # average overall mshr miss latency
1049 system.cpu3.dcache.overall_avg_mshr_miss_latency::total 52306.695464 # average overall mshr miss latency
1050 system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1051 system.l2c.replacements 0 # number of replacements
1052 system.l2c.tagsinuse 1943.172107 # Cycle average of tags in use
1053 system.l2c.total_refs 332 # Total number of references to valid blocks.
1054 system.l2c.sampled_refs 2932 # Sample count of references to valid blocks.
1055 system.l2c.avg_refs 0.113233 # Average number of references to valid blocks.
1056 system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1057 system.l2c.occ_blocks::writebacks 17.224555 # Average occupied blocks per requestor
1058 system.l2c.occ_blocks::cpu0.inst 265.011494 # Average occupied blocks per requestor
1059 system.l2c.occ_blocks::cpu0.data 216.488870 # Average occupied blocks per requestor
1060 system.l2c.occ_blocks::cpu1.inst 265.006320 # Average occupied blocks per requestor
1061 system.l2c.occ_blocks::cpu1.data 216.484940 # Average occupied blocks per requestor
1062 system.l2c.occ_blocks::cpu2.inst 265.001344 # Average occupied blocks per requestor
1063 system.l2c.occ_blocks::cpu2.data 216.481052 # Average occupied blocks per requestor
1064 system.l2c.occ_blocks::cpu3.inst 264.996369 # Average occupied blocks per requestor
1065 system.l2c.occ_blocks::cpu3.data 216.477163 # Average occupied blocks per requestor
1066 system.l2c.occ_percent::writebacks 0.000263 # Average percentage of cache occupancy
1067 system.l2c.occ_percent::cpu0.inst 0.004044 # Average percentage of cache occupancy
1068 system.l2c.occ_percent::cpu0.data 0.003303 # Average percentage of cache occupancy
1069 system.l2c.occ_percent::cpu1.inst 0.004044 # Average percentage of cache occupancy
1070 system.l2c.occ_percent::cpu1.data 0.003303 # Average percentage of cache occupancy
1071 system.l2c.occ_percent::cpu2.inst 0.004044 # Average percentage of cache occupancy
1072 system.l2c.occ_percent::cpu2.data 0.003303 # Average percentage of cache occupancy
1073 system.l2c.occ_percent::cpu3.inst 0.004044 # Average percentage of cache occupancy
1074 system.l2c.occ_percent::cpu3.data 0.003303 # Average percentage of cache occupancy
1075 system.l2c.occ_percent::total 0.029650 # Average percentage of cache occupancy
1076 system.l2c.ReadReq_hits::cpu0.inst 60 # number of ReadReq hits
1077 system.l2c.ReadReq_hits::cpu0.data 9 # number of ReadReq hits
1078 system.l2c.ReadReq_hits::cpu1.inst 60 # number of ReadReq hits
1079 system.l2c.ReadReq_hits::cpu1.data 9 # number of ReadReq hits
1080 system.l2c.ReadReq_hits::cpu2.inst 60 # number of ReadReq hits
1081 system.l2c.ReadReq_hits::cpu2.data 9 # number of ReadReq hits
1082 system.l2c.ReadReq_hits::cpu3.inst 60 # number of ReadReq hits
1083 system.l2c.ReadReq_hits::cpu3.data 9 # number of ReadReq hits
1084 system.l2c.ReadReq_hits::total 276 # number of ReadReq hits
1085 system.l2c.Writeback_hits::writebacks 116 # number of Writeback hits
1086 system.l2c.Writeback_hits::total 116 # number of Writeback hits
1087 system.l2c.demand_hits::cpu0.inst 60 # number of demand (read+write) hits
1088 system.l2c.demand_hits::cpu0.data 9 # number of demand (read+write) hits
1089 system.l2c.demand_hits::cpu1.inst 60 # number of demand (read+write) hits
1090 system.l2c.demand_hits::cpu1.data 9 # number of demand (read+write) hits
1091 system.l2c.demand_hits::cpu2.inst 60 # number of demand (read+write) hits
1092 system.l2c.demand_hits::cpu2.data 9 # number of demand (read+write) hits
1093 system.l2c.demand_hits::cpu3.inst 60 # number of demand (read+write) hits
1094 system.l2c.demand_hits::cpu3.data 9 # number of demand (read+write) hits
1095 system.l2c.demand_hits::total 276 # number of demand (read+write) hits
1096 system.l2c.overall_hits::cpu0.inst 60 # number of overall hits
1097 system.l2c.overall_hits::cpu0.data 9 # number of overall hits
1098 system.l2c.overall_hits::cpu1.inst 60 # number of overall hits
1099 system.l2c.overall_hits::cpu1.data 9 # number of overall hits
1100 system.l2c.overall_hits::cpu2.inst 60 # number of overall hits
1101 system.l2c.overall_hits::cpu2.data 9 # number of overall hits
1102 system.l2c.overall_hits::cpu3.inst 60 # number of overall hits
1103 system.l2c.overall_hits::cpu3.data 9 # number of overall hits
1104 system.l2c.overall_hits::total 276 # number of overall hits
1105 system.l2c.ReadReq_misses::cpu0.inst 403 # number of ReadReq misses
1106 system.l2c.ReadReq_misses::cpu0.data 315 # number of ReadReq misses
1107 system.l2c.ReadReq_misses::cpu1.inst 403 # number of ReadReq misses
1108 system.l2c.ReadReq_misses::cpu1.data 315 # number of ReadReq misses
1109 system.l2c.ReadReq_misses::cpu2.inst 403 # number of ReadReq misses
1110 system.l2c.ReadReq_misses::cpu2.data 315 # number of ReadReq misses
1111 system.l2c.ReadReq_misses::cpu3.inst 403 # number of ReadReq misses
1112 system.l2c.ReadReq_misses::cpu3.data 315 # number of ReadReq misses
1113 system.l2c.ReadReq_misses::total 2872 # number of ReadReq misses
1114 system.l2c.ReadExReq_misses::cpu0.data 139 # number of ReadExReq misses
1115 system.l2c.ReadExReq_misses::cpu1.data 139 # number of ReadExReq misses
1116 system.l2c.ReadExReq_misses::cpu2.data 139 # number of ReadExReq misses
1117 system.l2c.ReadExReq_misses::cpu3.data 139 # number of ReadExReq misses
1118 system.l2c.ReadExReq_misses::total 556 # number of ReadExReq misses
1119 system.l2c.demand_misses::cpu0.inst 403 # number of demand (read+write) misses
1120 system.l2c.demand_misses::cpu0.data 454 # number of demand (read+write) misses
1121 system.l2c.demand_misses::cpu1.inst 403 # number of demand (read+write) misses
1122 system.l2c.demand_misses::cpu1.data 454 # number of demand (read+write) misses
1123 system.l2c.demand_misses::cpu2.inst 403 # number of demand (read+write) misses
1124 system.l2c.demand_misses::cpu2.data 454 # number of demand (read+write) misses
1125 system.l2c.demand_misses::cpu3.inst 403 # number of demand (read+write) misses
1126 system.l2c.demand_misses::cpu3.data 454 # number of demand (read+write) misses
1127 system.l2c.demand_misses::total 3428 # number of demand (read+write) misses
1128 system.l2c.overall_misses::cpu0.inst 403 # number of overall misses
1129 system.l2c.overall_misses::cpu0.data 454 # number of overall misses
1130 system.l2c.overall_misses::cpu1.inst 403 # number of overall misses
1131 system.l2c.overall_misses::cpu1.data 454 # number of overall misses
1132 system.l2c.overall_misses::cpu2.inst 403 # number of overall misses
1133 system.l2c.overall_misses::cpu2.data 454 # number of overall misses
1134 system.l2c.overall_misses::cpu3.inst 403 # number of overall misses
1135 system.l2c.overall_misses::cpu3.data 454 # number of overall misses
1136 system.l2c.overall_misses::total 3428 # number of overall misses
1137 system.l2c.ReadReq_miss_latency::cpu0.inst 21101500 # number of ReadReq miss cycles
1138 system.l2c.ReadReq_miss_latency::cpu0.data 16409500 # number of ReadReq miss cycles
1139 system.l2c.ReadReq_miss_latency::cpu1.inst 21110000 # number of ReadReq miss cycles
1140 system.l2c.ReadReq_miss_latency::cpu1.data 16409500 # number of ReadReq miss cycles
1141 system.l2c.ReadReq_miss_latency::cpu2.inst 21118500 # number of ReadReq miss cycles
1142 system.l2c.ReadReq_miss_latency::cpu2.data 16409500 # number of ReadReq miss cycles
1143 system.l2c.ReadReq_miss_latency::cpu3.inst 21129500 # number of ReadReq miss cycles
1144 system.l2c.ReadReq_miss_latency::cpu3.data 16412000 # number of ReadReq miss cycles
1145 system.l2c.ReadReq_miss_latency::total 150100000 # number of ReadReq miss cycles
1146 system.l2c.ReadExReq_miss_latency::cpu0.data 7252500 # number of ReadExReq miss cycles
1147 system.l2c.ReadExReq_miss_latency::cpu1.data 7252500 # number of ReadExReq miss cycles
1148 system.l2c.ReadExReq_miss_latency::cpu2.data 7252500 # number of ReadExReq miss cycles
1149 system.l2c.ReadExReq_miss_latency::cpu3.data 7252500 # number of ReadExReq miss cycles
1150 system.l2c.ReadExReq_miss_latency::total 29010000 # number of ReadExReq miss cycles
1151 system.l2c.demand_miss_latency::cpu0.inst 21101500 # number of demand (read+write) miss cycles
1152 system.l2c.demand_miss_latency::cpu0.data 23662000 # number of demand (read+write) miss cycles
1153 system.l2c.demand_miss_latency::cpu1.inst 21110000 # number of demand (read+write) miss cycles
1154 system.l2c.demand_miss_latency::cpu1.data 23662000 # number of demand (read+write) miss cycles
1155 system.l2c.demand_miss_latency::cpu2.inst 21118500 # number of demand (read+write) miss cycles
1156 system.l2c.demand_miss_latency::cpu2.data 23662000 # number of demand (read+write) miss cycles
1157 system.l2c.demand_miss_latency::cpu3.inst 21129500 # number of demand (read+write) miss cycles
1158 system.l2c.demand_miss_latency::cpu3.data 23664500 # number of demand (read+write) miss cycles
1159 system.l2c.demand_miss_latency::total 179110000 # number of demand (read+write) miss cycles
1160 system.l2c.overall_miss_latency::cpu0.inst 21101500 # number of overall miss cycles
1161 system.l2c.overall_miss_latency::cpu0.data 23662000 # number of overall miss cycles
1162 system.l2c.overall_miss_latency::cpu1.inst 21110000 # number of overall miss cycles
1163 system.l2c.overall_miss_latency::cpu1.data 23662000 # number of overall miss cycles
1164 system.l2c.overall_miss_latency::cpu2.inst 21118500 # number of overall miss cycles
1165 system.l2c.overall_miss_latency::cpu2.data 23662000 # number of overall miss cycles
1166 system.l2c.overall_miss_latency::cpu3.inst 21129500 # number of overall miss cycles
1167 system.l2c.overall_miss_latency::cpu3.data 23664500 # number of overall miss cycles
1168 system.l2c.overall_miss_latency::total 179110000 # number of overall miss cycles
1169 system.l2c.ReadReq_accesses::cpu0.inst 463 # number of ReadReq accesses(hits+misses)
1170 system.l2c.ReadReq_accesses::cpu0.data 324 # number of ReadReq accesses(hits+misses)
1171 system.l2c.ReadReq_accesses::cpu1.inst 463 # number of ReadReq accesses(hits+misses)
1172 system.l2c.ReadReq_accesses::cpu1.data 324 # number of ReadReq accesses(hits+misses)
1173 system.l2c.ReadReq_accesses::cpu2.inst 463 # number of ReadReq accesses(hits+misses)
1174 system.l2c.ReadReq_accesses::cpu2.data 324 # number of ReadReq accesses(hits+misses)
1175 system.l2c.ReadReq_accesses::cpu3.inst 463 # number of ReadReq accesses(hits+misses)
1176 system.l2c.ReadReq_accesses::cpu3.data 324 # number of ReadReq accesses(hits+misses)
1177 system.l2c.ReadReq_accesses::total 3148 # number of ReadReq accesses(hits+misses)
1178 system.l2c.Writeback_accesses::writebacks 116 # number of Writeback accesses(hits+misses)
1179 system.l2c.Writeback_accesses::total 116 # number of Writeback accesses(hits+misses)
1180 system.l2c.ReadExReq_accesses::cpu0.data 139 # number of ReadExReq accesses(hits+misses)
1181 system.l2c.ReadExReq_accesses::cpu1.data 139 # number of ReadExReq accesses(hits+misses)
1182 system.l2c.ReadExReq_accesses::cpu2.data 139 # number of ReadExReq accesses(hits+misses)
1183 system.l2c.ReadExReq_accesses::cpu3.data 139 # number of ReadExReq accesses(hits+misses)
1184 system.l2c.ReadExReq_accesses::total 556 # number of ReadExReq accesses(hits+misses)
1185 system.l2c.demand_accesses::cpu0.inst 463 # number of demand (read+write) accesses
1186 system.l2c.demand_accesses::cpu0.data 463 # number of demand (read+write) accesses
1187 system.l2c.demand_accesses::cpu1.inst 463 # number of demand (read+write) accesses
1188 system.l2c.demand_accesses::cpu1.data 463 # number of demand (read+write) accesses
1189 system.l2c.demand_accesses::cpu2.inst 463 # number of demand (read+write) accesses
1190 system.l2c.demand_accesses::cpu2.data 463 # number of demand (read+write) accesses
1191 system.l2c.demand_accesses::cpu3.inst 463 # number of demand (read+write) accesses
1192 system.l2c.demand_accesses::cpu3.data 463 # number of demand (read+write) accesses
1193 system.l2c.demand_accesses::total 3704 # number of demand (read+write) accesses
1194 system.l2c.overall_accesses::cpu0.inst 463 # number of overall (read+write) accesses
1195 system.l2c.overall_accesses::cpu0.data 463 # number of overall (read+write) accesses
1196 system.l2c.overall_accesses::cpu1.inst 463 # number of overall (read+write) accesses
1197 system.l2c.overall_accesses::cpu1.data 463 # number of overall (read+write) accesses
1198 system.l2c.overall_accesses::cpu2.inst 463 # number of overall (read+write) accesses
1199 system.l2c.overall_accesses::cpu2.data 463 # number of overall (read+write) accesses
1200 system.l2c.overall_accesses::cpu3.inst 463 # number of overall (read+write) accesses
1201 system.l2c.overall_accesses::cpu3.data 463 # number of overall (read+write) accesses
1202 system.l2c.overall_accesses::total 3704 # number of overall (read+write) accesses
1203 system.l2c.ReadReq_miss_rate::cpu0.inst 0.870410 # miss rate for ReadReq accesses
1204 system.l2c.ReadReq_miss_rate::cpu0.data 0.972222 # miss rate for ReadReq accesses
1205 system.l2c.ReadReq_miss_rate::cpu1.inst 0.870410 # miss rate for ReadReq accesses
1206 system.l2c.ReadReq_miss_rate::cpu1.data 0.972222 # miss rate for ReadReq accesses
1207 system.l2c.ReadReq_miss_rate::cpu2.inst 0.870410 # miss rate for ReadReq accesses
1208 system.l2c.ReadReq_miss_rate::cpu2.data 0.972222 # miss rate for ReadReq accesses
1209 system.l2c.ReadReq_miss_rate::cpu3.inst 0.870410 # miss rate for ReadReq accesses
1210 system.l2c.ReadReq_miss_rate::cpu3.data 0.972222 # miss rate for ReadReq accesses
1211 system.l2c.ReadReq_miss_rate::total 0.912325 # miss rate for ReadReq accesses
1212 system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses
1213 system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses
1214 system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses
1215 system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses
1216 system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
1217 system.l2c.demand_miss_rate::cpu0.inst 0.870410 # miss rate for demand accesses
1218 system.l2c.demand_miss_rate::cpu0.data 0.980562 # miss rate for demand accesses
1219 system.l2c.demand_miss_rate::cpu1.inst 0.870410 # miss rate for demand accesses
1220 system.l2c.demand_miss_rate::cpu1.data 0.980562 # miss rate for demand accesses
1221 system.l2c.demand_miss_rate::cpu2.inst 0.870410 # miss rate for demand accesses
1222 system.l2c.demand_miss_rate::cpu2.data 0.980562 # miss rate for demand accesses
1223 system.l2c.demand_miss_rate::cpu3.inst 0.870410 # miss rate for demand accesses
1224 system.l2c.demand_miss_rate::cpu3.data 0.980562 # miss rate for demand accesses
1225 system.l2c.demand_miss_rate::total 0.925486 # miss rate for demand accesses
1226 system.l2c.overall_miss_rate::cpu0.inst 0.870410 # miss rate for overall accesses
1227 system.l2c.overall_miss_rate::cpu0.data 0.980562 # miss rate for overall accesses
1228 system.l2c.overall_miss_rate::cpu1.inst 0.870410 # miss rate for overall accesses
1229 system.l2c.overall_miss_rate::cpu1.data 0.980562 # miss rate for overall accesses
1230 system.l2c.overall_miss_rate::cpu2.inst 0.870410 # miss rate for overall accesses
1231 system.l2c.overall_miss_rate::cpu2.data 0.980562 # miss rate for overall accesses
1232 system.l2c.overall_miss_rate::cpu3.inst 0.870410 # miss rate for overall accesses
1233 system.l2c.overall_miss_rate::cpu3.data 0.980562 # miss rate for overall accesses
1234 system.l2c.overall_miss_rate::total 0.925486 # miss rate for overall accesses
1235 system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52361.042184 # average ReadReq miss latency
1236 system.l2c.ReadReq_avg_miss_latency::cpu0.data 52093.650794 # average ReadReq miss latency
1237 system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52382.133995 # average ReadReq miss latency
1238 system.l2c.ReadReq_avg_miss_latency::cpu1.data 52093.650794 # average ReadReq miss latency
1239 system.l2c.ReadReq_avg_miss_latency::cpu2.inst 52403.225806 # average ReadReq miss latency
1240 system.l2c.ReadReq_avg_miss_latency::cpu2.data 52093.650794 # average ReadReq miss latency
1241 system.l2c.ReadReq_avg_miss_latency::cpu3.inst 52430.521092 # average ReadReq miss latency
1242 system.l2c.ReadReq_avg_miss_latency::cpu3.data 52101.587302 # average ReadReq miss latency
1243 system.l2c.ReadReq_avg_miss_latency::total 52263.231198 # average ReadReq miss latency
1244 system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52176.258993 # average ReadExReq miss latency
1245 system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52176.258993 # average ReadExReq miss latency
1246 system.l2c.ReadExReq_avg_miss_latency::cpu2.data 52176.258993 # average ReadExReq miss latency
1247 system.l2c.ReadExReq_avg_miss_latency::cpu3.data 52176.258993 # average ReadExReq miss latency
1248 system.l2c.ReadExReq_avg_miss_latency::total 52176.258993 # average ReadExReq miss latency
1249 system.l2c.demand_avg_miss_latency::cpu0.inst 52361.042184 # average overall miss latency
1250 system.l2c.demand_avg_miss_latency::cpu0.data 52118.942731 # average overall miss latency
1251 system.l2c.demand_avg_miss_latency::cpu1.inst 52382.133995 # average overall miss latency
1252 system.l2c.demand_avg_miss_latency::cpu1.data 52118.942731 # average overall miss latency
1253 system.l2c.demand_avg_miss_latency::cpu2.inst 52403.225806 # average overall miss latency
1254 system.l2c.demand_avg_miss_latency::cpu2.data 52118.942731 # average overall miss latency
1255 system.l2c.demand_avg_miss_latency::cpu3.inst 52430.521092 # average overall miss latency
1256 system.l2c.demand_avg_miss_latency::cpu3.data 52124.449339 # average overall miss latency
1257 system.l2c.demand_avg_miss_latency::total 52249.124854 # average overall miss latency
1258 system.l2c.overall_avg_miss_latency::cpu0.inst 52361.042184 # average overall miss latency
1259 system.l2c.overall_avg_miss_latency::cpu0.data 52118.942731 # average overall miss latency
1260 system.l2c.overall_avg_miss_latency::cpu1.inst 52382.133995 # average overall miss latency
1261 system.l2c.overall_avg_miss_latency::cpu1.data 52118.942731 # average overall miss latency
1262 system.l2c.overall_avg_miss_latency::cpu2.inst 52403.225806 # average overall miss latency
1263 system.l2c.overall_avg_miss_latency::cpu2.data 52118.942731 # average overall miss latency
1264 system.l2c.overall_avg_miss_latency::cpu3.inst 52430.521092 # average overall miss latency
1265 system.l2c.overall_avg_miss_latency::cpu3.data 52124.449339 # average overall miss latency
1266 system.l2c.overall_avg_miss_latency::total 52249.124854 # average overall miss latency
1267 system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1268 system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
1269 system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
1270 system.l2c.blocked::no_targets 0 # number of cycles access was blocked
1271 system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1272 system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1273 system.l2c.fast_writes 0 # number of fast writes performed
1274 system.l2c.cache_copies 0 # number of cache copies performed
1275 system.l2c.ReadReq_mshr_misses::cpu0.inst 403 # number of ReadReq MSHR misses
1276 system.l2c.ReadReq_mshr_misses::cpu0.data 315 # number of ReadReq MSHR misses
1277 system.l2c.ReadReq_mshr_misses::cpu1.inst 403 # number of ReadReq MSHR misses
1278 system.l2c.ReadReq_mshr_misses::cpu1.data 315 # number of ReadReq MSHR misses
1279 system.l2c.ReadReq_mshr_misses::cpu2.inst 403 # number of ReadReq MSHR misses
1280 system.l2c.ReadReq_mshr_misses::cpu2.data 315 # number of ReadReq MSHR misses
1281 system.l2c.ReadReq_mshr_misses::cpu3.inst 403 # number of ReadReq MSHR misses
1282 system.l2c.ReadReq_mshr_misses::cpu3.data 315 # number of ReadReq MSHR misses
1283 system.l2c.ReadReq_mshr_misses::total 2872 # number of ReadReq MSHR misses
1284 system.l2c.ReadExReq_mshr_misses::cpu0.data 139 # number of ReadExReq MSHR misses
1285 system.l2c.ReadExReq_mshr_misses::cpu1.data 139 # number of ReadExReq MSHR misses
1286 system.l2c.ReadExReq_mshr_misses::cpu2.data 139 # number of ReadExReq MSHR misses
1287 system.l2c.ReadExReq_mshr_misses::cpu3.data 139 # number of ReadExReq MSHR misses
1288 system.l2c.ReadExReq_mshr_misses::total 556 # number of ReadExReq MSHR misses
1289 system.l2c.demand_mshr_misses::cpu0.inst 403 # number of demand (read+write) MSHR misses
1290 system.l2c.demand_mshr_misses::cpu0.data 454 # number of demand (read+write) MSHR misses
1291 system.l2c.demand_mshr_misses::cpu1.inst 403 # number of demand (read+write) MSHR misses
1292 system.l2c.demand_mshr_misses::cpu1.data 454 # number of demand (read+write) MSHR misses
1293 system.l2c.demand_mshr_misses::cpu2.inst 403 # number of demand (read+write) MSHR misses
1294 system.l2c.demand_mshr_misses::cpu2.data 454 # number of demand (read+write) MSHR misses
1295 system.l2c.demand_mshr_misses::cpu3.inst 403 # number of demand (read+write) MSHR misses
1296 system.l2c.demand_mshr_misses::cpu3.data 454 # number of demand (read+write) MSHR misses
1297 system.l2c.demand_mshr_misses::total 3428 # number of demand (read+write) MSHR misses
1298 system.l2c.overall_mshr_misses::cpu0.inst 403 # number of overall MSHR misses
1299 system.l2c.overall_mshr_misses::cpu0.data 454 # number of overall MSHR misses
1300 system.l2c.overall_mshr_misses::cpu1.inst 403 # number of overall MSHR misses
1301 system.l2c.overall_mshr_misses::cpu1.data 454 # number of overall MSHR misses
1302 system.l2c.overall_mshr_misses::cpu2.inst 403 # number of overall MSHR misses
1303 system.l2c.overall_mshr_misses::cpu2.data 454 # number of overall MSHR misses
1304 system.l2c.overall_mshr_misses::cpu3.inst 403 # number of overall MSHR misses
1305 system.l2c.overall_mshr_misses::cpu3.data 454 # number of overall MSHR misses
1306 system.l2c.overall_mshr_misses::total 3428 # number of overall MSHR misses
1307 system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 16120000 # number of ReadReq MSHR miss cycles
1308 system.l2c.ReadReq_mshr_miss_latency::cpu0.data 12600000 # number of ReadReq MSHR miss cycles
1309 system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 16274000 # number of ReadReq MSHR miss cycles
1310 system.l2c.ReadReq_mshr_miss_latency::cpu1.data 12629500 # number of ReadReq MSHR miss cycles
1311 system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 16282500 # number of ReadReq MSHR miss cycles
1312 system.l2c.ReadReq_mshr_miss_latency::cpu2.data 12629500 # number of ReadReq MSHR miss cycles
1313 system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 16293500 # number of ReadReq MSHR miss cycles
1314 system.l2c.ReadReq_mshr_miss_latency::cpu3.data 12632000 # number of ReadReq MSHR miss cycles
1315 system.l2c.ReadReq_mshr_miss_latency::total 115461000 # number of ReadReq MSHR miss cycles
1316 system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 5560000 # number of ReadExReq MSHR miss cycles
1317 system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 5584500 # number of ReadExReq MSHR miss cycles
1318 system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 5584500 # number of ReadExReq MSHR miss cycles
1319 system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 5584500 # number of ReadExReq MSHR miss cycles
1320 system.l2c.ReadExReq_mshr_miss_latency::total 22313500 # number of ReadExReq MSHR miss cycles
1321 system.l2c.demand_mshr_miss_latency::cpu0.inst 16120000 # number of demand (read+write) MSHR miss cycles
1322 system.l2c.demand_mshr_miss_latency::cpu0.data 18160000 # number of demand (read+write) MSHR miss cycles
1323 system.l2c.demand_mshr_miss_latency::cpu1.inst 16274000 # number of demand (read+write) MSHR miss cycles
1324 system.l2c.demand_mshr_miss_latency::cpu1.data 18214000 # number of demand (read+write) MSHR miss cycles
1325 system.l2c.demand_mshr_miss_latency::cpu2.inst 16282500 # number of demand (read+write) MSHR miss cycles
1326 system.l2c.demand_mshr_miss_latency::cpu2.data 18214000 # number of demand (read+write) MSHR miss cycles
1327 system.l2c.demand_mshr_miss_latency::cpu3.inst 16293500 # number of demand (read+write) MSHR miss cycles
1328 system.l2c.demand_mshr_miss_latency::cpu3.data 18216500 # number of demand (read+write) MSHR miss cycles
1329 system.l2c.demand_mshr_miss_latency::total 137774500 # number of demand (read+write) MSHR miss cycles
1330 system.l2c.overall_mshr_miss_latency::cpu0.inst 16120000 # number of overall MSHR miss cycles
1331 system.l2c.overall_mshr_miss_latency::cpu0.data 18160000 # number of overall MSHR miss cycles
1332 system.l2c.overall_mshr_miss_latency::cpu1.inst 16274000 # number of overall MSHR miss cycles
1333 system.l2c.overall_mshr_miss_latency::cpu1.data 18214000 # number of overall MSHR miss cycles
1334 system.l2c.overall_mshr_miss_latency::cpu2.inst 16282500 # number of overall MSHR miss cycles
1335 system.l2c.overall_mshr_miss_latency::cpu2.data 18214000 # number of overall MSHR miss cycles
1336 system.l2c.overall_mshr_miss_latency::cpu3.inst 16293500 # number of overall MSHR miss cycles
1337 system.l2c.overall_mshr_miss_latency::cpu3.data 18216500 # number of overall MSHR miss cycles
1338 system.l2c.overall_mshr_miss_latency::total 137774500 # number of overall MSHR miss cycles
1339 system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.870410 # mshr miss rate for ReadReq accesses
1340 system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.972222 # mshr miss rate for ReadReq accesses
1341 system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.870410 # mshr miss rate for ReadReq accesses
1342 system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.972222 # mshr miss rate for ReadReq accesses
1343 system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.870410 # mshr miss rate for ReadReq accesses
1344 system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.972222 # mshr miss rate for ReadReq accesses
1345 system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.870410 # mshr miss rate for ReadReq accesses
1346 system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.972222 # mshr miss rate for ReadReq accesses
1347 system.l2c.ReadReq_mshr_miss_rate::total 0.912325 # mshr miss rate for ReadReq accesses
1348 system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses
1349 system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses
1350 system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses
1351 system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses
1352 system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
1353 system.l2c.demand_mshr_miss_rate::cpu0.inst 0.870410 # mshr miss rate for demand accesses
1354 system.l2c.demand_mshr_miss_rate::cpu0.data 0.980562 # mshr miss rate for demand accesses
1355 system.l2c.demand_mshr_miss_rate::cpu1.inst 0.870410 # mshr miss rate for demand accesses
1356 system.l2c.demand_mshr_miss_rate::cpu1.data 0.980562 # mshr miss rate for demand accesses
1357 system.l2c.demand_mshr_miss_rate::cpu2.inst 0.870410 # mshr miss rate for demand accesses
1358 system.l2c.demand_mshr_miss_rate::cpu2.data 0.980562 # mshr miss rate for demand accesses
1359 system.l2c.demand_mshr_miss_rate::cpu3.inst 0.870410 # mshr miss rate for demand accesses
1360 system.l2c.demand_mshr_miss_rate::cpu3.data 0.980562 # mshr miss rate for demand accesses
1361 system.l2c.demand_mshr_miss_rate::total 0.925486 # mshr miss rate for demand accesses
1362 system.l2c.overall_mshr_miss_rate::cpu0.inst 0.870410 # mshr miss rate for overall accesses
1363 system.l2c.overall_mshr_miss_rate::cpu0.data 0.980562 # mshr miss rate for overall accesses
1364 system.l2c.overall_mshr_miss_rate::cpu1.inst 0.870410 # mshr miss rate for overall accesses
1365 system.l2c.overall_mshr_miss_rate::cpu1.data 0.980562 # mshr miss rate for overall accesses
1366 system.l2c.overall_mshr_miss_rate::cpu2.inst 0.870410 # mshr miss rate for overall accesses
1367 system.l2c.overall_mshr_miss_rate::cpu2.data 0.980562 # mshr miss rate for overall accesses
1368 system.l2c.overall_mshr_miss_rate::cpu3.inst 0.870410 # mshr miss rate for overall accesses
1369 system.l2c.overall_mshr_miss_rate::cpu3.data 0.980562 # mshr miss rate for overall accesses
1370 system.l2c.overall_mshr_miss_rate::total 0.925486 # mshr miss rate for overall accesses
1371 system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40000 # average ReadReq mshr miss latency
1372 system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40000 # average ReadReq mshr miss latency
1373 system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40382.133995 # average ReadReq mshr miss latency
1374 system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40093.650794 # average ReadReq mshr miss latency
1375 system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 40403.225806 # average ReadReq mshr miss latency
1376 system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 40093.650794 # average ReadReq mshr miss latency
1377 system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 40430.521092 # average ReadReq mshr miss latency
1378 system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 40101.587302 # average ReadReq mshr miss latency
1379 system.l2c.ReadReq_avg_mshr_miss_latency::total 40202.298050 # average ReadReq mshr miss latency
1380 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40000 # average ReadExReq mshr miss latency
1381 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40176.258993 # average ReadExReq mshr miss latency
1382 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 40176.258993 # average ReadExReq mshr miss latency
1383 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 40176.258993 # average ReadExReq mshr miss latency
1384 system.l2c.ReadExReq_avg_mshr_miss_latency::total 40132.194245 # average ReadExReq mshr miss latency
1385 system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40000 # average overall mshr miss latency
1386 system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40000 # average overall mshr miss latency
1387 system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40382.133995 # average overall mshr miss latency
1388 system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40118.942731 # average overall mshr miss latency
1389 system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40403.225806 # average overall mshr miss latency
1390 system.l2c.demand_avg_mshr_miss_latency::cpu2.data 40118.942731 # average overall mshr miss latency
1391 system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 40430.521092 # average overall mshr miss latency
1392 system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40124.449339 # average overall mshr miss latency
1393 system.l2c.demand_avg_mshr_miss_latency::total 40190.927655 # average overall mshr miss latency
1394 system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40000 # average overall mshr miss latency
1395 system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40000 # average overall mshr miss latency
1396 system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40382.133995 # average overall mshr miss latency
1397 system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40118.942731 # average overall mshr miss latency
1398 system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40403.225806 # average overall mshr miss latency
1399 system.l2c.overall_avg_mshr_miss_latency::cpu2.data 40118.942731 # average overall mshr miss latency
1400 system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40430.521092 # average overall mshr miss latency
1401 system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40124.449339 # average overall mshr miss latency
1402 system.l2c.overall_avg_mshr_miss_latency::total 40190.927655 # average overall mshr miss latency
1403 system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
1405 ---------- End Simulation Statistics ----------
projects / gem5.git / blob