tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 eventq_index=0
   5 full_system=false
   6 sim_quantum=0
   7 time_sync_enable=false
   8 time_sync_period=100000000000
   9 time_sync_spin_threshold=100000000
  10
  11 [system]
  12 type=System
  13 children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu_clk_domain dvfs_handler l2c membus physmem toL2Bus voltage_domain
  14 boot_osflags=a
  15 cache_line_size=64
  16 clk_domain=system.clk_domain
  17 eventq_index=0
  18 init_param=0
  19 kernel=
  20 kernel_addr_check=true
  21 load_addr_mask=1099511627775
  22 load_offset=0
  23 mem_mode=timing
  24 mem_ranges=
  25 memories=system.physmem
  26 num_work_ids=16
  27 readfile=
  28 symbolfile=
  29 work_begin_ckpt_count=0
  30 work_begin_cpu_id_exit=-1
  31 work_begin_exit_count=0
  32 work_cpus_ckpt_count=0
  33 work_end_ckpt_count=0
  34 work_end_exit_count=0
  35 work_item_id=-1
  36 system_port=system.membus.slave[0]
  37
  38 [system.clk_domain]
  39 type=SrcClockDomain
  40 clock=1000
  41 domain_id=-1
  42 eventq_index=0
  43 init_perf_level=0
  44 voltage_domain=system.voltage_domain
  45
  46 [system.cpu0]
  47 type=DerivO3CPU
  48 children=branchPred dcache dtb fuPool icache interrupts isa itb tracer workload
  49 LFSTSize=1024
  50 LQEntries=32
  51 LSQCheckLoads=true
  52 LSQDepCheckShift=4
  53 SQEntries=32
  54 SSITSize=1024
  55 activity=0
  56 backComSize=5
  57 branchPred=system.cpu0.branchPred
  58 cachePorts=200
  59 checker=Null
  60 clk_domain=system.cpu_clk_domain
  61 commitToDecodeDelay=1
  62 commitToFetchDelay=1
  63 commitToIEWDelay=1
  64 commitToRenameDelay=1
  65 commitWidth=8
  66 cpu_id=0
  67 decodeToFetchDelay=1
  68 decodeToRenameDelay=1
  69 decodeWidth=8
  70 dispatchWidth=8
  71 do_checkpoint_insts=true
  72 do_quiesce=true
  73 do_statistics_insts=true
  74 dtb=system.cpu0.dtb
  75 eventq_index=0
  76 fetchBufferSize=64
  77 fetchToDecodeDelay=1
  78 fetchTrapLatency=1
  79 fetchWidth=8
  80 forwardComSize=5
  81 fuPool=system.cpu0.fuPool
  82 function_trace=false
  83 function_trace_start=0
  84 iewToCommitDelay=1
  85 iewToDecodeDelay=1
  86 iewToFetchDelay=1
  87 iewToRenameDelay=1
  88 interrupts=system.cpu0.interrupts
  89 isa=system.cpu0.isa
  90 issueToExecuteDelay=1
  91 issueWidth=8
  92 itb=system.cpu0.itb
  93 max_insts_all_threads=0
  94 max_insts_any_thread=0
  95 max_loads_all_threads=0
  96 max_loads_any_thread=0
  97 needsTSO=false
  98 numIQEntries=64
  99 numPhysCCRegs=0
 100 numPhysFloatRegs=256
 101 numPhysIntRegs=256
 102 numROBEntries=192
 103 numRobs=1
 104 numThreads=1
 105 profile=0
 106 progress_interval=0
 107 renameToDecodeDelay=1
 108 renameToFetchDelay=1
 109 renameToIEWDelay=2
 110 renameToROBDelay=1
 111 renameWidth=8
 112 simpoint_start_insts=
 113 smtCommitPolicy=RoundRobin
 114 smtFetchPolicy=SingleThread
 115 smtIQPolicy=Partitioned
 116 smtIQThreshold=100
 117 smtLSQPolicy=Partitioned
 118 smtLSQThreshold=100
 119 smtNumFetchingThreads=1
 120 smtROBPolicy=Partitioned
 121 smtROBThreshold=100
 122 socket_id=0
 123 squashWidth=8
 124 store_set_clear_period=250000
 125 switched_out=false
 126 system=system
 127 tracer=system.cpu0.tracer
 128 trapLatency=13
 129 wbDepth=1
 130 wbWidth=8
 131 workload=system.cpu0.workload
 132 dcache_port=system.cpu0.dcache.cpu_side
 133 icache_port=system.cpu0.icache.cpu_side
 134
 135 [system.cpu0.branchPred]
 136 type=BranchPredictor
 137 BTBEntries=4096
 138 BTBTagSize=16
 139 RASSize=16
 140 choiceCtrBits=2
 141 choicePredictorSize=8192
 142 eventq_index=0
 143 globalCtrBits=2
 144 globalPredictorSize=8192
 145 instShiftAmt=2
 146 localCtrBits=2
 147 localHistoryTableSize=2048
 148 localPredictorSize=2048
 149 numThreads=1
 150 predType=tournament
 151
 152 [system.cpu0.dcache]
 153 type=BaseCache
 154 children=tags
 155 addr_ranges=0:18446744073709551615
 156 assoc=4
 157 clk_domain=system.cpu_clk_domain
 158 eventq_index=0
 159 forward_snoops=true
 160 hit_latency=2
 161 is_top_level=true
 162 max_miss_count=0
 163 mshrs=4
 164 prefetch_on_access=false
 165 prefetcher=Null
 166 response_latency=2
 167 sequential_access=false
 168 size=32768
 169 system=system
 170 tags=system.cpu0.dcache.tags
 171 tgts_per_mshr=20
 172 two_queue=false
 173 write_buffers=8
 174 cpu_side=system.cpu0.dcache_port
 175 mem_side=system.toL2Bus.slave[1]
 176
 177 [system.cpu0.dcache.tags]
 178 type=LRU
 179 assoc=4
 180 block_size=64
 181 clk_domain=system.cpu_clk_domain
 182 eventq_index=0
 183 hit_latency=2
 184 sequential_access=false
 185 size=32768
 186
 187 [system.cpu0.dtb]
 188 type=SparcTLB
 189 eventq_index=0
 190 size=64
 191
 192 [system.cpu0.fuPool]
 193 type=FUPool
 194 children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
 195 FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 system.cpu0.fuPool.FUList8
 196 eventq_index=0
 197
 198 [system.cpu0.fuPool.FUList0]
 199 type=FUDesc
 200 children=opList
 201 count=6
 202 eventq_index=0
 203 opList=system.cpu0.fuPool.FUList0.opList
 204
 205 [system.cpu0.fuPool.FUList0.opList]
 206 type=OpDesc
 207 eventq_index=0
 208 issueLat=1
 209 opClass=IntAlu
 210 opLat=1
 211
 212 [system.cpu0.fuPool.FUList1]
 213 type=FUDesc
 214 children=opList0 opList1
 215 count=2
 216 eventq_index=0
 217 opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1
 218
 219 [system.cpu0.fuPool.FUList1.opList0]
 220 type=OpDesc
 221 eventq_index=0
 222 issueLat=1
 223 opClass=IntMult
 224 opLat=3
 225
 226 [system.cpu0.fuPool.FUList1.opList1]
 227 type=OpDesc
 228 eventq_index=0
 229 issueLat=19
 230 opClass=IntDiv
 231 opLat=20
 232
 233 [system.cpu0.fuPool.FUList2]
 234 type=FUDesc
 235 children=opList0 opList1 opList2
 236 count=4
 237 eventq_index=0
 238 opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2
 239
 240 [system.cpu0.fuPool.FUList2.opList0]
 241 type=OpDesc
 242 eventq_index=0
 243 issueLat=1
 244 opClass=FloatAdd
 245 opLat=2
 246
 247 [system.cpu0.fuPool.FUList2.opList1]
 248 type=OpDesc
 249 eventq_index=0
 250 issueLat=1
 251 opClass=FloatCmp
 252 opLat=2
 253
 254 [system.cpu0.fuPool.FUList2.opList2]
 255 type=OpDesc
 256 eventq_index=0
 257 issueLat=1
 258 opClass=FloatCvt
 259 opLat=2
 260
 261 [system.cpu0.fuPool.FUList3]
 262 type=FUDesc
 263 children=opList0 opList1 opList2
 264 count=2
 265 eventq_index=0
 266 opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2
 267
 268 [system.cpu0.fuPool.FUList3.opList0]
 269 type=OpDesc
 270 eventq_index=0
 271 issueLat=1
 272 opClass=FloatMult
 273 opLat=4
 274
 275 [system.cpu0.fuPool.FUList3.opList1]
 276 type=OpDesc
 277 eventq_index=0
 278 issueLat=12
 279 opClass=FloatDiv
 280 opLat=12
 281
 282 [system.cpu0.fuPool.FUList3.opList2]
 283 type=OpDesc
 284 eventq_index=0
 285 issueLat=24
 286 opClass=FloatSqrt
 287 opLat=24
 288
 289 [system.cpu0.fuPool.FUList4]
 290 type=FUDesc
 291 children=opList
 292 count=0
 293 eventq_index=0
 294 opList=system.cpu0.fuPool.FUList4.opList
 295
 296 [system.cpu0.fuPool.FUList4.opList]
 297 type=OpDesc
 298 eventq_index=0
 299 issueLat=1
 300 opClass=MemRead
 301 opLat=1
 302
 303 [system.cpu0.fuPool.FUList5]
 304 type=FUDesc
 305 children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
 306 count=4
 307 eventq_index=0
 308 opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 system.cpu0.fuPool.FUList5.opList02 system.cpu0.fuPool.FUList5.opList03 system.cpu0.fuPool.FUList5.opList04 system.cpu0.fuPool.FUList5.opList05 system.cpu0.fuPool.FUList5.opList06 system.cpu0.fuPool.FUList5.opList07 system.cpu0.fuPool.FUList5.opList08 system.cpu0.fuPool.FUList5.opList09 system.cpu0.fuPool.FUList5.opList10 system.cpu0.fuPool.FUList5.opList11 system.cpu0.fuPool.FUList5.opList12 system.cpu0.fuPool.FUList5.opList13 system.cpu0.fuPool.FUList5.opList14 system.cpu0.fuPool.FUList5.opList15 system.cpu0.fuPool.FUList5.opList16 system.cpu0.fuPool.FUList5.opList17 system.cpu0.fuPool.FUList5.opList18 system.cpu0.fuPool.FUList5.opList19
 309
 310 [system.cpu0.fuPool.FUList5.opList00]
 311 type=OpDesc
 312 eventq_index=0
 313 issueLat=1
 314 opClass=SimdAdd
 315 opLat=1
 316
 317 [system.cpu0.fuPool.FUList5.opList01]
 318 type=OpDesc
 319 eventq_index=0
 320 issueLat=1
 321 opClass=SimdAddAcc
 322 opLat=1
 323
 324 [system.cpu0.fuPool.FUList5.opList02]
 325 type=OpDesc
 326 eventq_index=0
 327 issueLat=1
 328 opClass=SimdAlu
 329 opLat=1
 330
 331 [system.cpu0.fuPool.FUList5.opList03]
 332 type=OpDesc
 333 eventq_index=0
 334 issueLat=1
 335 opClass=SimdCmp
 336 opLat=1
 337
 338 [system.cpu0.fuPool.FUList5.opList04]
 339 type=OpDesc
 340 eventq_index=0
 341 issueLat=1
 342 opClass=SimdCvt
 343 opLat=1
 344
 345 [system.cpu0.fuPool.FUList5.opList05]
 346 type=OpDesc
 347 eventq_index=0
 348 issueLat=1
 349 opClass=SimdMisc
 350 opLat=1
 351
 352 [system.cpu0.fuPool.FUList5.opList06]
 353 type=OpDesc
 354 eventq_index=0
 355 issueLat=1
 356 opClass=SimdMult
 357 opLat=1
 358
 359 [system.cpu0.fuPool.FUList5.opList07]
 360 type=OpDesc
 361 eventq_index=0
 362 issueLat=1
 363 opClass=SimdMultAcc
 364 opLat=1
 365
 366 [system.cpu0.fuPool.FUList5.opList08]
 367 type=OpDesc
 368 eventq_index=0
 369 issueLat=1
 370 opClass=SimdShift
 371 opLat=1
 372
 373 [system.cpu0.fuPool.FUList5.opList09]
 374 type=OpDesc
 375 eventq_index=0
 376 issueLat=1
 377 opClass=SimdShiftAcc
 378 opLat=1
 379
 380 [system.cpu0.fuPool.FUList5.opList10]
 381 type=OpDesc
 382 eventq_index=0
 383 issueLat=1
 384 opClass=SimdSqrt
 385 opLat=1
 386
 387 [system.cpu0.fuPool.FUList5.opList11]
 388 type=OpDesc
 389 eventq_index=0
 390 issueLat=1
 391 opClass=SimdFloatAdd
 392 opLat=1
 393
 394 [system.cpu0.fuPool.FUList5.opList12]
 395 type=OpDesc
 396 eventq_index=0
 397 issueLat=1
 398 opClass=SimdFloatAlu
 399 opLat=1
 400
 401 [system.cpu0.fuPool.FUList5.opList13]
 402 type=OpDesc
 403 eventq_index=0
 404 issueLat=1
 405 opClass=SimdFloatCmp
 406 opLat=1
 407
 408 [system.cpu0.fuPool.FUList5.opList14]
 409 type=OpDesc
 410 eventq_index=0
 411 issueLat=1
 412 opClass=SimdFloatCvt
 413 opLat=1
 414
 415 [system.cpu0.fuPool.FUList5.opList15]
 416 type=OpDesc
 417 eventq_index=0
 418 issueLat=1
 419 opClass=SimdFloatDiv
 420 opLat=1
 421
 422 [system.cpu0.fuPool.FUList5.opList16]
 423 type=OpDesc
 424 eventq_index=0
 425 issueLat=1
 426 opClass=SimdFloatMisc
 427 opLat=1
 428
 429 [system.cpu0.fuPool.FUList5.opList17]
 430 type=OpDesc
 431 eventq_index=0
 432 issueLat=1
 433 opClass=SimdFloatMult
 434 opLat=1
 435
 436 [system.cpu0.fuPool.FUList5.opList18]
 437 type=OpDesc
 438 eventq_index=0
 439 issueLat=1
 440 opClass=SimdFloatMultAcc
 441 opLat=1
 442
 443 [system.cpu0.fuPool.FUList5.opList19]
 444 type=OpDesc
 445 eventq_index=0
 446 issueLat=1
 447 opClass=SimdFloatSqrt
 448 opLat=1
 449
 450 [system.cpu0.fuPool.FUList6]
 451 type=FUDesc
 452 children=opList
 453 count=0
 454 eventq_index=0
 455 opList=system.cpu0.fuPool.FUList6.opList
 456
 457 [system.cpu0.fuPool.FUList6.opList]
 458 type=OpDesc
 459 eventq_index=0
 460 issueLat=1
 461 opClass=MemWrite
 462 opLat=1
 463
 464 [system.cpu0.fuPool.FUList7]
 465 type=FUDesc
 466 children=opList0 opList1
 467 count=4
 468 eventq_index=0
 469 opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1
 470
 471 [system.cpu0.fuPool.FUList7.opList0]
 472 type=OpDesc
 473 eventq_index=0
 474 issueLat=1
 475 opClass=MemRead
 476 opLat=1
 477
 478 [system.cpu0.fuPool.FUList7.opList1]
 479 type=OpDesc
 480 eventq_index=0
 481 issueLat=1
 482 opClass=MemWrite
 483 opLat=1
 484
 485 [system.cpu0.fuPool.FUList8]
 486 type=FUDesc
 487 children=opList
 488 count=1
 489 eventq_index=0
 490 opList=system.cpu0.fuPool.FUList8.opList
 491
 492 [system.cpu0.fuPool.FUList8.opList]
 493 type=OpDesc
 494 eventq_index=0
 495 issueLat=3
 496 opClass=IprAccess
 497 opLat=3
 498
 499 [system.cpu0.icache]
 500 type=BaseCache
 501 children=tags
 502 addr_ranges=0:18446744073709551615
 503 assoc=1
 504 clk_domain=system.cpu_clk_domain
 505 eventq_index=0
 506 forward_snoops=true
 507 hit_latency=2
 508 is_top_level=true
 509 max_miss_count=0
 510 mshrs=4
 511 prefetch_on_access=false
 512 prefetcher=Null
 513 response_latency=2
 514 sequential_access=false
 515 size=32768
 516 system=system
 517 tags=system.cpu0.icache.tags
 518 tgts_per_mshr=20
 519 two_queue=false
 520 write_buffers=8
 521 cpu_side=system.cpu0.icache_port
 522 mem_side=system.toL2Bus.slave[0]
 523
 524 [system.cpu0.icache.tags]
 525 type=LRU
 526 assoc=1
 527 block_size=64
 528 clk_domain=system.cpu_clk_domain
 529 eventq_index=0
 530 hit_latency=2
 531 sequential_access=false
 532 size=32768
 533
 534 [system.cpu0.interrupts]
 535 type=SparcInterrupts
 536 eventq_index=0
 537
 538 [system.cpu0.isa]
 539 type=SparcISA
 540 eventq_index=0
 541
 542 [system.cpu0.itb]
 543 type=SparcTLB
 544 eventq_index=0
 545 size=64
 546
 547 [system.cpu0.tracer]
 548 type=ExeTracer
 549 eventq_index=0
 550
 551 [system.cpu0.workload]
 552 type=LiveProcess
 553 cmd=test_atomic 4
 554 cwd=
 555 egid=100
 556 env=
 557 errout=cerr
 558 euid=100
 559 eventq_index=0
 560 executable=/scratch/nilay/GEM5/gem5/tests/test-progs/m5threads/bin/sparc/linux/test_atomic
 561 gid=100
 562 input=cin
 563 max_stack_size=67108864
 564 output=cout
 565 pid=100
 566 ppid=99
 567 simpoint=0
 568 system=system
 569 uid=100
 570
 571 [system.cpu1]
 572 type=DerivO3CPU
 573 children=branchPred dcache dtb fuPool icache interrupts isa itb tracer
 574 LFSTSize=1024
 575 LQEntries=32
 576 LSQCheckLoads=true
 577 LSQDepCheckShift=4
 578 SQEntries=32
 579 SSITSize=1024
 580 activity=0
 581 backComSize=5
 582 branchPred=system.cpu1.branchPred
 583 cachePorts=200
 584 checker=Null
 585 clk_domain=system.cpu_clk_domain
 586 commitToDecodeDelay=1
 587 commitToFetchDelay=1
 588 commitToIEWDelay=1
 589 commitToRenameDelay=1
 590 commitWidth=8
 591 cpu_id=1
 592 decodeToFetchDelay=1
 593 decodeToRenameDelay=1
 594 decodeWidth=8
 595 dispatchWidth=8
 596 do_checkpoint_insts=true
 597 do_quiesce=true
 598 do_statistics_insts=true
 599 dtb=system.cpu1.dtb
 600 eventq_index=0
 601 fetchBufferSize=64
 602 fetchToDecodeDelay=1
 603 fetchTrapLatency=1
 604 fetchWidth=8
 605 forwardComSize=5
 606 fuPool=system.cpu1.fuPool
 607 function_trace=false
 608 function_trace_start=0
 609 iewToCommitDelay=1
 610 iewToDecodeDelay=1
 611 iewToFetchDelay=1
 612 iewToRenameDelay=1
 613 interrupts=system.cpu1.interrupts
 614 isa=system.cpu1.isa
 615 issueToExecuteDelay=1
 616 issueWidth=8
 617 itb=system.cpu1.itb
 618 max_insts_all_threads=0
 619 max_insts_any_thread=0
 620 max_loads_all_threads=0
 621 max_loads_any_thread=0
 622 needsTSO=false
 623 numIQEntries=64
 624 numPhysCCRegs=0
 625 numPhysFloatRegs=256
 626 numPhysIntRegs=256
 627 numROBEntries=192
 628 numRobs=1
 629 numThreads=1
 630 profile=0
 631 progress_interval=0
 632 renameToDecodeDelay=1
 633 renameToFetchDelay=1
 634 renameToIEWDelay=2
 635 renameToROBDelay=1
 636 renameWidth=8
 637 simpoint_start_insts=
 638 smtCommitPolicy=RoundRobin
 639 smtFetchPolicy=SingleThread
 640 smtIQPolicy=Partitioned
 641 smtIQThreshold=100
 642 smtLSQPolicy=Partitioned
 643 smtLSQThreshold=100
 644 smtNumFetchingThreads=1
 645 smtROBPolicy=Partitioned
 646 smtROBThreshold=100
 647 socket_id=0
 648 squashWidth=8
 649 store_set_clear_period=250000
 650 switched_out=false
 651 system=system
 652 tracer=system.cpu1.tracer
 653 trapLatency=13
 654 wbDepth=1
 655 wbWidth=8
 656 workload=system.cpu0.workload
 657 dcache_port=system.cpu1.dcache.cpu_side
 658 icache_port=system.cpu1.icache.cpu_side
 659
 660 [system.cpu1.branchPred]
 661 type=BranchPredictor
 662 BTBEntries=4096
 663 BTBTagSize=16
 664 RASSize=16
 665 choiceCtrBits=2
 666 choicePredictorSize=8192
 667 eventq_index=0
 668 globalCtrBits=2
 669 globalPredictorSize=8192
 670 instShiftAmt=2
 671 localCtrBits=2
 672 localHistoryTableSize=2048
 673 localPredictorSize=2048
 674 numThreads=1
 675 predType=tournament
 676
 677 [system.cpu1.dcache]
 678 type=BaseCache
 679 children=tags
 680 addr_ranges=0:18446744073709551615
 681 assoc=4
 682 clk_domain=system.cpu_clk_domain
 683 eventq_index=0
 684 forward_snoops=true
 685 hit_latency=2
 686 is_top_level=true
 687 max_miss_count=0
 688 mshrs=4
 689 prefetch_on_access=false
 690 prefetcher=Null
 691 response_latency=2
 692 sequential_access=false
 693 size=32768
 694 system=system
 695 tags=system.cpu1.dcache.tags
 696 tgts_per_mshr=20
 697 two_queue=false
 698 write_buffers=8
 699 cpu_side=system.cpu1.dcache_port
 700 mem_side=system.toL2Bus.slave[3]
 701
 702 [system.cpu1.dcache.tags]
 703 type=LRU
 704 assoc=4
 705 block_size=64
 706 clk_domain=system.cpu_clk_domain
 707 eventq_index=0
 708 hit_latency=2
 709 sequential_access=false
 710 size=32768
 711
 712 [system.cpu1.dtb]
 713 type=SparcTLB
 714 eventq_index=0
 715 size=64
 716
 717 [system.cpu1.fuPool]
 718 type=FUPool
 719 children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
 720 FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 system.cpu1.fuPool.FUList5 system.cpu1.fuPool.FUList6 system.cpu1.fuPool.FUList7 system.cpu1.fuPool.FUList8
 721 eventq_index=0
 722
 723 [system.cpu1.fuPool.FUList0]
 724 type=FUDesc
 725 children=opList
 726 count=6
 727 eventq_index=0
 728 opList=system.cpu1.fuPool.FUList0.opList
 729
 730 [system.cpu1.fuPool.FUList0.opList]
 731 type=OpDesc
 732 eventq_index=0
 733 issueLat=1
 734 opClass=IntAlu
 735 opLat=1
 736
 737 [system.cpu1.fuPool.FUList1]
 738 type=FUDesc
 739 children=opList0 opList1
 740 count=2
 741 eventq_index=0
 742 opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1
 743
 744 [system.cpu1.fuPool.FUList1.opList0]
 745 type=OpDesc
 746 eventq_index=0
 747 issueLat=1
 748 opClass=IntMult
 749 opLat=3
 750
 751 [system.cpu1.fuPool.FUList1.opList1]
 752 type=OpDesc
 753 eventq_index=0
 754 issueLat=19
 755 opClass=IntDiv
 756 opLat=20
 757
 758 [system.cpu1.fuPool.FUList2]
 759 type=FUDesc
 760 children=opList0 opList1 opList2
 761 count=4
 762 eventq_index=0
 763 opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1 system.cpu1.fuPool.FUList2.opList2
 764
 765 [system.cpu1.fuPool.FUList2.opList0]
 766 type=OpDesc
 767 eventq_index=0
 768 issueLat=1
 769 opClass=FloatAdd
 770 opLat=2
 771
 772 [system.cpu1.fuPool.FUList2.opList1]
 773 type=OpDesc
 774 eventq_index=0
 775 issueLat=1
 776 opClass=FloatCmp
 777 opLat=2
 778
 779 [system.cpu1.fuPool.FUList2.opList2]
 780 type=OpDesc
 781 eventq_index=0
 782 issueLat=1
 783 opClass=FloatCvt
 784 opLat=2
 785
 786 [system.cpu1.fuPool.FUList3]
 787 type=FUDesc
 788 children=opList0 opList1 opList2
 789 count=2
 790 eventq_index=0
 791 opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2
 792
 793 [system.cpu1.fuPool.FUList3.opList0]
 794 type=OpDesc
 795 eventq_index=0
 796 issueLat=1
 797 opClass=FloatMult
 798 opLat=4
 799
 800 [system.cpu1.fuPool.FUList3.opList1]
 801 type=OpDesc
 802 eventq_index=0
 803 issueLat=12
 804 opClass=FloatDiv
 805 opLat=12
 806
 807 [system.cpu1.fuPool.FUList3.opList2]
 808 type=OpDesc
 809 eventq_index=0
 810 issueLat=24
 811 opClass=FloatSqrt
 812 opLat=24
 813
 814 [system.cpu1.fuPool.FUList4]
 815 type=FUDesc
 816 children=opList
 817 count=0
 818 eventq_index=0
 819 opList=system.cpu1.fuPool.FUList4.opList
 820
 821 [system.cpu1.fuPool.FUList4.opList]
 822 type=OpDesc
 823 eventq_index=0
 824 issueLat=1
 825 opClass=MemRead
 826 opLat=1
 827
 828 [system.cpu1.fuPool.FUList5]
 829 type=FUDesc
 830 children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
 831 count=4
 832 eventq_index=0
 833 opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 system.cpu1.fuPool.FUList5.opList02 system.cpu1.fuPool.FUList5.opList03 system.cpu1.fuPool.FUList5.opList04 system.cpu1.fuPool.FUList5.opList05 system.cpu1.fuPool.FUList5.opList06 system.cpu1.fuPool.FUList5.opList07 system.cpu1.fuPool.FUList5.opList08 system.cpu1.fuPool.FUList5.opList09 system.cpu1.fuPool.FUList5.opList10 system.cpu1.fuPool.FUList5.opList11 system.cpu1.fuPool.FUList5.opList12 system.cpu1.fuPool.FUList5.opList13 system.cpu1.fuPool.FUList5.opList14 system.cpu1.fuPool.FUList5.opList15 system.cpu1.fuPool.FUList5.opList16 system.cpu1.fuPool.FUList5.opList17 system.cpu1.fuPool.FUList5.opList18 system.cpu1.fuPool.FUList5.opList19
 834
 835 [system.cpu1.fuPool.FUList5.opList00]
 836 type=OpDesc
 837 eventq_index=0
 838 issueLat=1
 839 opClass=SimdAdd
 840 opLat=1
 841
 842 [system.cpu1.fuPool.FUList5.opList01]
 843 type=OpDesc
 844 eventq_index=0
 845 issueLat=1
 846 opClass=SimdAddAcc
 847 opLat=1
 848
 849 [system.cpu1.fuPool.FUList5.opList02]
 850 type=OpDesc
 851 eventq_index=0
 852 issueLat=1
 853 opClass=SimdAlu
 854 opLat=1
 855
 856 [system.cpu1.fuPool.FUList5.opList03]
 857 type=OpDesc
 858 eventq_index=0
 859 issueLat=1
 860 opClass=SimdCmp
 861 opLat=1
 862
 863 [system.cpu1.fuPool.FUList5.opList04]
 864 type=OpDesc
 865 eventq_index=0
 866 issueLat=1
 867 opClass=SimdCvt
 868 opLat=1
 869
 870 [system.cpu1.fuPool.FUList5.opList05]
 871 type=OpDesc
 872 eventq_index=0
 873 issueLat=1
 874 opClass=SimdMisc
 875 opLat=1
 876
 877 [system.cpu1.fuPool.FUList5.opList06]
 878 type=OpDesc
 879 eventq_index=0
 880 issueLat=1
 881 opClass=SimdMult
 882 opLat=1
 883
 884 [system.cpu1.fuPool.FUList5.opList07]
 885 type=OpDesc
 886 eventq_index=0
 887 issueLat=1
 888 opClass=SimdMultAcc
 889 opLat=1
 890
 891 [system.cpu1.fuPool.FUList5.opList08]
 892 type=OpDesc
 893 eventq_index=0
 894 issueLat=1
 895 opClass=SimdShift
 896 opLat=1
 897
 898 [system.cpu1.fuPool.FUList5.opList09]
 899 type=OpDesc
 900 eventq_index=0
 901 issueLat=1
 902 opClass=SimdShiftAcc
 903 opLat=1
 904
 905 [system.cpu1.fuPool.FUList5.opList10]
 906 type=OpDesc
 907 eventq_index=0
 908 issueLat=1
 909 opClass=SimdSqrt
 910 opLat=1
 911
 912 [system.cpu1.fuPool.FUList5.opList11]
 913 type=OpDesc
 914 eventq_index=0
 915 issueLat=1
 916 opClass=SimdFloatAdd
 917 opLat=1
 918
 919 [system.cpu1.fuPool.FUList5.opList12]
 920 type=OpDesc
 921 eventq_index=0
 922 issueLat=1
 923 opClass=SimdFloatAlu
 924 opLat=1
 925
 926 [system.cpu1.fuPool.FUList5.opList13]
 927 type=OpDesc
 928 eventq_index=0
 929 issueLat=1
 930 opClass=SimdFloatCmp
 931 opLat=1
 932
 933 [system.cpu1.fuPool.FUList5.opList14]
 934 type=OpDesc
 935 eventq_index=0
 936 issueLat=1
 937 opClass=SimdFloatCvt
 938 opLat=1
 939
 940 [system.cpu1.fuPool.FUList5.opList15]
 941 type=OpDesc
 942 eventq_index=0
 943 issueLat=1
 944 opClass=SimdFloatDiv
 945 opLat=1
 946
 947 [system.cpu1.fuPool.FUList5.opList16]
 948 type=OpDesc
 949 eventq_index=0
 950 issueLat=1
 951 opClass=SimdFloatMisc
 952 opLat=1
 953
 954 [system.cpu1.fuPool.FUList5.opList17]
 955 type=OpDesc
 956 eventq_index=0
 957 issueLat=1
 958 opClass=SimdFloatMult
 959 opLat=1
 960
 961 [system.cpu1.fuPool.FUList5.opList18]
 962 type=OpDesc
 963 eventq_index=0
 964 issueLat=1
 965 opClass=SimdFloatMultAcc
 966 opLat=1
 967
 968 [system.cpu1.fuPool.FUList5.opList19]
 969 type=OpDesc
 970 eventq_index=0
 971 issueLat=1
 972 opClass=SimdFloatSqrt
 973 opLat=1
 974
 975 [system.cpu1.fuPool.FUList6]
 976 type=FUDesc
 977 children=opList
 978 count=0
 979 eventq_index=0
 980 opList=system.cpu1.fuPool.FUList6.opList
 981
 982 [system.cpu1.fuPool.FUList6.opList]
 983 type=OpDesc
 984 eventq_index=0
 985 issueLat=1
 986 opClass=MemWrite
 987 opLat=1
 988
 989 [system.cpu1.fuPool.FUList7]
 990 type=FUDesc
 991 children=opList0 opList1
 992 count=4
 993 eventq_index=0
 994 opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1
 995
 996 [system.cpu1.fuPool.FUList7.opList0]
 997 type=OpDesc
 998 eventq_index=0
 999 issueLat=1
1000 opClass=MemRead
1001 opLat=1
1002
1003 [system.cpu1.fuPool.FUList7.opList1]
1004 type=OpDesc
1005 eventq_index=0
1006 issueLat=1
1007 opClass=MemWrite
1008 opLat=1
1009
1010 [system.cpu1.fuPool.FUList8]
1011 type=FUDesc
1012 children=opList
1013 count=1
1014 eventq_index=0
1015 opList=system.cpu1.fuPool.FUList8.opList
1016
1017 [system.cpu1.fuPool.FUList8.opList]
1018 type=OpDesc
1019 eventq_index=0
1020 issueLat=3
1021 opClass=IprAccess
1022 opLat=3
1023
1024 [system.cpu1.icache]
1025 type=BaseCache
1026 children=tags
1027 addr_ranges=0:18446744073709551615
1028 assoc=1
1029 clk_domain=system.cpu_clk_domain
1030 eventq_index=0
1031 forward_snoops=true
1032 hit_latency=2
1033 is_top_level=true
1034 max_miss_count=0
1035 mshrs=4
1036 prefetch_on_access=false
1037 prefetcher=Null
1038 response_latency=2
1039 sequential_access=false
1040 size=32768
1041 system=system
1042 tags=system.cpu1.icache.tags
1043 tgts_per_mshr=20
1044 two_queue=false
1045 write_buffers=8
1046 cpu_side=system.cpu1.icache_port
1047 mem_side=system.toL2Bus.slave[2]
1048
1049 [system.cpu1.icache.tags]
1050 type=LRU
1051 assoc=1
1052 block_size=64
1053 clk_domain=system.cpu_clk_domain
1054 eventq_index=0
1055 hit_latency=2
1056 sequential_access=false
1057 size=32768
1058
1059 [system.cpu1.interrupts]
1060 type=SparcInterrupts
1061 eventq_index=0
1062
1063 [system.cpu1.isa]
1064 type=SparcISA
1065 eventq_index=0
1066
1067 [system.cpu1.itb]
1068 type=SparcTLB
1069 eventq_index=0
1070 size=64
1071
1072 [system.cpu1.tracer]
1073 type=ExeTracer
1074 eventq_index=0
1075
1076 [system.cpu2]
1077 type=DerivO3CPU
1078 children=branchPred dcache dtb fuPool icache interrupts isa itb tracer
1079 LFSTSize=1024
1080 LQEntries=32
1081 LSQCheckLoads=true
1082 LSQDepCheckShift=4
1083 SQEntries=32
1084 SSITSize=1024
1085 activity=0
1086 backComSize=5
1087 branchPred=system.cpu2.branchPred
1088 cachePorts=200
1089 checker=Null
1090 clk_domain=system.cpu_clk_domain
1091 commitToDecodeDelay=1
1092 commitToFetchDelay=1
1093 commitToIEWDelay=1
1094 commitToRenameDelay=1
1095 commitWidth=8
1096 cpu_id=2
1097 decodeToFetchDelay=1
1098 decodeToRenameDelay=1
1099 decodeWidth=8
1100 dispatchWidth=8
1101 do_checkpoint_insts=true
1102 do_quiesce=true
1103 do_statistics_insts=true
1104 dtb=system.cpu2.dtb
1105 eventq_index=0
1106 fetchBufferSize=64
1107 fetchToDecodeDelay=1
1108 fetchTrapLatency=1
1109 fetchWidth=8
1110 forwardComSize=5
1111 fuPool=system.cpu2.fuPool
1112 function_trace=false
1113 function_trace_start=0
1114 iewToCommitDelay=1
1115 iewToDecodeDelay=1
1116 iewToFetchDelay=1
1117 iewToRenameDelay=1
1118 interrupts=system.cpu2.interrupts
1119 isa=system.cpu2.isa
1120 issueToExecuteDelay=1
1121 issueWidth=8
1122 itb=system.cpu2.itb
1123 max_insts_all_threads=0
1124 max_insts_any_thread=0
1125 max_loads_all_threads=0
1126 max_loads_any_thread=0
1127 needsTSO=false
1128 numIQEntries=64
1129 numPhysCCRegs=0
1130 numPhysFloatRegs=256
1131 numPhysIntRegs=256
1132 numROBEntries=192
1133 numRobs=1
1134 numThreads=1
1135 profile=0
1136 progress_interval=0
1137 renameToDecodeDelay=1
1138 renameToFetchDelay=1
1139 renameToIEWDelay=2
1140 renameToROBDelay=1
1141 renameWidth=8
1142 simpoint_start_insts=
1143 smtCommitPolicy=RoundRobin
1144 smtFetchPolicy=SingleThread
1145 smtIQPolicy=Partitioned
1146 smtIQThreshold=100
1147 smtLSQPolicy=Partitioned
1148 smtLSQThreshold=100
1149 smtNumFetchingThreads=1
1150 smtROBPolicy=Partitioned
1151 smtROBThreshold=100
1152 socket_id=0
1153 squashWidth=8
1154 store_set_clear_period=250000
1155 switched_out=false
1156 system=system
1157 tracer=system.cpu2.tracer
1158 trapLatency=13
1159 wbDepth=1
1160 wbWidth=8
1161 workload=system.cpu0.workload
1162 dcache_port=system.cpu2.dcache.cpu_side
1163 icache_port=system.cpu2.icache.cpu_side
1164
1165 [system.cpu2.branchPred]
1166 type=BranchPredictor
1167 BTBEntries=4096
1168 BTBTagSize=16
1169 RASSize=16
1170 choiceCtrBits=2
1171 choicePredictorSize=8192
1172 eventq_index=0
1173 globalCtrBits=2
1174 globalPredictorSize=8192
1175 instShiftAmt=2
1176 localCtrBits=2
1177 localHistoryTableSize=2048
1178 localPredictorSize=2048
1179 numThreads=1
1180 predType=tournament
1181
1182 [system.cpu2.dcache]
1183 type=BaseCache
1184 children=tags
1185 addr_ranges=0:18446744073709551615
1186 assoc=4
1187 clk_domain=system.cpu_clk_domain
1188 eventq_index=0
1189 forward_snoops=true
1190 hit_latency=2
1191 is_top_level=true
1192 max_miss_count=0
1193 mshrs=4
1194 prefetch_on_access=false
1195 prefetcher=Null
1196 response_latency=2
1197 sequential_access=false
1198 size=32768
1199 system=system
1200 tags=system.cpu2.dcache.tags
1201 tgts_per_mshr=20
1202 two_queue=false
1203 write_buffers=8
1204 cpu_side=system.cpu2.dcache_port
1205 mem_side=system.toL2Bus.slave[5]
1206
1207 [system.cpu2.dcache.tags]
1208 type=LRU
1209 assoc=4
1210 block_size=64
1211 clk_domain=system.cpu_clk_domain
1212 eventq_index=0
1213 hit_latency=2
1214 sequential_access=false
1215 size=32768
1216
1217 [system.cpu2.dtb]
1218 type=SparcTLB
1219 eventq_index=0
1220 size=64
1221
1222 [system.cpu2.fuPool]
1223 type=FUPool
1224 children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
1225 FUList=system.cpu2.fuPool.FUList0 system.cpu2.fuPool.FUList1 system.cpu2.fuPool.FUList2 system.cpu2.fuPool.FUList3 system.cpu2.fuPool.FUList4 system.cpu2.fuPool.FUList5 system.cpu2.fuPool.FUList6 system.cpu2.fuPool.FUList7 system.cpu2.fuPool.FUList8
1226 eventq_index=0
1227
1228 [system.cpu2.fuPool.FUList0]
1229 type=FUDesc
1230 children=opList
1231 count=6
1232 eventq_index=0
1233 opList=system.cpu2.fuPool.FUList0.opList
1234
1235 [system.cpu2.fuPool.FUList0.opList]
1236 type=OpDesc
1237 eventq_index=0
1238 issueLat=1
1239 opClass=IntAlu
1240 opLat=1
1241
1242 [system.cpu2.fuPool.FUList1]
1243 type=FUDesc
1244 children=opList0 opList1
1245 count=2
1246 eventq_index=0
1247 opList=system.cpu2.fuPool.FUList1.opList0 system.cpu2.fuPool.FUList1.opList1
1248
1249 [system.cpu2.fuPool.FUList1.opList0]
1250 type=OpDesc
1251 eventq_index=0
1252 issueLat=1
1253 opClass=IntMult
1254 opLat=3
1255
1256 [system.cpu2.fuPool.FUList1.opList1]
1257 type=OpDesc
1258 eventq_index=0
1259 issueLat=19
1260 opClass=IntDiv
1261 opLat=20
1262
1263 [system.cpu2.fuPool.FUList2]
1264 type=FUDesc
1265 children=opList0 opList1 opList2
1266 count=4
1267 eventq_index=0
1268 opList=system.cpu2.fuPool.FUList2.opList0 system.cpu2.fuPool.FUList2.opList1 system.cpu2.fuPool.FUList2.opList2
1269
1270 [system.cpu2.fuPool.FUList2.opList0]
1271 type=OpDesc
1272 eventq_index=0
1273 issueLat=1
1274 opClass=FloatAdd
1275 opLat=2
1276
1277 [system.cpu2.fuPool.FUList2.opList1]
1278 type=OpDesc
1279 eventq_index=0
1280 issueLat=1
1281 opClass=FloatCmp
1282 opLat=2
1283
1284 [system.cpu2.fuPool.FUList2.opList2]
1285 type=OpDesc
1286 eventq_index=0
1287 issueLat=1
1288 opClass=FloatCvt
1289 opLat=2
1290
1291 [system.cpu2.fuPool.FUList3]
1292 type=FUDesc
1293 children=opList0 opList1 opList2
1294 count=2
1295 eventq_index=0
1296 opList=system.cpu2.fuPool.FUList3.opList0 system.cpu2.fuPool.FUList3.opList1 system.cpu2.fuPool.FUList3.opList2
1297
1298 [system.cpu2.fuPool.FUList3.opList0]
1299 type=OpDesc
1300 eventq_index=0
1301 issueLat=1
1302 opClass=FloatMult
1303 opLat=4
1304
1305 [system.cpu2.fuPool.FUList3.opList1]
1306 type=OpDesc
1307 eventq_index=0
1308 issueLat=12
1309 opClass=FloatDiv
1310 opLat=12
1311
1312 [system.cpu2.fuPool.FUList3.opList2]
1313 type=OpDesc
1314 eventq_index=0
1315 issueLat=24
1316 opClass=FloatSqrt
1317 opLat=24
1318
1319 [system.cpu2.fuPool.FUList4]
1320 type=FUDesc
1321 children=opList
1322 count=0
1323 eventq_index=0
1324 opList=system.cpu2.fuPool.FUList4.opList
1325
1326 [system.cpu2.fuPool.FUList4.opList]
1327 type=OpDesc
1328 eventq_index=0
1329 issueLat=1
1330 opClass=MemRead
1331 opLat=1
1332
1333 [system.cpu2.fuPool.FUList5]
1334 type=FUDesc
1335 children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
1336 count=4
1337 eventq_index=0
1338 opList=system.cpu2.fuPool.FUList5.opList00 system.cpu2.fuPool.FUList5.opList01 system.cpu2.fuPool.FUList5.opList02 system.cpu2.fuPool.FUList5.opList03 system.cpu2.fuPool.FUList5.opList04 system.cpu2.fuPool.FUList5.opList05 system.cpu2.fuPool.FUList5.opList06 system.cpu2.fuPool.FUList5.opList07 system.cpu2.fuPool.FUList5.opList08 system.cpu2.fuPool.FUList5.opList09 system.cpu2.fuPool.FUList5.opList10 system.cpu2.fuPool.FUList5.opList11 system.cpu2.fuPool.FUList5.opList12 system.cpu2.fuPool.FUList5.opList13 system.cpu2.fuPool.FUList5.opList14 system.cpu2.fuPool.FUList5.opList15 system.cpu2.fuPool.FUList5.opList16 system.cpu2.fuPool.FUList5.opList17 system.cpu2.fuPool.FUList5.opList18 system.cpu2.fuPool.FUList5.opList19
1339
1340 [system.cpu2.fuPool.FUList5.opList00]
1341 type=OpDesc
1342 eventq_index=0
1343 issueLat=1
1344 opClass=SimdAdd
1345 opLat=1
1346
1347 [system.cpu2.fuPool.FUList5.opList01]
1348 type=OpDesc
1349 eventq_index=0
1350 issueLat=1
1351 opClass=SimdAddAcc
1352 opLat=1
1353
1354 [system.cpu2.fuPool.FUList5.opList02]
1355 type=OpDesc
1356 eventq_index=0
1357 issueLat=1
1358 opClass=SimdAlu
1359 opLat=1
1360
1361 [system.cpu2.fuPool.FUList5.opList03]
1362 type=OpDesc
1363 eventq_index=0
1364 issueLat=1
1365 opClass=SimdCmp
1366 opLat=1
1367
1368 [system.cpu2.fuPool.FUList5.opList04]
1369 type=OpDesc
1370 eventq_index=0
1371 issueLat=1
1372 opClass=SimdCvt
1373 opLat=1
1374
1375 [system.cpu2.fuPool.FUList5.opList05]
1376 type=OpDesc
1377 eventq_index=0
1378 issueLat=1
1379 opClass=SimdMisc
1380 opLat=1
1381
1382 [system.cpu2.fuPool.FUList5.opList06]
1383 type=OpDesc
1384 eventq_index=0
1385 issueLat=1
1386 opClass=SimdMult
1387 opLat=1
1388
1389 [system.cpu2.fuPool.FUList5.opList07]
1390 type=OpDesc
1391 eventq_index=0
1392 issueLat=1
1393 opClass=SimdMultAcc
1394 opLat=1
1395
1396 [system.cpu2.fuPool.FUList5.opList08]
1397 type=OpDesc
1398 eventq_index=0
1399 issueLat=1
1400 opClass=SimdShift
1401 opLat=1
1402
1403 [system.cpu2.fuPool.FUList5.opList09]
1404 type=OpDesc
1405 eventq_index=0
1406 issueLat=1
1407 opClass=SimdShiftAcc
1408 opLat=1
1409
1410 [system.cpu2.fuPool.FUList5.opList10]
1411 type=OpDesc
1412 eventq_index=0
1413 issueLat=1
1414 opClass=SimdSqrt
1415 opLat=1
1416
1417 [system.cpu2.fuPool.FUList5.opList11]
1418 type=OpDesc
1419 eventq_index=0
1420 issueLat=1
1421 opClass=SimdFloatAdd
1422 opLat=1
1423
1424 [system.cpu2.fuPool.FUList5.opList12]
1425 type=OpDesc
1426 eventq_index=0
1427 issueLat=1
1428 opClass=SimdFloatAlu
1429 opLat=1
1430
1431 [system.cpu2.fuPool.FUList5.opList13]
1432 type=OpDesc
1433 eventq_index=0
1434 issueLat=1
1435 opClass=SimdFloatCmp
1436 opLat=1
1437
1438 [system.cpu2.fuPool.FUList5.opList14]
1439 type=OpDesc
1440 eventq_index=0
1441 issueLat=1
1442 opClass=SimdFloatCvt
1443 opLat=1
1444
1445 [system.cpu2.fuPool.FUList5.opList15]
1446 type=OpDesc
1447 eventq_index=0
1448 issueLat=1
1449 opClass=SimdFloatDiv
1450 opLat=1
1451
1452 [system.cpu2.fuPool.FUList5.opList16]
1453 type=OpDesc
1454 eventq_index=0
1455 issueLat=1
1456 opClass=SimdFloatMisc
1457 opLat=1
1458
1459 [system.cpu2.fuPool.FUList5.opList17]
1460 type=OpDesc
1461 eventq_index=0
1462 issueLat=1
1463 opClass=SimdFloatMult
1464 opLat=1
1465
1466 [system.cpu2.fuPool.FUList5.opList18]
1467 type=OpDesc
1468 eventq_index=0
1469 issueLat=1
1470 opClass=SimdFloatMultAcc
1471 opLat=1
1472
1473 [system.cpu2.fuPool.FUList5.opList19]
1474 type=OpDesc
1475 eventq_index=0
1476 issueLat=1
1477 opClass=SimdFloatSqrt
1478 opLat=1
1479
1480 [system.cpu2.fuPool.FUList6]
1481 type=FUDesc
1482 children=opList
1483 count=0
1484 eventq_index=0
1485 opList=system.cpu2.fuPool.FUList6.opList
1486
1487 [system.cpu2.fuPool.FUList6.opList]
1488 type=OpDesc
1489 eventq_index=0
1490 issueLat=1
1491 opClass=MemWrite
1492 opLat=1
1493
1494 [system.cpu2.fuPool.FUList7]
1495 type=FUDesc
1496 children=opList0 opList1
1497 count=4
1498 eventq_index=0
1499 opList=system.cpu2.fuPool.FUList7.opList0 system.cpu2.fuPool.FUList7.opList1
1500
1501 [system.cpu2.fuPool.FUList7.opList0]
1502 type=OpDesc
1503 eventq_index=0
1504 issueLat=1
1505 opClass=MemRead
1506 opLat=1
1507
1508 [system.cpu2.fuPool.FUList7.opList1]
1509 type=OpDesc
1510 eventq_index=0
1511 issueLat=1
1512 opClass=MemWrite
1513 opLat=1
1514
1515 [system.cpu2.fuPool.FUList8]
1516 type=FUDesc
1517 children=opList
1518 count=1
1519 eventq_index=0
1520 opList=system.cpu2.fuPool.FUList8.opList
1521
1522 [system.cpu2.fuPool.FUList8.opList]
1523 type=OpDesc
1524 eventq_index=0
1525 issueLat=3
1526 opClass=IprAccess
1527 opLat=3
1528
1529 [system.cpu2.icache]
1530 type=BaseCache
1531 children=tags
1532 addr_ranges=0:18446744073709551615
1533 assoc=1
1534 clk_domain=system.cpu_clk_domain
1535 eventq_index=0
1536 forward_snoops=true
1537 hit_latency=2
1538 is_top_level=true
1539 max_miss_count=0
1540 mshrs=4
1541 prefetch_on_access=false
1542 prefetcher=Null
1543 response_latency=2
1544 sequential_access=false
1545 size=32768
1546 system=system
1547 tags=system.cpu2.icache.tags
1548 tgts_per_mshr=20
1549 two_queue=false
1550 write_buffers=8
1551 cpu_side=system.cpu2.icache_port
1552 mem_side=system.toL2Bus.slave[4]
1553
1554 [system.cpu2.icache.tags]
1555 type=LRU
1556 assoc=1
1557 block_size=64
1558 clk_domain=system.cpu_clk_domain
1559 eventq_index=0
1560 hit_latency=2
1561 sequential_access=false
1562 size=32768
1563
1564 [system.cpu2.interrupts]
1565 type=SparcInterrupts
1566 eventq_index=0
1567
1568 [system.cpu2.isa]
1569 type=SparcISA
1570 eventq_index=0
1571
1572 [system.cpu2.itb]
1573 type=SparcTLB
1574 eventq_index=0
1575 size=64
1576
1577 [system.cpu2.tracer]
1578 type=ExeTracer
1579 eventq_index=0
1580
1581 [system.cpu3]
1582 type=DerivO3CPU
1583 children=branchPred dcache dtb fuPool icache interrupts isa itb tracer
1584 LFSTSize=1024
1585 LQEntries=32
1586 LSQCheckLoads=true
1587 LSQDepCheckShift=4
1588 SQEntries=32
1589 SSITSize=1024
1590 activity=0
1591 backComSize=5
1592 branchPred=system.cpu3.branchPred
1593 cachePorts=200
1594 checker=Null
1595 clk_domain=system.cpu_clk_domain
1596 commitToDecodeDelay=1
1597 commitToFetchDelay=1
1598 commitToIEWDelay=1
1599 commitToRenameDelay=1
1600 commitWidth=8
1601 cpu_id=3
1602 decodeToFetchDelay=1
1603 decodeToRenameDelay=1
1604 decodeWidth=8
1605 dispatchWidth=8
1606 do_checkpoint_insts=true
1607 do_quiesce=true
1608 do_statistics_insts=true
1609 dtb=system.cpu3.dtb
1610 eventq_index=0
1611 fetchBufferSize=64
1612 fetchToDecodeDelay=1
1613 fetchTrapLatency=1
1614 fetchWidth=8
1615 forwardComSize=5
1616 fuPool=system.cpu3.fuPool
1617 function_trace=false
1618 function_trace_start=0
1619 iewToCommitDelay=1
1620 iewToDecodeDelay=1
1621 iewToFetchDelay=1
1622 iewToRenameDelay=1
1623 interrupts=system.cpu3.interrupts
1624 isa=system.cpu3.isa
1625 issueToExecuteDelay=1
1626 issueWidth=8
1627 itb=system.cpu3.itb
1628 max_insts_all_threads=0
1629 max_insts_any_thread=0
1630 max_loads_all_threads=0
1631 max_loads_any_thread=0
1632 needsTSO=false
1633 numIQEntries=64
1634 numPhysCCRegs=0
1635 numPhysFloatRegs=256
1636 numPhysIntRegs=256
1637 numROBEntries=192
1638 numRobs=1
1639 numThreads=1
1640 profile=0
1641 progress_interval=0
1642 renameToDecodeDelay=1
1643 renameToFetchDelay=1
1644 renameToIEWDelay=2
1645 renameToROBDelay=1
1646 renameWidth=8
1647 simpoint_start_insts=
1648 smtCommitPolicy=RoundRobin
1649 smtFetchPolicy=SingleThread
1650 smtIQPolicy=Partitioned
1651 smtIQThreshold=100
1652 smtLSQPolicy=Partitioned
1653 smtLSQThreshold=100
1654 smtNumFetchingThreads=1
1655 smtROBPolicy=Partitioned
1656 smtROBThreshold=100
1657 socket_id=0
1658 squashWidth=8
1659 store_set_clear_period=250000
1660 switched_out=false
1661 system=system
1662 tracer=system.cpu3.tracer
1663 trapLatency=13
1664 wbDepth=1
1665 wbWidth=8
1666 workload=system.cpu0.workload
1667 dcache_port=system.cpu3.dcache.cpu_side
1668 icache_port=system.cpu3.icache.cpu_side
1669
1670 [system.cpu3.branchPred]
1671 type=BranchPredictor
1672 BTBEntries=4096
1673 BTBTagSize=16
1674 RASSize=16
1675 choiceCtrBits=2
1676 choicePredictorSize=8192
1677 eventq_index=0
1678 globalCtrBits=2
1679 globalPredictorSize=8192
1680 instShiftAmt=2
1681 localCtrBits=2
1682 localHistoryTableSize=2048
1683 localPredictorSize=2048
1684 numThreads=1
1685 predType=tournament
1686
1687 [system.cpu3.dcache]
1688 type=BaseCache
1689 children=tags
1690 addr_ranges=0:18446744073709551615
1691 assoc=4
1692 clk_domain=system.cpu_clk_domain
1693 eventq_index=0
1694 forward_snoops=true
1695 hit_latency=2
1696 is_top_level=true
1697 max_miss_count=0
1698 mshrs=4
1699 prefetch_on_access=false
1700 prefetcher=Null
1701 response_latency=2
1702 sequential_access=false
1703 size=32768
1704 system=system
1705 tags=system.cpu3.dcache.tags
1706 tgts_per_mshr=20
1707 two_queue=false
1708 write_buffers=8
1709 cpu_side=system.cpu3.dcache_port
1710 mem_side=system.toL2Bus.slave[7]
1711
1712 [system.cpu3.dcache.tags]
1713 type=LRU
1714 assoc=4
1715 block_size=64
1716 clk_domain=system.cpu_clk_domain
1717 eventq_index=0
1718 hit_latency=2
1719 sequential_access=false
1720 size=32768
1721
1722 [system.cpu3.dtb]
1723 type=SparcTLB
1724 eventq_index=0
1725 size=64
1726
1727 [system.cpu3.fuPool]
1728 type=FUPool
1729 children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
1730 FUList=system.cpu3.fuPool.FUList0 system.cpu3.fuPool.FUList1 system.cpu3.fuPool.FUList2 system.cpu3.fuPool.FUList3 system.cpu3.fuPool.FUList4 system.cpu3.fuPool.FUList5 system.cpu3.fuPool.FUList6 system.cpu3.fuPool.FUList7 system.cpu3.fuPool.FUList8
1731 eventq_index=0
1732
1733 [system.cpu3.fuPool.FUList0]
1734 type=FUDesc
1735 children=opList
1736 count=6
1737 eventq_index=0
1738 opList=system.cpu3.fuPool.FUList0.opList
1739
1740 [system.cpu3.fuPool.FUList0.opList]
1741 type=OpDesc
1742 eventq_index=0
1743 issueLat=1
1744 opClass=IntAlu
1745 opLat=1
1746
1747 [system.cpu3.fuPool.FUList1]
1748 type=FUDesc
1749 children=opList0 opList1
1750 count=2
1751 eventq_index=0
1752 opList=system.cpu3.fuPool.FUList1.opList0 system.cpu3.fuPool.FUList1.opList1
1753
1754 [system.cpu3.fuPool.FUList1.opList0]
1755 type=OpDesc
1756 eventq_index=0
1757 issueLat=1
1758 opClass=IntMult
1759 opLat=3
1760
1761 [system.cpu3.fuPool.FUList1.opList1]
1762 type=OpDesc
1763 eventq_index=0
1764 issueLat=19
1765 opClass=IntDiv
1766 opLat=20
1767
1768 [system.cpu3.fuPool.FUList2]
1769 type=FUDesc
1770 children=opList0 opList1 opList2
1771 count=4
1772 eventq_index=0
1773 opList=system.cpu3.fuPool.FUList2.opList0 system.cpu3.fuPool.FUList2.opList1 system.cpu3.fuPool.FUList2.opList2
1774
1775 [system.cpu3.fuPool.FUList2.opList0]
1776 type=OpDesc
1777 eventq_index=0
1778 issueLat=1
1779 opClass=FloatAdd
1780 opLat=2
1781
1782 [system.cpu3.fuPool.FUList2.opList1]
1783 type=OpDesc
1784 eventq_index=0
1785 issueLat=1
1786 opClass=FloatCmp
1787 opLat=2
1788
1789 [system.cpu3.fuPool.FUList2.opList2]
1790 type=OpDesc
1791 eventq_index=0
1792 issueLat=1
1793 opClass=FloatCvt
1794 opLat=2
1795
1796 [system.cpu3.fuPool.FUList3]
1797 type=FUDesc
1798 children=opList0 opList1 opList2
1799 count=2
1800 eventq_index=0
1801 opList=system.cpu3.fuPool.FUList3.opList0 system.cpu3.fuPool.FUList3.opList1 system.cpu3.fuPool.FUList3.opList2
1802
1803 [system.cpu3.fuPool.FUList3.opList0]
1804 type=OpDesc
1805 eventq_index=0
1806 issueLat=1
1807 opClass=FloatMult
1808 opLat=4
1809
1810 [system.cpu3.fuPool.FUList3.opList1]
1811 type=OpDesc
1812 eventq_index=0
1813 issueLat=12
1814 opClass=FloatDiv
1815 opLat=12
1816
1817 [system.cpu3.fuPool.FUList3.opList2]
1818 type=OpDesc
1819 eventq_index=0
1820 issueLat=24
1821 opClass=FloatSqrt
1822 opLat=24
1823
1824 [system.cpu3.fuPool.FUList4]
1825 type=FUDesc
1826 children=opList
1827 count=0
1828 eventq_index=0
1829 opList=system.cpu3.fuPool.FUList4.opList
1830
1831 [system.cpu3.fuPool.FUList4.opList]
1832 type=OpDesc
1833 eventq_index=0
1834 issueLat=1
1835 opClass=MemRead
1836 opLat=1
1837
1838 [system.cpu3.fuPool.FUList5]
1839 type=FUDesc
1840 children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
1841 count=4
1842 eventq_index=0
1843 opList=system.cpu3.fuPool.FUList5.opList00 system.cpu3.fuPool.FUList5.opList01 system.cpu3.fuPool.FUList5.opList02 system.cpu3.fuPool.FUList5.opList03 system.cpu3.fuPool.FUList5.opList04 system.cpu3.fuPool.FUList5.opList05 system.cpu3.fuPool.FUList5.opList06 system.cpu3.fuPool.FUList5.opList07 system.cpu3.fuPool.FUList5.opList08 system.cpu3.fuPool.FUList5.opList09 system.cpu3.fuPool.FUList5.opList10 system.cpu3.fuPool.FUList5.opList11 system.cpu3.fuPool.FUList5.opList12 system.cpu3.fuPool.FUList5.opList13 system.cpu3.fuPool.FUList5.opList14 system.cpu3.fuPool.FUList5.opList15 system.cpu3.fuPool.FUList5.opList16 system.cpu3.fuPool.FUList5.opList17 system.cpu3.fuPool.FUList5.opList18 system.cpu3.fuPool.FUList5.opList19
1844
1845 [system.cpu3.fuPool.FUList5.opList00]
1846 type=OpDesc
1847 eventq_index=0
1848 issueLat=1
1849 opClass=SimdAdd
1850 opLat=1
1851
1852 [system.cpu3.fuPool.FUList5.opList01]
1853 type=OpDesc
1854 eventq_index=0
1855 issueLat=1
1856 opClass=SimdAddAcc
1857 opLat=1
1858
1859 [system.cpu3.fuPool.FUList5.opList02]
1860 type=OpDesc
1861 eventq_index=0
1862 issueLat=1
1863 opClass=SimdAlu
1864 opLat=1
1865
1866 [system.cpu3.fuPool.FUList5.opList03]
1867 type=OpDesc
1868 eventq_index=0
1869 issueLat=1
1870 opClass=SimdCmp
1871 opLat=1
1872
1873 [system.cpu3.fuPool.FUList5.opList04]
1874 type=OpDesc
1875 eventq_index=0
1876 issueLat=1
1877 opClass=SimdCvt
1878 opLat=1
1879
1880 [system.cpu3.fuPool.FUList5.opList05]
1881 type=OpDesc
1882 eventq_index=0
1883 issueLat=1
1884 opClass=SimdMisc
1885 opLat=1
1886
1887 [system.cpu3.fuPool.FUList5.opList06]
1888 type=OpDesc
1889 eventq_index=0
1890 issueLat=1
1891 opClass=SimdMult
1892 opLat=1
1893
1894 [system.cpu3.fuPool.FUList5.opList07]
1895 type=OpDesc
1896 eventq_index=0
1897 issueLat=1
1898 opClass=SimdMultAcc
1899 opLat=1
1900
1901 [system.cpu3.fuPool.FUList5.opList08]
1902 type=OpDesc
1903 eventq_index=0
1904 issueLat=1
1905 opClass=SimdShift
1906 opLat=1
1907
1908 [system.cpu3.fuPool.FUList5.opList09]
1909 type=OpDesc
1910 eventq_index=0
1911 issueLat=1
1912 opClass=SimdShiftAcc
1913 opLat=1
1914
1915 [system.cpu3.fuPool.FUList5.opList10]
1916 type=OpDesc
1917 eventq_index=0
1918 issueLat=1
1919 opClass=SimdSqrt
1920 opLat=1
1921
1922 [system.cpu3.fuPool.FUList5.opList11]
1923 type=OpDesc
1924 eventq_index=0
1925 issueLat=1
1926 opClass=SimdFloatAdd
1927 opLat=1
1928
1929 [system.cpu3.fuPool.FUList5.opList12]
1930 type=OpDesc
1931 eventq_index=0
1932 issueLat=1
1933 opClass=SimdFloatAlu
1934 opLat=1
1935
1936 [system.cpu3.fuPool.FUList5.opList13]
1937 type=OpDesc
1938 eventq_index=0
1939 issueLat=1
1940 opClass=SimdFloatCmp
1941 opLat=1
1942
1943 [system.cpu3.fuPool.FUList5.opList14]
1944 type=OpDesc
1945 eventq_index=0
1946 issueLat=1
1947 opClass=SimdFloatCvt
1948 opLat=1
1949
1950 [system.cpu3.fuPool.FUList5.opList15]
1951 type=OpDesc
1952 eventq_index=0
1953 issueLat=1
1954 opClass=SimdFloatDiv
1955 opLat=1
1956
1957 [system.cpu3.fuPool.FUList5.opList16]
1958 type=OpDesc
1959 eventq_index=0
1960 issueLat=1
1961 opClass=SimdFloatMisc
1962 opLat=1
1963
1964 [system.cpu3.fuPool.FUList5.opList17]
1965 type=OpDesc
1966 eventq_index=0
1967 issueLat=1
1968 opClass=SimdFloatMult
1969 opLat=1
1970
1971 [system.cpu3.fuPool.FUList5.opList18]
1972 type=OpDesc
1973 eventq_index=0
1974 issueLat=1
1975 opClass=SimdFloatMultAcc
1976 opLat=1
1977
1978 [system.cpu3.fuPool.FUList5.opList19]
1979 type=OpDesc
1980 eventq_index=0
1981 issueLat=1
1982 opClass=SimdFloatSqrt
1983 opLat=1
1984
1985 [system.cpu3.fuPool.FUList6]
1986 type=FUDesc
1987 children=opList
1988 count=0
1989 eventq_index=0
1990 opList=system.cpu3.fuPool.FUList6.opList
1991
1992 [system.cpu3.fuPool.FUList6.opList]
1993 type=OpDesc
1994 eventq_index=0
1995 issueLat=1
1996 opClass=MemWrite
1997 opLat=1
1998
1999 [system.cpu3.fuPool.FUList7]
2000 type=FUDesc
2001 children=opList0 opList1
2002 count=4
2003 eventq_index=0
2004 opList=system.cpu3.fuPool.FUList7.opList0 system.cpu3.fuPool.FUList7.opList1
2005
2006 [system.cpu3.fuPool.FUList7.opList0]
2007 type=OpDesc
2008 eventq_index=0
2009 issueLat=1
2010 opClass=MemRead
2011 opLat=1
2012
2013 [system.cpu3.fuPool.FUList7.opList1]
2014 type=OpDesc
2015 eventq_index=0
2016 issueLat=1
2017 opClass=MemWrite
2018 opLat=1
2019
2020 [system.cpu3.fuPool.FUList8]
2021 type=FUDesc
2022 children=opList
2023 count=1
2024 eventq_index=0
2025 opList=system.cpu3.fuPool.FUList8.opList
2026
2027 [system.cpu3.fuPool.FUList8.opList]
2028 type=OpDesc
2029 eventq_index=0
2030 issueLat=3
2031 opClass=IprAccess
2032 opLat=3
2033
2034 [system.cpu3.icache]
2035 type=BaseCache
2036 children=tags
2037 addr_ranges=0:18446744073709551615
2038 assoc=1
2039 clk_domain=system.cpu_clk_domain
2040 eventq_index=0
2041 forward_snoops=true
2042 hit_latency=2
2043 is_top_level=true
2044 max_miss_count=0
2045 mshrs=4
2046 prefetch_on_access=false
2047 prefetcher=Null
2048 response_latency=2
2049 sequential_access=false
2050 size=32768
2051 system=system
2052 tags=system.cpu3.icache.tags
2053 tgts_per_mshr=20
2054 two_queue=false
2055 write_buffers=8
2056 cpu_side=system.cpu3.icache_port
2057 mem_side=system.toL2Bus.slave[6]
2058
2059 [system.cpu3.icache.tags]
2060 type=LRU
2061 assoc=1
2062 block_size=64
2063 clk_domain=system.cpu_clk_domain
2064 eventq_index=0
2065 hit_latency=2
2066 sequential_access=false
2067 size=32768
2068
2069 [system.cpu3.interrupts]
2070 type=SparcInterrupts
2071 eventq_index=0
2072
2073 [system.cpu3.isa]
2074 type=SparcISA
2075 eventq_index=0
2076
2077 [system.cpu3.itb]
2078 type=SparcTLB
2079 eventq_index=0
2080 size=64
2081
2082 [system.cpu3.tracer]
2083 type=ExeTracer
2084 eventq_index=0
2085
2086 [system.cpu_clk_domain]
2087 type=SrcClockDomain
2088 clock=500
2089 domain_id=-1
2090 eventq_index=0
2091 init_perf_level=0
2092 voltage_domain=system.voltage_domain
2093
2094 [system.dvfs_handler]
2095 type=DVFSHandler
2096 domains=
2097 enable=false
2098 eventq_index=0
2099 sys_clk_domain=system.clk_domain
2100 transition_latency=100000000
2101
2102 [system.l2c]
2103 type=BaseCache
2104 children=tags
2105 addr_ranges=0:18446744073709551615
2106 assoc=8
2107 clk_domain=system.cpu_clk_domain
2108 eventq_index=0
2109 forward_snoops=true
2110 hit_latency=20
2111 is_top_level=false
2112 max_miss_count=0
2113 mshrs=20
2114 prefetch_on_access=false
2115 prefetcher=Null
2116 response_latency=20
2117 sequential_access=false
2118 size=4194304
2119 system=system
2120 tags=system.l2c.tags
2121 tgts_per_mshr=12
2122 two_queue=false
2123 write_buffers=8
2124 cpu_side=system.toL2Bus.master[0]
2125 mem_side=system.membus.slave[1]
2126
2127 [system.l2c.tags]
2128 type=LRU
2129 assoc=8
2130 block_size=64
2131 clk_domain=system.cpu_clk_domain
2132 eventq_index=0
2133 hit_latency=20
2134 sequential_access=false
2135 size=4194304
2136
2137 [system.membus]
2138 type=CoherentBus
2139 clk_domain=system.clk_domain
2140 eventq_index=0
2141 header_cycles=1
2142 system=system
2143 use_default_range=false
2144 width=8
2145 master=system.physmem.port
2146 slave=system.system_port system.l2c.mem_side
2147
2148 [system.physmem]
2149 type=DRAMCtrl
2150 activation_limit=4
2151 addr_mapping=RoRaBaChCo
2152 banks_per_rank=8
2153 burst_length=8
2154 channels=1
2155 clk_domain=system.clk_domain
2156 conf_table_reported=true
2157 device_bus_width=8
2158 device_rowbuffer_size=1024
2159 devices_per_rank=8
2160 eventq_index=0
2161 in_addr_map=true
2162 max_accesses_per_row=16
2163 mem_sched_policy=frfcfs
2164 min_writes_per_switch=16
2165 null=false
2166 page_policy=open_adaptive
2167 range=0:134217727
2168 ranks_per_channel=2
2169 read_buffer_size=32
2170 static_backend_latency=10000
2171 static_frontend_latency=10000
2172 tBURST=5000
2173 tCK=1250
2174 tCL=13750
2175 tRAS=35000
2176 tRCD=13750
2177 tREFI=7800000
2178 tRFC=260000
2179 tRP=13750
2180 tRRD=6000
2181 tRTP=7500
2182 tRTW=2500
2183 tWR=15000
2184 tWTR=7500
2185 tXAW=30000
2186 write_buffer_size=64
2187 write_high_thresh_perc=85
2188 write_low_thresh_perc=50
2189 port=system.membus.master[0]
2190
2191 [system.toL2Bus]
2192 type=CoherentBus
2193 clk_domain=system.cpu_clk_domain
2194 eventq_index=0
2195 header_cycles=1
2196 system=system
2197 use_default_range=false
2198 width=8
2199 master=system.l2c.cpu_side
2200 slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side
2201
2202 [system.voltage_domain]
2203 type=VoltageDomain
2204 eventq_index=0
2205 voltage=1.000000
2206