[gem5.git] / tests / quick / se / 40.m5threads-test-atomic / ref / sparc / linux / o3-timing-mp / stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.000111                       # Number of seconds simulated
sim_ticks                                   111402500                       # Number of ticks simulated
final_tick                                  111402500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 189621                       # Simulator instruction rate (inst/s)
host_op_rate                                   189621                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               19396106                       # Simulator tick rate (ticks/s)
host_mem_usage                                 226052                       # Number of bytes of host memory used
host_seconds                                     5.74                       # Real time elapsed on the host
sim_insts                                     1089093                       # Number of instructions simulated
sim_ops                                       1089093                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read                       43072                       # Number of bytes read from this memory
system.physmem.bytes_inst_read                  29312                       # Number of instructions bytes read from this memory
system.physmem.bytes_written                        0                       # Number of bytes written to this memory
system.physmem.num_reads                          673                       # Number of read requests responded to by this memory
system.physmem.num_writes                           0                       # Number of write requests responded to by this memory
system.physmem.num_other                            0                       # Number of other requests responded to by this memory
system.physmem.bw_read                      386634052                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read                 263117973                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total                     386634052                       # Total bandwidth to/from this memory (bytes/s)
system.cpu0.workload.num_syscalls                  89                       # Number of system calls
system.cpu0.numCycles                          222806                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.BPredUnit.lookups                   87253                       # Number of BP lookups
system.cpu0.BPredUnit.condPredicted             84917                       # Number of conditional branches predicted
system.cpu0.BPredUnit.condIncorrect              1303                       # Number of conditional branches incorrect
system.cpu0.BPredUnit.BTBLookups                84794                       # Number of BTB lookups
system.cpu0.BPredUnit.BTBHits                   82358                       # Number of BTB hits
system.cpu0.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.BPredUnit.usedRAS                     518                       # Number of times the RAS was used to get a target.
system.cpu0.BPredUnit.RASInCorrect                136                       # Number of incorrect RAS predictions.
system.cpu0.fetch.icacheStallCycles             17579                       # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts                        517995                       # Number of instructions fetch has processed
system.cpu0.fetch.Branches                      87253                       # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches             82876                       # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles                       170053                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles                   3992                       # Number of cycles fetch has spent squashing
system.cpu0.fetch.BlockedCycles                 13261                       # Number of cycles fetch has spent blocked
system.cpu0.fetch.MiscStallCycles                   5                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingTrapStallCycles         1318                       # Number of stall cycles due to pending traps
system.cpu0.fetch.CacheLines                     6218                       # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes                  521                       # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.rateDist::samples            204756                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean             2.529816                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev            2.210666                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0                   34703     16.95%     16.95% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1                   84234     41.14%     58.09% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2                     594      0.29%     58.38% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3                     959      0.47%     58.85% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4                     591      0.29%     59.13% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5                   80169     39.15%     98.29% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6                     594      0.29%     98.58% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7                     373      0.18%     98.76% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8                    2539      1.24%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total              204756                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate                 0.391610                       # Number of branch fetches per cycle
system.cpu0.fetch.rate                       2.324870                       # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles                   18003                       # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles                14874                       # Number of cycles decode is blocked
system.cpu0.decode.RunCycles                   169024                       # Number of cycles decode is running
system.cpu0.decode.UnblockCycles                  315                       # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles                  2540                       # Number of cycles decode is squashing
system.cpu0.decode.DecodedInsts                515001                       # Number of instructions handled by decode
system.cpu0.rename.SquashCycles                  2540                       # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles                   18709                       # Number of cycles rename is idle
system.cpu0.rename.BlockCycles                   1371                       # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles         12822                       # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles                   168665                       # Number of cycles rename is running
system.cpu0.rename.UnblockCycles                  649                       # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts                511590                       # Number of instructions processed by rename
system.cpu0.rename.IQFullEvents                     5                       # Number of times rename has blocked due to IQ full
system.cpu0.rename.LSQFullEvents                  235                       # Number of times rename has blocked due to LSQ full
system.cpu0.rename.RenamedOperands             349678                       # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups              1020456                       # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups         1020456                       # Number of integer rename lookups
system.cpu0.rename.CommittedMaps               335896                       # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps                   13782                       # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts               911                       # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts           939                       # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts                     4054                       # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads              163918                       # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores              82754                       # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads            79985                       # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores           79744                       # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded                    427655                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded                948                       # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued                   424795                       # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued              156                       # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined          11264                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined        10234                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved           389                       # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples       204756                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean        2.074640                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev       1.085274                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0              33869     16.54%     16.54% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1               5212      2.55%     19.09% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2              81806     39.95%     59.04% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3              81161     39.64%     98.68% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4               1586      0.77%     99.45% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5                710      0.35%     99.80% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6                306      0.15%     99.95% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7                 90      0.04%     99.99% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8                 16      0.01%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total         204756                       # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu                     53     21.81%     21.81% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult                     0      0.00%     21.81% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv                      0      0.00%     21.81% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     21.81% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     21.81% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     21.81% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult                   0      0.00%     21.81% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     21.81% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     21.81% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     21.81% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     21.81% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     21.81% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     21.81% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     21.81% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     21.81% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult                    0      0.00%     21.81% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     21.81% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift                   0      0.00%     21.81% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     21.81% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     21.81% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     21.81% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     21.81% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     21.81% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     21.81% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     21.81% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     21.81% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     21.81% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     21.81% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     21.81% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead                    78     32.10%     53.91% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite                  112     46.09%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu               179222     42.19%     42.19% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult                   0      0.00%     42.19% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     42.19% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     42.19% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     42.19% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     42.19% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     42.19% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     42.19% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     42.19% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     42.19% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     42.19% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     42.19% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     42.19% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     42.19% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     42.19% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     42.19% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     42.19% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     42.19% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     42.19% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     42.19% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     42.19% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     42.19% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     42.19% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     42.19% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     42.19% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc             0      0.00%     42.19% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     42.19% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     42.19% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     42.19% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead              163383     38.46%     80.65% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite              82190     19.35%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total                424795                       # Type of FU issued
system.cpu0.iq.rate                          1.906569                       # Inst issue rate
system.cpu0.iq.fu_busy_cnt                        243                       # FU busy when requested
system.cpu0.iq.fu_busy_rate                  0.000572                       # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads           1054745                       # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes           439928                       # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses       422836                       # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes                 0                       # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses                425038                       # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads           79492                       # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads         2386                       # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses            3                       # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation           61                       # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores         1482                       # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked           16                       # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles                  2540                       # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles                    996                       # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles                   37                       # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts             509141                       # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts              346                       # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts               163918                       # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts               82754                       # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts               837                       # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents                    38                       # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents            61                       # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect           382                       # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect         1141                       # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts                1523                       # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts               423658                       # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts               163081                       # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts             1137                       # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
system.cpu0.iew.exec_nop                        80538                       # number of nop insts executed
system.cpu0.iew.exec_refs                      245123                       # number of memory reference insts executed
system.cpu0.iew.exec_branches                   84187                       # Number of branches executed
system.cpu0.iew.exec_stores                     82042                       # Number of stores executed
system.cpu0.iew.exec_rate                    1.901466                       # Inst execution rate
system.cpu0.iew.wb_sent                        423189                       # cumulative count of insts sent to commit
system.cpu0.iew.wb_count                       422836                       # cumulative count of insts written-back
system.cpu0.iew.wb_producers                   250585                       # num instructions producing a value
system.cpu0.iew.wb_consumers                   253105                       # num instructions consuming a value
system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu0.iew.wb_rate                      1.897777                       # insts written-back per cycle
system.cpu0.iew.wb_fanout                    0.990044                       # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu0.commit.commitCommittedInsts        496189                       # The number of committed instructions
system.cpu0.commit.commitCommittedOps          496189                       # The number of committed instructions
system.cpu0.commit.commitSquashedInsts          12929                       # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls            559                       # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts             1303                       # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples       202233                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean     2.453551                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev     2.134267                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0        34442     17.03%     17.03% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1        83893     41.48%     58.51% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2         2396      1.18%     59.70% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3          690      0.34%     60.04% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4          548      0.27%     60.31% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5        79225     39.18%     99.49% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6          480      0.24%     99.72% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7          235      0.12%     99.84% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8          324      0.16%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total       202233                       # Number of insts commited each cycle
system.cpu0.commit.committedInsts              496189                       # Number of instructions committed
system.cpu0.commit.committedOps                496189                       # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu0.commit.refs                        242804                       # Number of memory references committed
system.cpu0.commit.loads                       161532                       # Number of loads committed
system.cpu0.commit.membars                         84                       # Number of memory barriers committed
system.cpu0.commit.branches                     83160                       # Number of branches committed
system.cpu0.commit.fp_insts                         0                       # Number of committed floating point instructions.
system.cpu0.commit.int_insts                   334226                       # Number of committed integer instructions.
system.cpu0.commit.function_calls                 223                       # Number of function calls committed.
system.cpu0.commit.bw_lim_events                  324                       # number cycles where commit BW limit reached
system.cpu0.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu0.rob.rob_reads                      709866                       # The number of ROB reads
system.cpu0.rob.rob_writes                    1020791                       # The number of ROB writes
system.cpu0.timesIdled                            320                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles                          18050                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.committedInsts                     416214                       # Number of Instructions Simulated
system.cpu0.committedOps                       416214                       # Number of Ops (including micro ops) Simulated
system.cpu0.committedInsts_total               416214                       # Number of Instructions Simulated
system.cpu0.cpi                              0.535316                       # CPI: Cycles Per Instruction
system.cpu0.cpi_total                        0.535316                       # CPI: Total CPI of All Threads
system.cpu0.ipc                              1.868056                       # IPC: Instructions Per Cycle
system.cpu0.ipc_total                        1.868056                       # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads                  757980                       # number of integer regfile reads
system.cpu0.int_regfile_writes                 341432                       # number of integer regfile writes
system.cpu0.fp_regfile_reads                      192                       # number of floating regfile reads
system.cpu0.misc_regfile_reads                 246952                       # number of misc regfile reads
system.cpu0.misc_regfile_writes                   564                       # number of misc regfile writes
system.cpu0.icache.replacements                   300                       # number of replacements
system.cpu0.icache.tagsinuse               248.673809                       # Cycle average of tags in use
system.cpu0.icache.total_refs                    5459                       # Total number of references to valid blocks.
system.cpu0.icache.sampled_refs                   593                       # Sample count of references to valid blocks.
system.cpu0.icache.avg_refs                  9.205734                       # Average number of references to valid blocks.
system.cpu0.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.occ_blocks::cpu0.inst   248.673809                       # Average occupied blocks per requestor
system.cpu0.icache.occ_percent::cpu0.inst     0.485691                       # Average percentage of cache occupancy
system.cpu0.icache.occ_percent::total        0.485691                       # Average percentage of cache occupancy
system.cpu0.icache.ReadReq_hits::cpu0.inst         5459                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total           5459                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst         5459                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total            5459                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst         5459                       # number of overall hits
system.cpu0.icache.overall_hits::total           5459                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst          759                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total          759                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst          759                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total           759                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst          759                       # number of overall misses
system.cpu0.icache.overall_misses::total          759                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst     29159500                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total     29159500                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst     29159500                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total     29159500                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst     29159500                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total     29159500                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst         6218                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total         6218                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst         6218                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total         6218                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst         6218                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total         6218                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.122065                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.122065                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.122065                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 38418.313570                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 38418.313570                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 38418.313570                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs        15500                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs                1                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs        15500                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst          165                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total          165                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst          165                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total          165                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst          165                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total          165                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst          594                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total          594                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst          594                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total          594                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst          594                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total          594                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst     21891000                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total     21891000                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst     21891000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total     21891000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst     21891000                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total     21891000                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.095529                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.095529                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.095529                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36853.535354                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 36853.535354                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 36853.535354                       # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.dcache.replacements                     8                       # number of replacements
system.cpu0.dcache.tagsinuse               141.285775                       # Cycle average of tags in use
system.cpu0.dcache.total_refs                  100453                       # Total number of references to valid blocks.
system.cpu0.dcache.sampled_refs                   174                       # Sample count of references to valid blocks.
system.cpu0.dcache.avg_refs                577.316092                       # Average number of references to valid blocks.
system.cpu0.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.occ_blocks::cpu0.data   141.285775                       # Average occupied blocks per requestor
system.cpu0.dcache.occ_percent::cpu0.data     0.275949                       # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::total        0.275949                       # Average percentage of cache occupancy
system.cpu0.dcache.ReadReq_hits::cpu0.data        83026                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total          83026                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data        80684                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total         80684                       # number of WriteReq hits
system.cpu0.dcache.SwapReq_hits::cpu0.data           22                       # number of SwapReq hits
system.cpu0.dcache.SwapReq_hits::total             22                       # number of SwapReq hits
system.cpu0.dcache.demand_hits::cpu0.data       163710                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total          163710                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data       163710                       # number of overall hits
system.cpu0.dcache.overall_hits::total         163710                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data          495                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total          495                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data          546                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total          546                       # number of WriteReq misses
system.cpu0.dcache.SwapReq_misses::cpu0.data           20                       # number of SwapReq misses
system.cpu0.dcache.SwapReq_misses::total           20                       # number of SwapReq misses
system.cpu0.dcache.demand_misses::cpu0.data         1041                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total          1041                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data         1041                       # number of overall misses
system.cpu0.dcache.overall_misses::total         1041                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data     13976000                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total     13976000                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data     24361986                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total     24361986                       # number of WriteReq miss cycles
system.cpu0.dcache.SwapReq_miss_latency::cpu0.data       380500                       # number of SwapReq miss cycles
system.cpu0.dcache.SwapReq_miss_latency::total       380500                       # number of SwapReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data     38337986                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total     38337986                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data     38337986                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total     38337986                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data        83521                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total        83521                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data        81230                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total        81230                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SwapReq_accesses::cpu0.data           42                       # number of SwapReq accesses(hits+misses)
system.cpu0.dcache.SwapReq_accesses::total           42                       # number of SwapReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data       164751                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total       164751                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data       164751                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total       164751                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.005927                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.006722                       # miss rate for WriteReq accesses
system.cpu0.dcache.SwapReq_miss_rate::cpu0.data     0.476190                       # miss rate for SwapReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.006319                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.006319                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 28234.343434                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44619.021978                       # average WriteReq miss latency
system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data        19025                       # average SwapReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 36828.036503                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 36828.036503                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs       194000                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs               19                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 10210.526316                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks            6                       # number of writebacks
system.cpu0.dcache.writebacks::total                6                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data          313                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total          313                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data          370                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total          370                       # number of WriteReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data          683                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total          683                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data          683                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total          683                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data          182                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total          182                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data          176                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total          176                       # number of WriteReq MSHR misses
system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data           20                       # number of SwapReq MSHR misses
system.cpu0.dcache.SwapReq_mshr_misses::total           20                       # number of SwapReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data          358                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total          358                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data          358                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total          358                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data      4954500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total      4954500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data      6250000                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total      6250000                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data       320500                       # number of SwapReq MSHR miss cycles
system.cpu0.dcache.SwapReq_mshr_miss_latency::total       320500                       # number of SwapReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data     11204500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total     11204500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data     11204500                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total     11204500                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.002179                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.002167                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data     0.476190                       # mshr miss rate for SwapReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.002173                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.002173                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 27222.527473                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35511.363636                       # average WriteReq mshr miss latency
system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data        16025                       # average SwapReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31297.486034                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31297.486034                       # average overall mshr miss latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.numCycles                          187393                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.BPredUnit.lookups                   57495                       # Number of BP lookups
system.cpu1.BPredUnit.condPredicted             54509                       # Number of conditional branches predicted
system.cpu1.BPredUnit.condIncorrect              1432                       # Number of conditional branches incorrect
system.cpu1.BPredUnit.BTBLookups                50945                       # Number of BTB lookups
system.cpu1.BPredUnit.BTBHits                   49902                       # Number of BTB hits
system.cpu1.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.BPredUnit.usedRAS                     759                       # Number of times the RAS was used to get a target.
system.cpu1.BPredUnit.RASInCorrect                232                       # Number of incorrect RAS predictions.
system.cpu1.fetch.icacheStallCycles             28506                       # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts                        323137                       # Number of instructions fetch has processed
system.cpu1.fetch.Branches                      57495                       # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches             50661                       # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles                       112599                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles                   4204                       # Number of cycles fetch has spent squashing
system.cpu1.fetch.BlockedCycles                 33253                       # Number of cycles fetch has spent blocked
system.cpu1.fetch.MiscStallCycles                   5                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.NoActiveThreadStallCycles         6513                       # Number of stall cycles due to no active thread to fetch from
system.cpu1.fetch.PendingTrapStallCycles         1058                       # Number of stall cycles due to pending traps
system.cpu1.fetch.CacheLines                    19809                       # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes                  287                       # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.rateDist::samples            184628                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean             1.750206                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev            2.168540                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0                   72029     39.01%     39.01% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1                   57027     30.89%     69.90% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2                    6026      3.26%     73.16% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3                    3313      1.79%     74.96% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4                     681      0.37%     75.33% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5                   39928     21.63%     96.95% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6                    1176      0.64%     97.59% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7                     885      0.48%     98.07% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8                    3563      1.93%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total              184628                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate                 0.306815                       # Number of branch fetches per cycle
system.cpu1.fetch.rate                       1.724381                       # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles                   34082                       # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles                29678                       # Number of cycles decode is blocked
system.cpu1.decode.RunCycles                   106549                       # Number of cycles decode is running
system.cpu1.decode.UnblockCycles                 5112                       # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles                  2694                       # Number of cycles decode is squashing
system.cpu1.decode.DecodedInsts                318863                       # Number of instructions handled by decode
system.cpu1.rename.SquashCycles                  2694                       # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles                   34823                       # Number of cycles rename is idle
system.cpu1.rename.BlockCycles                  15756                       # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles         13064                       # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles                   101771                       # Number of cycles rename is running
system.cpu1.rename.UnblockCycles                10007                       # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts                316589                       # Number of instructions processed by rename
system.cpu1.rename.IQFullEvents                    26                       # Number of times rename has blocked due to IQ full
system.cpu1.rename.LSQFullEvents                   63                       # Number of times rename has blocked due to LSQ full
system.cpu1.rename.RenamedOperands             221379                       # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups               610170                       # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups          610170                       # Number of integer rename lookups
system.cpu1.rename.CommittedMaps               206274                       # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps                   15105                       # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts              1171                       # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts          1292                       # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts                    12551                       # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads               90746                       # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores              43396                       # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads            43483                       # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores           38230                       # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded                    262560                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded               6300                       # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued                   264126                       # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued               64                       # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined          12570                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined        11522                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved           654                       # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples       184628                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean        1.430585                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev       1.313833                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0              69552     37.67%     37.67% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1              22561     12.22%     49.89% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2              43412     23.51%     73.40% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3              44019     23.84%     97.25% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4               3358      1.82%     99.07% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5               1272      0.69%     99.75% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6                343      0.19%     99.94% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7                 54      0.03%     99.97% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8                 57      0.03%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total         184628                       # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu                     21      6.65%      6.65% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult                     0      0.00%      6.65% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv                      0      0.00%      6.65% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      6.65% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      6.65% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      6.65% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult                   0      0.00%      6.65% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      6.65% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      6.65% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      6.65% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      6.65% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      6.65% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      6.65% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      6.65% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      6.65% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult                    0      0.00%      6.65% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      6.65% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift                   0      0.00%      6.65% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      6.65% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      6.65% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      6.65% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      6.65% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      6.65% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      6.65% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      6.65% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      6.65% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      6.65% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      6.65% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      6.65% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead                    85     26.90%     33.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite                  210     66.46%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu               126488     47.89%     47.89% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult                   0      0.00%     47.89% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     47.89% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     47.89% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     47.89% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     47.89% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     47.89% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     47.89% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     47.89% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     47.89% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     47.89% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     47.89% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     47.89% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     47.89% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     47.89% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     47.89% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     47.89% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     47.89% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     47.89% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     47.89% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     47.89% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     47.89% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     47.89% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     47.89% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     47.89% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc             0      0.00%     47.89% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     47.89% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     47.89% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     47.89% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead               94921     35.94%     83.83% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite              42717     16.17%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total                264126                       # Type of FU issued
system.cpu1.iq.rate                          1.409476                       # Inst issue rate
system.cpu1.iq.fu_busy_cnt                        316                       # FU busy when requested
system.cpu1.iq.fu_busy_rate                  0.001196                       # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads            713260                       # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes           281477                       # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses       262161                       # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes                 0                       # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses                264442                       # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads           37998                       # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads         2692                       # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses            2                       # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation           47                       # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores         1591                       # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked            0                       # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles                  2694                       # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles                   1681                       # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles                   49                       # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts             313238                       # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts              386                       # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts                90746                       # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts               43396                       # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts              1094                       # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents                    45                       # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents            47                       # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect           484                       # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect         1109                       # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts                1593                       # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts               262830                       # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts                89694                       # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts             1296                       # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
system.cpu1.iew.exec_nop                        44378                       # number of nop insts executed
system.cpu1.iew.exec_refs                      132319                       # number of memory reference insts executed
system.cpu1.iew.exec_branches                   53738                       # Number of branches executed
system.cpu1.iew.exec_stores                     42625                       # Number of stores executed
system.cpu1.iew.exec_rate                    1.402560                       # Inst execution rate
system.cpu1.iew.wb_sent                        262446                       # cumulative count of insts sent to commit
system.cpu1.iew.wb_count                       262161                       # cumulative count of insts written-back
system.cpu1.iew.wb_producers                   149144                       # num instructions producing a value
system.cpu1.iew.wb_consumers                   154061                       # num instructions consuming a value
system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu1.iew.wb_rate                      1.398990                       # insts written-back per cycle
system.cpu1.iew.wb_fanout                    0.968084                       # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu1.commit.commitCommittedInsts        298843                       # The number of committed instructions
system.cpu1.commit.commitCommittedOps          298843                       # The number of committed instructions
system.cpu1.commit.commitSquashedInsts          14389                       # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls           5646                       # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts             1432                       # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples       175422                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean     1.703566                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev     2.044466                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0        68710     39.17%     39.17% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1        51651     29.44%     68.61% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2         6180      3.52%     72.14% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3         6549      3.73%     75.87% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4         1541      0.88%     76.75% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5        38344     21.86%     98.61% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6          640      0.36%     98.97% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7          995      0.57%     99.54% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8          812      0.46%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total       175422                       # Number of insts commited each cycle
system.cpu1.commit.committedInsts              298843                       # Number of instructions committed
system.cpu1.commit.committedOps                298843                       # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu1.commit.refs                        129859                       # Number of memory references committed
system.cpu1.commit.loads                        88054                       # Number of loads committed
system.cpu1.commit.membars                       4938                       # Number of memory barriers committed
system.cpu1.commit.branches                     52708                       # Number of branches committed
system.cpu1.commit.fp_insts                         0                       # Number of committed floating point instructions.
system.cpu1.commit.int_insts                   204694                       # Number of committed integer instructions.
system.cpu1.commit.function_calls                 322                       # Number of function calls committed.
system.cpu1.commit.bw_lim_events                  812                       # number cycles where commit BW limit reached
system.cpu1.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu1.rob.rob_reads                      487255                       # The number of ROB reads
system.cpu1.rob.rob_writes                     629168                       # The number of ROB writes
system.cpu1.timesIdled                            232                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles                           2765                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles                       35411                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts                     250401                       # Number of Instructions Simulated
system.cpu1.committedOps                       250401                       # Number of Ops (including micro ops) Simulated
system.cpu1.committedInsts_total               250401                       # Number of Instructions Simulated
system.cpu1.cpi                              0.748372                       # CPI: Cycles Per Instruction
system.cpu1.cpi_total                        0.748372                       # CPI: Total CPI of All Threads
system.cpu1.ipc                              1.336235                       # IPC: Instructions Per Cycle
system.cpu1.ipc_total                        1.336235                       # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads                  456552                       # number of integer regfile reads
system.cpu1.int_regfile_writes                 212248                       # number of integer regfile writes
system.cpu1.fp_regfile_writes                      64                       # number of floating regfile writes
system.cpu1.misc_regfile_reads                 133945                       # number of misc regfile reads
system.cpu1.misc_regfile_writes                   646                       # number of misc regfile writes
system.cpu1.icache.replacements                   322                       # number of replacements
system.cpu1.icache.tagsinuse                82.769076                       # Cycle average of tags in use
system.cpu1.icache.total_refs                   19304                       # Total number of references to valid blocks.
system.cpu1.icache.sampled_refs                   435                       # Sample count of references to valid blocks.
system.cpu1.icache.avg_refs                 44.377011                       # Average number of references to valid blocks.
system.cpu1.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.occ_blocks::cpu1.inst    82.769076                       # Average occupied blocks per requestor
system.cpu1.icache.occ_percent::cpu1.inst     0.161658                       # Average percentage of cache occupancy
system.cpu1.icache.occ_percent::total        0.161658                       # Average percentage of cache occupancy
system.cpu1.icache.ReadReq_hits::cpu1.inst        19304                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total          19304                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst        19304                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total           19304                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst        19304                       # number of overall hits
system.cpu1.icache.overall_hits::total          19304                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst          505                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total          505                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst          505                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total           505                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst          505                       # number of overall misses
system.cpu1.icache.overall_misses::total          505                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst      7500500                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total      7500500                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst      7500500                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total      7500500                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst      7500500                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total      7500500                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst        19809                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total        19809                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst        19809                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total        19809                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst        19809                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total        19809                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.025493                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.025493                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.025493                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14852.475248                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14852.475248                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14852.475248                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst           70                       # number of ReadReq MSHR hits
system.cpu1.icache.ReadReq_mshr_hits::total           70                       # number of ReadReq MSHR hits
system.cpu1.icache.demand_mshr_hits::cpu1.inst           70                       # number of demand (read+write) MSHR hits
system.cpu1.icache.demand_mshr_hits::total           70                       # number of demand (read+write) MSHR hits
system.cpu1.icache.overall_mshr_hits::cpu1.inst           70                       # number of overall MSHR hits
system.cpu1.icache.overall_mshr_hits::total           70                       # number of overall MSHR hits
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst          435                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total          435                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst          435                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total          435                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst          435                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total          435                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst      5474500                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total      5474500                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst      5474500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total      5474500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst      5474500                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total      5474500                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.021960                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.021960                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.021960                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12585.057471                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12585.057471                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12585.057471                       # average overall mshr miss latency
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dcache.replacements                     2                       # number of replacements
system.cpu1.dcache.tagsinuse                24.070551                       # Cycle average of tags in use
system.cpu1.dcache.total_refs                   48111                       # Total number of references to valid blocks.
system.cpu1.dcache.sampled_refs                    30                       # Sample count of references to valid blocks.
system.cpu1.dcache.avg_refs               1603.700000                       # Average number of references to valid blocks.
system.cpu1.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.occ_blocks::cpu1.data    24.070551                       # Average occupied blocks per requestor
system.cpu1.dcache.occ_percent::cpu1.data     0.047013                       # Average percentage of cache occupancy
system.cpu1.dcache.occ_percent::total        0.047013                       # Average percentage of cache occupancy
system.cpu1.dcache.ReadReq_hits::cpu1.data        51204                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total          51204                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data        41589                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total         41589                       # number of WriteReq hits
system.cpu1.dcache.SwapReq_hits::cpu1.data           12                       # number of SwapReq hits
system.cpu1.dcache.SwapReq_hits::total             12                       # number of SwapReq hits
system.cpu1.dcache.demand_hits::cpu1.data        92793                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total           92793                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data        92793                       # number of overall hits
system.cpu1.dcache.overall_hits::total          92793                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data          475                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total          475                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data          154                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total          154                       # number of WriteReq misses
system.cpu1.dcache.SwapReq_misses::cpu1.data           50                       # number of SwapReq misses
system.cpu1.dcache.SwapReq_misses::total           50                       # number of SwapReq misses
system.cpu1.dcache.demand_misses::cpu1.data          629                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total           629                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data          629                       # number of overall misses
system.cpu1.dcache.overall_misses::total          629                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data      9635500                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total      9635500                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data      2967500                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total      2967500                       # number of WriteReq miss cycles
system.cpu1.dcache.SwapReq_miss_latency::cpu1.data      1038500                       # number of SwapReq miss cycles
system.cpu1.dcache.SwapReq_miss_latency::total      1038500                       # number of SwapReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data     12603000                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total     12603000                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data     12603000                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total     12603000                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data        51679                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total        51679                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data        41743                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total        41743                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SwapReq_accesses::cpu1.data           62                       # number of SwapReq accesses(hits+misses)
system.cpu1.dcache.SwapReq_accesses::total           62                       # number of SwapReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data        93422                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total        93422                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data        93422                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total        93422                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.009191                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.003689                       # miss rate for WriteReq accesses
system.cpu1.dcache.SwapReq_miss_rate::cpu1.data     0.806452                       # miss rate for SwapReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.006733                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.006733                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 20285.263158                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 19269.480519                       # average WriteReq miss latency
system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data        20770                       # average SwapReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20036.565978                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20036.565978                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks            1                       # number of writebacks
system.cpu1.dcache.writebacks::total                1                       # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data          319                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total          319                       # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data           45                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total           45                       # number of WriteReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data          364                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total          364                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data          364                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total          364                       # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data          156                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total          156                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data          109                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total          109                       # number of WriteReq MSHR misses
system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data           50                       # number of SwapReq MSHR misses
system.cpu1.dcache.SwapReq_mshr_misses::total           50                       # number of SwapReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data          265                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total          265                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data          265                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total          265                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data      2052000                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total      2052000                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data      1523500                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total      1523500                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data       888500                       # number of SwapReq MSHR miss cycles
system.cpu1.dcache.SwapReq_mshr_miss_latency::total       888500                       # number of SwapReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data      3575500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total      3575500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data      3575500                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total      3575500                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.003019                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.002611                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data     0.806452                       # mshr miss rate for SwapReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.002837                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.002837                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13153.846154                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 13977.064220                       # average WriteReq mshr miss latency
system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data        17770                       # average SwapReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13492.452830                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13492.452830                       # average overall mshr miss latency
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu2.numCycles                          187102                       # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu2.BPredUnit.lookups                   52366                       # Number of BP lookups
system.cpu2.BPredUnit.condPredicted             49346                       # Number of conditional branches predicted
system.cpu2.BPredUnit.condIncorrect              1501                       # Number of conditional branches incorrect
system.cpu2.BPredUnit.BTBLookups                45884                       # Number of BTB lookups
system.cpu2.BPredUnit.BTBHits                   44697                       # Number of BTB hits
system.cpu2.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu2.BPredUnit.usedRAS                     764                       # Number of times the RAS was used to get a target.
system.cpu2.BPredUnit.RASInCorrect                230                       # Number of incorrect RAS predictions.
system.cpu2.fetch.icacheStallCycles             30829                       # Number of cycles fetch is stalled on an Icache miss
system.cpu2.fetch.Insts                        289891                       # Number of instructions fetch has processed
system.cpu2.fetch.Branches                      52366                       # Number of branches that fetch encountered
system.cpu2.fetch.predictedBranches             45461                       # Number of branches that fetch has predicted taken
system.cpu2.fetch.Cycles                       103159                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu2.fetch.SquashCycles                   4491                       # Number of cycles fetch has spent squashing
system.cpu2.fetch.BlockedCycles                 37226                       # Number of cycles fetch has spent blocked
system.cpu2.fetch.MiscStallCycles                   5                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu2.fetch.NoActiveThreadStallCycles         6501                       # Number of stall cycles due to no active thread to fetch from
system.cpu2.fetch.PendingTrapStallCycles         1096                       # Number of stall cycles due to pending traps
system.cpu2.fetch.CacheLines                    21870                       # Number of cache lines fetched
system.cpu2.fetch.IcacheSquashes                  331                       # Number of outstanding Icache misses that were squashed
system.cpu2.fetch.rateDist::samples            181728                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::mean             1.595192                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::stdev            2.120038                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::0                   78569     43.23%     43.23% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::1                   52779     29.04%     72.28% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::2                    6971      3.84%     76.11% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::3                    3518      1.94%     78.05% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::4                     702      0.39%     78.44% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::5                   33444     18.40%     96.84% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::6                    1229      0.68%     97.51% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::7                     914      0.50%     98.02% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::8                    3602      1.98%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::total              181728                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.branchRate                 0.279879                       # Number of branch fetches per cycle
system.cpu2.fetch.rate                       1.549374                       # Number of inst fetches per cycle
system.cpu2.decode.IdleCycles                   37176                       # Number of cycles decode is idle
system.cpu2.decode.BlockedCycles                32970                       # Number of cycles decode is blocked
system.cpu2.decode.RunCycles                    96308                       # Number of cycles decode is running
system.cpu2.decode.UnblockCycles                 5861                       # Number of cycles decode is unblocking
system.cpu2.decode.SquashCycles                  2912                       # Number of cycles decode is squashing
system.cpu2.decode.DecodedInsts                285362                       # Number of instructions handled by decode
system.cpu2.rename.SquashCycles                  2912                       # Number of cycles rename is squashing
system.cpu2.rename.IdleCycles                   37970                       # Number of cycles rename is idle
system.cpu2.rename.BlockCycles                  18336                       # Number of cycles rename is blocking
system.cpu2.rename.serializeStallCycles         13742                       # count of cycles rename stalled for serializing inst
system.cpu2.rename.RunCycles                    90714                       # Number of cycles rename is running
system.cpu2.rename.UnblockCycles                11553                       # Number of cycles rename is unblocking
system.cpu2.rename.RenamedInsts                283108                       # Number of instructions processed by rename
system.cpu2.rename.IQFullEvents                    27                       # Number of times rename has blocked due to IQ full
system.cpu2.rename.LSQFullEvents                   56                       # Number of times rename has blocked due to LSQ full
system.cpu2.rename.RenamedOperands             197373                       # Number of destination operands rename has renamed
system.cpu2.rename.RenameLookups               538438                       # Number of register rename lookups that rename has made
system.cpu2.rename.int_rename_lookups          538438                       # Number of integer rename lookups
system.cpu2.rename.CommittedMaps               181356                       # Number of HB maps that are committed
system.cpu2.rename.UndoneMaps                   16017                       # Number of HB maps that are undone due to squashing
system.cpu2.rename.serializingInsts              1193                       # count of serializing insts renamed
system.cpu2.rename.tempSerializingInsts          1308                       # count of temporary serializing insts renamed
system.cpu2.rename.skidInsts                    14181                       # count of insts added to the skid buffer
system.cpu2.memDep0.insertedLoads               79045                       # Number of loads inserted to the mem dependence unit.
system.cpu2.memDep0.insertedStores              36977                       # Number of stores inserted to the mem dependence unit.
system.cpu2.memDep0.conflictingLoads            38155                       # Number of conflicting loads.
system.cpu2.memDep0.conflictingStores           31746                       # Number of conflicting stores.
system.cpu2.iq.iqInstsAdded                    233020                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu2.iq.iqNonSpecInstsAdded               7475                       # Number of non-speculative instructions added to the IQ
system.cpu2.iq.iqInstsIssued                   234915                       # Number of instructions issued
system.cpu2.iq.iqSquashedInstsIssued               73                       # Number of squashed instructions issued
system.cpu2.iq.iqSquashedInstsExamined          13691                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu2.iq.iqSquashedOperandsExamined        12875                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu2.iq.iqSquashedNonSpecRemoved           913                       # Number of squashed non-spec instructions that were removed
system.cpu2.iq.issued_per_cycle::samples       181728                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::mean        1.292674                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::stdev       1.310296                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::0              76657     42.18%     42.18% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::1              25237     13.89%     56.07% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::2              37132     20.43%     76.50% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::3              37732     20.76%     97.27% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::4               3274      1.80%     99.07% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::5               1229      0.68%     99.74% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::6                353      0.19%     99.94% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::7                 53      0.03%     99.97% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::8                 61      0.03%    100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::total         181728                       # Number of insts issued each cycle
system.cpu2.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntAlu                     21      6.69%      6.69% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntMult                     0      0.00%      6.69% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntDiv                      0      0.00%      6.69% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatAdd                    0      0.00%      6.69% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCmp                    0      0.00%      6.69% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCvt                    0      0.00%      6.69% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatMult                   0      0.00%      6.69% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatDiv                    0      0.00%      6.69% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%      6.69% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAdd                     0      0.00%      6.69% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%      6.69% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAlu                     0      0.00%      6.69% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCmp                     0      0.00%      6.69% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCvt                     0      0.00%      6.69% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMisc                    0      0.00%      6.69% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMult                    0      0.00%      6.69% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%      6.69% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShift                   0      0.00%      6.69% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%      6.69% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%      6.69% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%      6.69% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%      6.69% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%      6.69% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%      6.69% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%      6.69% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%      6.69% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%      6.69% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%      6.69% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%      6.69% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemRead                    83     26.43%     33.12% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemWrite                  210     66.88%    100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu2.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
system.cpu2.iq.FU_type_0::IntAlu               114779     48.86%     48.86% # Type of FU issued
system.cpu2.iq.FU_type_0::IntMult                   0      0.00%     48.86% # Type of FU issued
system.cpu2.iq.FU_type_0::IntDiv                    0      0.00%     48.86% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatAdd                  0      0.00%     48.86% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     48.86% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCvt                  0      0.00%     48.86% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     48.86% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatDiv                  0      0.00%     48.86% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     48.86% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     48.86% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     48.86% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     48.86% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     48.86% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     48.86% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMisc                  0      0.00%     48.86% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     48.86% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     48.86% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     48.86% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     48.86% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     48.86% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     48.86% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     48.86% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     48.86% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     48.86% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     48.86% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMisc             0      0.00%     48.86% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     48.86% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     48.86% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     48.86% # Type of FU issued
system.cpu2.iq.FU_type_0::MemRead               83862     35.70%     84.56% # Type of FU issued
system.cpu2.iq.FU_type_0::MemWrite              36274     15.44%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::total                234915                       # Type of FU issued
system.cpu2.iq.rate                          1.255545                       # Inst issue rate
system.cpu2.iq.fu_busy_cnt                        314                       # FU busy when requested
system.cpu2.iq.fu_busy_rate                  0.001337                       # FU busy rate (busy events/executed inst)
system.cpu2.iq.int_inst_queue_reads            651945                       # Number of integer instruction queue reads
system.cpu2.iq.int_inst_queue_writes           254231                       # Number of integer instruction queue writes
system.cpu2.iq.int_inst_queue_wakeup_accesses       232815                       # Number of integer instruction queue wakeup accesses
system.cpu2.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
system.cpu2.iq.fp_inst_queue_writes                 0                       # Number of floating instruction queue writes
system.cpu2.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
system.cpu2.iq.int_alu_accesses                235229                       # Number of integer alu accesses
system.cpu2.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
system.cpu2.iew.lsq.thread0.forwLoads           31545                       # Number of loads that had data forwarded from stores
system.cpu2.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu2.iew.lsq.thread0.squashedLoads         3013                       # Number of loads squashed
system.cpu2.iew.lsq.thread0.ignoredResponses            8                       # Number of memory responses ignored because the instruction is squashed
system.cpu2.iew.lsq.thread0.memOrderViolation           45                       # Number of memory ordering violations
system.cpu2.iew.lsq.thread0.squashedStores         1611                       # Number of stores squashed
system.cpu2.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu2.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu2.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
system.cpu2.iew.lsq.thread0.cacheBlocked            0                       # Number of times an access to memory failed due to the cache being blocked
system.cpu2.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu2.iew.iewSquashCycles                  2912                       # Number of cycles IEW is squashing
system.cpu2.iew.iewBlockCycles                   1924                       # Number of cycles IEW is blocking
system.cpu2.iew.iewUnblockCycles                   66                       # Number of cycles IEW is unblocking
system.cpu2.iew.iewDispatchedInsts             279572                       # Number of instructions dispatched to IQ
system.cpu2.iew.iewDispSquashedInsts              369                       # Number of squashed instructions skipped by dispatch
system.cpu2.iew.iewDispLoadInsts                79045                       # Number of dispatched load instructions
system.cpu2.iew.iewDispStoreInsts               36977                       # Number of dispatched store instructions
system.cpu2.iew.iewDispNonSpecInsts              1114                       # Number of dispatched non-speculative instructions
system.cpu2.iew.iewIQFullEvents                    62                       # Number of times the IQ has become full, causing a stall
system.cpu2.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
system.cpu2.iew.memOrderViolationEvents            45                       # Number of memory order violations
system.cpu2.iew.predictedTakenIncorrect           517                       # Number of branches that were predicted taken incorrectly
system.cpu2.iew.predictedNotTakenIncorrect         1138                       # Number of branches that were predicted not taken incorrectly
system.cpu2.iew.branchMispredicts                1655                       # Number of branch mispredicts detected at execute
system.cpu2.iew.iewExecutedInsts               233532                       # Number of executed instructions
system.cpu2.iew.iewExecLoadInsts                77718                       # Number of load instructions executed
system.cpu2.iew.iewExecSquashedInsts             1383                       # Number of squashed instructions skipped in execute
system.cpu2.iew.exec_swp                            0                       # number of swp insts executed
system.cpu2.iew.exec_nop                        39077                       # number of nop insts executed
system.cpu2.iew.exec_refs                      113896                       # number of memory reference insts executed
system.cpu2.iew.exec_branches                   48223                       # Number of branches executed
system.cpu2.iew.exec_stores                     36178                       # Number of stores executed
system.cpu2.iew.exec_rate                    1.248153                       # Inst execution rate
system.cpu2.iew.wb_sent                        233124                       # cumulative count of insts sent to commit
system.cpu2.iew.wb_count                       232815                       # cumulative count of insts written-back
system.cpu2.iew.wb_producers                   130712                       # num instructions producing a value
system.cpu2.iew.wb_consumers                   135609                       # num instructions consuming a value
system.cpu2.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu2.iew.wb_rate                      1.244321                       # insts written-back per cycle
system.cpu2.iew.wb_fanout                    0.963889                       # average fanout of values written-back
system.cpu2.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu2.commit.commitCommittedInsts        263733                       # The number of committed instructions
system.cpu2.commit.commitCommittedOps          263733                       # The number of committed instructions
system.cpu2.commit.commitSquashedInsts          15844                       # The number of squashed insts skipped by commit
system.cpu2.commit.commitNonSpecStalls           6562                       # The number of times commit has been forced to stall to communicate backwards
system.cpu2.commit.branchMispredicts             1501                       # The number of times a branch was mispredicted
system.cpu2.commit.committed_per_cycle::samples       172316                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::mean     1.530520                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::stdev     1.983884                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::0        76563     44.43%     44.43% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::1        46194     26.81%     71.24% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::2         6230      3.62%     74.85% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::3         7466      4.33%     79.19% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::4         1536      0.89%     80.08% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::5        32043     18.60%     98.67% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::6          480      0.28%     98.95% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::7          990      0.57%     99.53% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::8          814      0.47%    100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::total       172316                       # Number of insts commited each cycle
system.cpu2.commit.committedInsts              263733                       # Number of instructions committed
system.cpu2.commit.committedOps                263733                       # Number of ops (including micro ops) committed
system.cpu2.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu2.commit.refs                        111398                       # Number of memory references committed
system.cpu2.commit.loads                        76032                       # Number of loads committed
system.cpu2.commit.membars                       5840                       # Number of memory barriers committed
system.cpu2.commit.branches                     47167                       # Number of branches committed
system.cpu2.commit.fp_insts                         0                       # Number of committed floating point instructions.
system.cpu2.commit.int_insts                   180680                       # Number of committed integer instructions.
system.cpu2.commit.function_calls                 322                       # Number of function calls committed.
system.cpu2.commit.bw_lim_events                  814                       # number cycles where commit BW limit reached
system.cpu2.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu2.rob.rob_reads                      450492                       # The number of ROB reads
system.cpu2.rob.rob_writes                     562082                       # The number of ROB writes
system.cpu2.timesIdled                            233                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu2.idleCycles                           5374                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu2.quiesceCycles                       35702                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu2.committedInsts                     219944                       # Number of Instructions Simulated
system.cpu2.committedOps                       219944                       # Number of Ops (including micro ops) Simulated
system.cpu2.committedInsts_total               219944                       # Number of Instructions Simulated
system.cpu2.cpi                              0.850680                       # CPI: Cycles Per Instruction
system.cpu2.cpi_total                        0.850680                       # CPI: Total CPI of All Threads
system.cpu2.ipc                              1.175530                       # IPC: Instructions Per Cycle
system.cpu2.ipc_total                        1.175530                       # IPC: Total IPC of All Threads
system.cpu2.int_regfile_reads                  401453                       # number of integer regfile reads
system.cpu2.int_regfile_writes                 187612                       # number of integer regfile writes
system.cpu2.fp_regfile_writes                      64                       # number of floating regfile writes
system.cpu2.misc_regfile_reads                 115545                       # number of misc regfile reads
system.cpu2.misc_regfile_writes                   646                       # number of misc regfile writes
system.cpu2.icache.replacements                   325                       # number of replacements
system.cpu2.icache.tagsinuse                91.851117                       # Cycle average of tags in use
system.cpu2.icache.total_refs                   21358                       # Total number of references to valid blocks.
system.cpu2.icache.sampled_refs                   440                       # Sample count of references to valid blocks.
system.cpu2.icache.avg_refs                 48.540909                       # Average number of references to valid blocks.
system.cpu2.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu2.icache.occ_blocks::cpu2.inst    91.851117                       # Average occupied blocks per requestor
system.cpu2.icache.occ_percent::cpu2.inst     0.179397                       # Average percentage of cache occupancy
system.cpu2.icache.occ_percent::total        0.179397                       # Average percentage of cache occupancy
system.cpu2.icache.ReadReq_hits::cpu2.inst        21358                       # number of ReadReq hits
system.cpu2.icache.ReadReq_hits::total          21358                       # number of ReadReq hits
system.cpu2.icache.demand_hits::cpu2.inst        21358                       # number of demand (read+write) hits
system.cpu2.icache.demand_hits::total           21358                       # number of demand (read+write) hits
system.cpu2.icache.overall_hits::cpu2.inst        21358                       # number of overall hits
system.cpu2.icache.overall_hits::total          21358                       # number of overall hits
system.cpu2.icache.ReadReq_misses::cpu2.inst          512                       # number of ReadReq misses
system.cpu2.icache.ReadReq_misses::total          512                       # number of ReadReq misses
system.cpu2.icache.demand_misses::cpu2.inst          512                       # number of demand (read+write) misses
system.cpu2.icache.demand_misses::total           512                       # number of demand (read+write) misses
system.cpu2.icache.overall_misses::cpu2.inst          512                       # number of overall misses
system.cpu2.icache.overall_misses::total          512                       # number of overall misses
system.cpu2.icache.ReadReq_miss_latency::cpu2.inst     11141500                       # number of ReadReq miss cycles
system.cpu2.icache.ReadReq_miss_latency::total     11141500                       # number of ReadReq miss cycles
system.cpu2.icache.demand_miss_latency::cpu2.inst     11141500                       # number of demand (read+write) miss cycles
system.cpu2.icache.demand_miss_latency::total     11141500                       # number of demand (read+write) miss cycles
system.cpu2.icache.overall_miss_latency::cpu2.inst     11141500                       # number of overall miss cycles
system.cpu2.icache.overall_miss_latency::total     11141500                       # number of overall miss cycles
system.cpu2.icache.ReadReq_accesses::cpu2.inst        21870                       # number of ReadReq accesses(hits+misses)
system.cpu2.icache.ReadReq_accesses::total        21870                       # number of ReadReq accesses(hits+misses)
system.cpu2.icache.demand_accesses::cpu2.inst        21870                       # number of demand (read+write) accesses
system.cpu2.icache.demand_accesses::total        21870                       # number of demand (read+write) accesses
system.cpu2.icache.overall_accesses::cpu2.inst        21870                       # number of overall (read+write) accesses
system.cpu2.icache.overall_accesses::total        21870                       # number of overall (read+write) accesses
system.cpu2.icache.ReadReq_miss_rate::cpu2.inst     0.023411                       # miss rate for ReadReq accesses
system.cpu2.icache.demand_miss_rate::cpu2.inst     0.023411                       # miss rate for demand accesses
system.cpu2.icache.overall_miss_rate::cpu2.inst     0.023411                       # miss rate for overall accesses
system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 21760.742188                       # average ReadReq miss latency
system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 21760.742188                       # average overall miss latency
system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 21760.742188                       # average overall miss latency
system.cpu2.icache.blocked_cycles::no_mshrs        33000                       # number of cycles access was blocked
system.cpu2.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu2.icache.blocked::no_mshrs                1                       # number of cycles access was blocked
system.cpu2.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu2.icache.avg_blocked_cycles::no_mshrs        33000                       # average number of cycles each access was blocked
system.cpu2.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu2.icache.fast_writes                      0                       # number of fast writes performed
system.cpu2.icache.cache_copies                     0                       # number of cache copies performed
system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst           72                       # number of ReadReq MSHR hits
system.cpu2.icache.ReadReq_mshr_hits::total           72                       # number of ReadReq MSHR hits
system.cpu2.icache.demand_mshr_hits::cpu2.inst           72                       # number of demand (read+write) MSHR hits
system.cpu2.icache.demand_mshr_hits::total           72                       # number of demand (read+write) MSHR hits
system.cpu2.icache.overall_mshr_hits::cpu2.inst           72                       # number of overall MSHR hits
system.cpu2.icache.overall_mshr_hits::total           72                       # number of overall MSHR hits
system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst          440                       # number of ReadReq MSHR misses
system.cpu2.icache.ReadReq_mshr_misses::total          440                       # number of ReadReq MSHR misses
system.cpu2.icache.demand_mshr_misses::cpu2.inst          440                       # number of demand (read+write) MSHR misses
system.cpu2.icache.demand_mshr_misses::total          440                       # number of demand (read+write) MSHR misses
system.cpu2.icache.overall_mshr_misses::cpu2.inst          440                       # number of overall MSHR misses
system.cpu2.icache.overall_mshr_misses::total          440                       # number of overall MSHR misses
system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst      8467000                       # number of ReadReq MSHR miss cycles
system.cpu2.icache.ReadReq_mshr_miss_latency::total      8467000                       # number of ReadReq MSHR miss cycles
system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst      8467000                       # number of demand (read+write) MSHR miss cycles
system.cpu2.icache.demand_mshr_miss_latency::total      8467000                       # number of demand (read+write) MSHR miss cycles
system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst      8467000                       # number of overall MSHR miss cycles
system.cpu2.icache.overall_mshr_miss_latency::total      8467000                       # number of overall MSHR miss cycles
system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.020119                       # mshr miss rate for ReadReq accesses
system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst     0.020119                       # mshr miss rate for demand accesses
system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst     0.020119                       # mshr miss rate for overall accesses
system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 19243.181818                       # average ReadReq mshr miss latency
system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 19243.181818                       # average overall mshr miss latency
system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 19243.181818                       # average overall mshr miss latency
system.cpu2.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu2.dcache.replacements                     2                       # number of replacements
system.cpu2.dcache.tagsinuse                26.720433                       # Cycle average of tags in use
system.cpu2.dcache.total_refs                   41712                       # Total number of references to valid blocks.
system.cpu2.dcache.sampled_refs                    31                       # Sample count of references to valid blocks.
system.cpu2.dcache.avg_refs               1345.548387                       # Average number of references to valid blocks.
system.cpu2.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu2.dcache.occ_blocks::cpu2.data    26.720433                       # Average occupied blocks per requestor
system.cpu2.dcache.occ_percent::cpu2.data     0.052188                       # Average percentage of cache occupancy
system.cpu2.dcache.occ_percent::total        0.052188                       # Average percentage of cache occupancy
system.cpu2.dcache.ReadReq_hits::cpu2.data        45716                       # number of ReadReq hits
system.cpu2.dcache.ReadReq_hits::total          45716                       # number of ReadReq hits
system.cpu2.dcache.WriteReq_hits::cpu2.data        35144                       # number of WriteReq hits
system.cpu2.dcache.WriteReq_hits::total         35144                       # number of WriteReq hits
system.cpu2.dcache.SwapReq_hits::cpu2.data           14                       # number of SwapReq hits
system.cpu2.dcache.SwapReq_hits::total             14                       # number of SwapReq hits
system.cpu2.dcache.demand_hits::cpu2.data        80860                       # number of demand (read+write) hits
system.cpu2.dcache.demand_hits::total           80860                       # number of demand (read+write) hits
system.cpu2.dcache.overall_hits::cpu2.data        80860                       # number of overall hits
system.cpu2.dcache.overall_hits::total          80860                       # number of overall hits
system.cpu2.dcache.ReadReq_misses::cpu2.data          438                       # number of ReadReq misses
system.cpu2.dcache.ReadReq_misses::total          438                       # number of ReadReq misses
system.cpu2.dcache.WriteReq_misses::cpu2.data          146                       # number of WriteReq misses
system.cpu2.dcache.WriteReq_misses::total          146                       # number of WriteReq misses
system.cpu2.dcache.SwapReq_misses::cpu2.data           62                       # number of SwapReq misses
system.cpu2.dcache.SwapReq_misses::total           62                       # number of SwapReq misses
system.cpu2.dcache.demand_misses::cpu2.data          584                       # number of demand (read+write) misses
system.cpu2.dcache.demand_misses::total           584                       # number of demand (read+write) misses
system.cpu2.dcache.overall_misses::cpu2.data          584                       # number of overall misses
system.cpu2.dcache.overall_misses::total          584                       # number of overall misses
system.cpu2.dcache.ReadReq_miss_latency::cpu2.data     10255000                       # number of ReadReq miss cycles
system.cpu2.dcache.ReadReq_miss_latency::total     10255000                       # number of ReadReq miss cycles
system.cpu2.dcache.WriteReq_miss_latency::cpu2.data      2937000                       # number of WriteReq miss cycles
system.cpu2.dcache.WriteReq_miss_latency::total      2937000                       # number of WriteReq miss cycles
system.cpu2.dcache.SwapReq_miss_latency::cpu2.data      1181000                       # number of SwapReq miss cycles
system.cpu2.dcache.SwapReq_miss_latency::total      1181000                       # number of SwapReq miss cycles
system.cpu2.dcache.demand_miss_latency::cpu2.data     13192000                       # number of demand (read+write) miss cycles
system.cpu2.dcache.demand_miss_latency::total     13192000                       # number of demand (read+write) miss cycles
system.cpu2.dcache.overall_miss_latency::cpu2.data     13192000                       # number of overall miss cycles
system.cpu2.dcache.overall_miss_latency::total     13192000                       # number of overall miss cycles
system.cpu2.dcache.ReadReq_accesses::cpu2.data        46154                       # number of ReadReq accesses(hits+misses)
system.cpu2.dcache.ReadReq_accesses::total        46154                       # number of ReadReq accesses(hits+misses)
system.cpu2.dcache.WriteReq_accesses::cpu2.data        35290                       # number of WriteReq accesses(hits+misses)
system.cpu2.dcache.WriteReq_accesses::total        35290                       # number of WriteReq accesses(hits+misses)
system.cpu2.dcache.SwapReq_accesses::cpu2.data           76                       # number of SwapReq accesses(hits+misses)
system.cpu2.dcache.SwapReq_accesses::total           76                       # number of SwapReq accesses(hits+misses)
system.cpu2.dcache.demand_accesses::cpu2.data        81444                       # number of demand (read+write) accesses
system.cpu2.dcache.demand_accesses::total        81444                       # number of demand (read+write) accesses
system.cpu2.dcache.overall_accesses::cpu2.data        81444                       # number of overall (read+write) accesses
system.cpu2.dcache.overall_accesses::total        81444                       # number of overall (read+write) accesses
system.cpu2.dcache.ReadReq_miss_rate::cpu2.data     0.009490                       # miss rate for ReadReq accesses
system.cpu2.dcache.WriteReq_miss_rate::cpu2.data     0.004137                       # miss rate for WriteReq accesses
system.cpu2.dcache.SwapReq_miss_rate::cpu2.data     0.815789                       # miss rate for SwapReq accesses
system.cpu2.dcache.demand_miss_rate::cpu2.data     0.007171                       # miss rate for demand accesses
system.cpu2.dcache.overall_miss_rate::cpu2.data     0.007171                       # miss rate for overall accesses
system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 23413.242009                       # average ReadReq miss latency
system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 20116.438356                       # average WriteReq miss latency
system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 19048.387097                       # average SwapReq miss latency
system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 22589.041096                       # average overall miss latency
system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 22589.041096                       # average overall miss latency
system.cpu2.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu2.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu2.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu2.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu2.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.cpu2.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu2.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu2.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu2.dcache.writebacks::writebacks            1                       # number of writebacks
system.cpu2.dcache.writebacks::total                1                       # number of writebacks
system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data          267                       # number of ReadReq MSHR hits
system.cpu2.dcache.ReadReq_mshr_hits::total          267                       # number of ReadReq MSHR hits
system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data           45                       # number of WriteReq MSHR hits
system.cpu2.dcache.WriteReq_mshr_hits::total           45                       # number of WriteReq MSHR hits
system.cpu2.dcache.demand_mshr_hits::cpu2.data          312                       # number of demand (read+write) MSHR hits
system.cpu2.dcache.demand_mshr_hits::total          312                       # number of demand (read+write) MSHR hits
system.cpu2.dcache.overall_mshr_hits::cpu2.data          312                       # number of overall MSHR hits
system.cpu2.dcache.overall_mshr_hits::total          312                       # number of overall MSHR hits
system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data          171                       # number of ReadReq MSHR misses
system.cpu2.dcache.ReadReq_mshr_misses::total          171                       # number of ReadReq MSHR misses
system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data          101                       # number of WriteReq MSHR misses
system.cpu2.dcache.WriteReq_mshr_misses::total          101                       # number of WriteReq MSHR misses
system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data           62                       # number of SwapReq MSHR misses
system.cpu2.dcache.SwapReq_mshr_misses::total           62                       # number of SwapReq MSHR misses
system.cpu2.dcache.demand_mshr_misses::cpu2.data          272                       # number of demand (read+write) MSHR misses
system.cpu2.dcache.demand_mshr_misses::total          272                       # number of demand (read+write) MSHR misses
system.cpu2.dcache.overall_mshr_misses::cpu2.data          272                       # number of overall MSHR misses
system.cpu2.dcache.overall_mshr_misses::total          272                       # number of overall MSHR misses
system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data      2480000                       # number of ReadReq MSHR miss cycles
system.cpu2.dcache.ReadReq_mshr_miss_latency::total      2480000                       # number of ReadReq MSHR miss cycles
system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data      1516500                       # number of WriteReq MSHR miss cycles
system.cpu2.dcache.WriteReq_mshr_miss_latency::total      1516500                       # number of WriteReq MSHR miss cycles
system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data       995000                       # number of SwapReq MSHR miss cycles
system.cpu2.dcache.SwapReq_mshr_miss_latency::total       995000                       # number of SwapReq MSHR miss cycles
system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data      3996500                       # number of demand (read+write) MSHR miss cycles
system.cpu2.dcache.demand_mshr_miss_latency::total      3996500                       # number of demand (read+write) MSHR miss cycles
system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data      3996500                       # number of overall MSHR miss cycles
system.cpu2.dcache.overall_mshr_miss_latency::total      3996500                       # number of overall MSHR miss cycles
system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.003705                       # mshr miss rate for ReadReq accesses
system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.002862                       # mshr miss rate for WriteReq accesses
system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data     0.815789                       # mshr miss rate for SwapReq accesses
system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data     0.003340                       # mshr miss rate for demand accesses
system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data     0.003340                       # mshr miss rate for overall accesses
system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14502.923977                       # average ReadReq mshr miss latency
system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 15014.851485                       # average WriteReq mshr miss latency
system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 16048.387097                       # average SwapReq mshr miss latency
system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 14693.014706                       # average overall mshr miss latency
system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 14693.014706                       # average overall mshr miss latency
system.cpu2.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu3.numCycles                          186832                       # number of cpu cycles simulated
system.cpu3.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu3.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu3.BPredUnit.lookups                   49447                       # Number of BP lookups
system.cpu3.BPredUnit.condPredicted             46344                       # Number of conditional branches predicted
system.cpu3.BPredUnit.condIncorrect              1525                       # Number of conditional branches incorrect
system.cpu3.BPredUnit.BTBLookups                42752                       # Number of BTB lookups
system.cpu3.BPredUnit.BTBHits                   41712                       # Number of BTB hits
system.cpu3.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu3.BPredUnit.usedRAS                     813                       # Number of times the RAS was used to get a target.
system.cpu3.BPredUnit.RASInCorrect                232                       # Number of incorrect RAS predictions.
system.cpu3.fetch.icacheStallCycles             32933                       # Number of cycles fetch is stalled on an Icache miss
system.cpu3.fetch.Insts                        270157                       # Number of instructions fetch has processed
system.cpu3.fetch.Branches                      49447                       # Number of branches that fetch encountered
system.cpu3.fetch.predictedBranches             42525                       # Number of branches that fetch has predicted taken
system.cpu3.fetch.Cycles                        98584                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu3.fetch.SquashCycles                   4439                       # Number of cycles fetch has spent squashing
system.cpu3.fetch.BlockedCycles                 41922                       # Number of cycles fetch has spent blocked
system.cpu3.fetch.MiscStallCycles                   5                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu3.fetch.NoActiveThreadStallCycles         6509                       # Number of stall cycles due to no active thread to fetch from
system.cpu3.fetch.PendingTrapStallCycles         1070                       # Number of stall cycles due to pending traps
system.cpu3.fetch.CacheLines                    24454                       # Number of cache lines fetched
system.cpu3.fetch.IcacheSquashes                  317                       # Number of outstanding Icache misses that were squashed
system.cpu3.fetch.rateDist::samples            183862                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::mean             1.469347                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::stdev            2.064581                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::0                   85278     46.38%     46.38% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::1                   51117     27.80%     74.18% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::2                    8231      4.48%     78.66% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::3                    3382      1.84%     80.50% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::4                     704      0.38%     80.88% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::5                   29457     16.02%     96.90% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::6                    1168      0.64%     97.54% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::7                     877      0.48%     98.02% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::8                    3648      1.98%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::total              183862                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.branchRate                 0.264660                       # Number of branch fetches per cycle
system.cpu3.fetch.rate                       1.445989                       # Number of inst fetches per cycle
system.cpu3.decode.IdleCycles                   40520                       # Number of cycles decode is idle
system.cpu3.decode.BlockedCycles                36424                       # Number of cycles decode is blocked
system.cpu3.decode.RunCycles                    90525                       # Number of cycles decode is running
system.cpu3.decode.UnblockCycles                 7045                       # Number of cycles decode is unblocking
system.cpu3.decode.SquashCycles                  2839                       # Number of cycles decode is squashing
system.cpu3.decode.DecodedInsts                265643                       # Number of instructions handled by decode
system.cpu3.rename.SquashCycles                  2839                       # Number of cycles rename is squashing
system.cpu3.rename.IdleCycles                   41308                       # Number of cycles rename is idle
system.cpu3.rename.BlockCycles                  21637                       # Number of cycles rename is blocking
system.cpu3.rename.serializeStallCycles         13915                       # count of cycles rename stalled for serializing inst
system.cpu3.rename.RunCycles                    83785                       # Number of cycles rename is running
system.cpu3.rename.UnblockCycles                13869                       # Number of cycles rename is unblocking
system.cpu3.rename.RenamedInsts                263122                       # Number of instructions processed by rename
system.cpu3.rename.IQFullEvents                    18                       # Number of times rename has blocked due to IQ full
system.cpu3.rename.LSQFullEvents                   51                       # Number of times rename has blocked due to LSQ full
system.cpu3.rename.RenamedOperands             182223                       # Number of destination operands rename has renamed
system.cpu3.rename.RenameLookups               494224                       # Number of register rename lookups that rename has made
system.cpu3.rename.int_rename_lookups          494224                       # Number of integer rename lookups
system.cpu3.rename.CommittedMaps               166723                       # Number of HB maps that are committed
system.cpu3.rename.UndoneMaps                   15500                       # Number of HB maps that are undone due to squashing
system.cpu3.rename.serializingInsts              1230                       # count of serializing insts renamed
system.cpu3.rename.tempSerializingInsts          1367                       # count of temporary serializing insts renamed
system.cpu3.rename.skidInsts                    16602                       # count of insts added to the skid buffer
system.cpu3.memDep0.insertedLoads               72088                       # Number of loads inserted to the mem dependence unit.
system.cpu3.memDep0.insertedStores              32971                       # Number of stores inserted to the mem dependence unit.
system.cpu3.memDep0.conflictingLoads            35168                       # Number of conflicting loads.
system.cpu3.memDep0.conflictingStores           27743                       # Number of conflicting stores.
system.cpu3.iq.iqInstsAdded                    215022                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu3.iq.iqNonSpecInstsAdded               8560                       # Number of non-speculative instructions added to the IQ
system.cpu3.iq.iqInstsIssued                   218529                       # Number of instructions issued
system.cpu3.iq.iqSquashedInstsIssued               46                       # Number of squashed instructions issued
system.cpu3.iq.iqSquashedInstsExamined          12998                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu3.iq.iqSquashedOperandsExamined        11805                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu3.iq.iqSquashedNonSpecRemoved           824                       # Number of squashed non-spec instructions that were removed
system.cpu3.iq.issued_per_cycle::samples       183862                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::mean        1.188549                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::stdev       1.293380                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::0              83207     45.26%     45.26% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::1              28783     15.65%     60.91% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::2              33187     18.05%     78.96% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::3              33716     18.34%     97.30% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::4               3245      1.76%     99.06% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::5               1264      0.69%     99.75% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::6                353      0.19%     99.94% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::7                 50      0.03%     99.97% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::8                 57      0.03%    100.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::total         183862                       # Number of insts issued each cycle
system.cpu3.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::IntAlu                     21      7.02%      7.02% # attempts to use FU when none available
system.cpu3.iq.fu_full::IntMult                     0      0.00%      7.02% # attempts to use FU when none available
system.cpu3.iq.fu_full::IntDiv                      0      0.00%      7.02% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatAdd                    0      0.00%      7.02% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatCmp                    0      0.00%      7.02% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatCvt                    0      0.00%      7.02% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatMult                   0      0.00%      7.02% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatDiv                    0      0.00%      7.02% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatSqrt                   0      0.00%      7.02% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdAdd                     0      0.00%      7.02% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdAddAcc                  0      0.00%      7.02% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdAlu                     0      0.00%      7.02% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdCmp                     0      0.00%      7.02% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdCvt                     0      0.00%      7.02% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdMisc                    0      0.00%      7.02% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdMult                    0      0.00%      7.02% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdMultAcc                 0      0.00%      7.02% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdShift                   0      0.00%      7.02% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdShiftAcc                0      0.00%      7.02% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdSqrt                    0      0.00%      7.02% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatAdd                0      0.00%      7.02% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatAlu                0      0.00%      7.02% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatCmp                0      0.00%      7.02% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatCvt                0      0.00%      7.02% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatDiv                0      0.00%      7.02% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatMisc               0      0.00%      7.02% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatMult               0      0.00%      7.02% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatMultAcc            0      0.00%      7.02% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatSqrt               0      0.00%      7.02% # attempts to use FU when none available
system.cpu3.iq.fu_full::MemRead                    68     22.74%     29.77% # attempts to use FU when none available
system.cpu3.iq.fu_full::MemWrite                  210     70.23%    100.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu3.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
system.cpu3.iq.FU_type_0::IntAlu               107929     49.39%     49.39% # Type of FU issued
system.cpu3.iq.FU_type_0::IntMult                   0      0.00%     49.39% # Type of FU issued
system.cpu3.iq.FU_type_0::IntDiv                    0      0.00%     49.39% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatAdd                  0      0.00%     49.39% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatCmp                  0      0.00%     49.39% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatCvt                  0      0.00%     49.39% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatMult                 0      0.00%     49.39% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatDiv                  0      0.00%     49.39% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatSqrt                 0      0.00%     49.39% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdAdd                   0      0.00%     49.39% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdAddAcc                0      0.00%     49.39% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdAlu                   0      0.00%     49.39% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdCmp                   0      0.00%     49.39% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdCvt                   0      0.00%     49.39% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdMisc                  0      0.00%     49.39% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdMult                  0      0.00%     49.39% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdMultAcc               0      0.00%     49.39% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdShift                 0      0.00%     49.39% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdShiftAcc              0      0.00%     49.39% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdSqrt                  0      0.00%     49.39% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatAdd              0      0.00%     49.39% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatAlu              0      0.00%     49.39% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatCmp              0      0.00%     49.39% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatCvt              0      0.00%     49.39% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatDiv              0      0.00%     49.39% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatMisc             0      0.00%     49.39% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatMult             0      0.00%     49.39% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     49.39% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatSqrt             0      0.00%     49.39% # Type of FU issued
system.cpu3.iq.FU_type_0::MemRead               78286     35.82%     85.21% # Type of FU issued
system.cpu3.iq.FU_type_0::MemWrite              32314     14.79%    100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::total                218529                       # Type of FU issued
system.cpu3.iq.rate                          1.169655                       # Inst issue rate
system.cpu3.iq.fu_busy_cnt                        299                       # FU busy when requested
system.cpu3.iq.fu_busy_rate                  0.001368                       # FU busy rate (busy events/executed inst)
system.cpu3.iq.int_inst_queue_reads            621265                       # Number of integer instruction queue reads
system.cpu3.iq.int_inst_queue_writes           236621                       # Number of integer instruction queue writes
system.cpu3.iq.int_inst_queue_wakeup_accesses       216530                       # Number of integer instruction queue wakeup accesses
system.cpu3.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
system.cpu3.iq.fp_inst_queue_writes                 0                       # Number of floating instruction queue writes
system.cpu3.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
system.cpu3.iq.int_alu_accesses                218828                       # Number of integer alu accesses
system.cpu3.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
system.cpu3.iew.lsq.thread0.forwLoads           27592                       # Number of loads that had data forwarded from stores
system.cpu3.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu3.iew.lsq.thread0.squashedLoads         2778                       # Number of loads squashed
system.cpu3.iew.lsq.thread0.ignoredResponses            6                       # Number of memory responses ignored because the instruction is squashed
system.cpu3.iew.lsq.thread0.memOrderViolation           41                       # Number of memory ordering violations
system.cpu3.iew.lsq.thread0.squashedStores         1562                       # Number of stores squashed
system.cpu3.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu3.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu3.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
system.cpu3.iew.lsq.thread0.cacheBlocked            0                       # Number of times an access to memory failed due to the cache being blocked
system.cpu3.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu3.iew.iewSquashCycles                  2839                       # Number of cycles IEW is squashing
system.cpu3.iew.iewBlockCycles                   1746                       # Number of cycles IEW is blocking
system.cpu3.iew.iewUnblockCycles                   57                       # Number of cycles IEW is unblocking
system.cpu3.iew.iewDispatchedInsts             259780                       # Number of instructions dispatched to IQ
system.cpu3.iew.iewDispSquashedInsts              389                       # Number of squashed instructions skipped by dispatch
system.cpu3.iew.iewDispLoadInsts                72088                       # Number of dispatched load instructions
system.cpu3.iew.iewDispStoreInsts               32971                       # Number of dispatched store instructions
system.cpu3.iew.iewDispNonSpecInsts              1143                       # Number of dispatched non-speculative instructions
system.cpu3.iew.iewIQFullEvents                    55                       # Number of times the IQ has become full, causing a stall
system.cpu3.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
system.cpu3.iew.memOrderViolationEvents            41                       # Number of memory order violations
system.cpu3.iew.predictedTakenIncorrect           513                       # Number of branches that were predicted taken incorrectly
system.cpu3.iew.predictedNotTakenIncorrect         1186                       # Number of branches that were predicted not taken incorrectly
system.cpu3.iew.branchMispredicts                1699                       # Number of branch mispredicts detected at execute
system.cpu3.iew.iewExecutedInsts               217228                       # Number of executed instructions
system.cpu3.iew.iewExecLoadInsts                70964                       # Number of load instructions executed
system.cpu3.iew.iewExecSquashedInsts             1301                       # Number of squashed instructions skipped in execute
system.cpu3.iew.exec_swp                            0                       # number of swp insts executed
system.cpu3.iew.exec_nop                        36198                       # number of nop insts executed
system.cpu3.iew.exec_refs                      103196                       # number of memory reference insts executed
system.cpu3.iew.exec_branches                   45494                       # Number of branches executed
system.cpu3.iew.exec_stores                     32232                       # Number of stores executed
system.cpu3.iew.exec_rate                    1.162692                       # Inst execution rate
system.cpu3.iew.wb_sent                        216841                       # cumulative count of insts sent to commit
system.cpu3.iew.wb_count                       216530                       # cumulative count of insts written-back
system.cpu3.iew.wb_producers                   119982                       # num instructions producing a value
system.cpu3.iew.wb_consumers                   124874                       # num instructions consuming a value
system.cpu3.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu3.iew.wb_rate                      1.158956                       # insts written-back per cycle
system.cpu3.iew.wb_fanout                    0.960825                       # average fanout of values written-back
system.cpu3.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu3.commit.commitCommittedInsts        244729                       # The number of committed instructions
system.cpu3.commit.commitCommittedOps          244729                       # The number of committed instructions
system.cpu3.commit.commitSquashedInsts          15046                       # The number of squashed insts skipped by commit
system.cpu3.commit.commitNonSpecStalls           7736                       # The number of times commit has been forced to stall to communicate backwards
system.cpu3.commit.branchMispredicts             1525                       # The number of times a branch was mispredicted
system.cpu3.commit.committed_per_cycle::samples       174515                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::mean     1.402338                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::stdev     1.927125                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::0        84328     48.32%     48.32% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::1        43439     24.89%     73.21% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::2         6199      3.55%     76.76% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::3         8632      4.95%     81.71% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::4         1540      0.88%     82.59% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::5        28042     16.07%     98.66% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::6          531      0.30%     98.97% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::7          992      0.57%     99.53% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::8          812      0.47%    100.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::total       174515                       # Number of insts commited each cycle
system.cpu3.commit.committedInsts              244729                       # Number of instructions committed
system.cpu3.commit.committedOps                244729                       # Number of ops (including micro ops) committed
system.cpu3.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu3.commit.refs                        100719                       # Number of memory references committed
system.cpu3.commit.loads                        69310                       # Number of loads committed
system.cpu3.commit.membars                       7019                       # Number of memory barriers committed
system.cpu3.commit.branches                     44389                       # Number of branches committed
system.cpu3.commit.fp_insts                         0                       # Number of committed floating point instructions.
system.cpu3.commit.int_insts                   167227                       # Number of committed integer instructions.
system.cpu3.commit.function_calls                 322                       # Number of function calls committed.
system.cpu3.commit.bw_lim_events                  812                       # number cycles where commit BW limit reached
system.cpu3.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu3.rob.rob_reads                      432891                       # The number of ROB reads
system.cpu3.rob.rob_writes                     522404                       # The number of ROB writes
system.cpu3.timesIdled                            228                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu3.idleCycles                           2970                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu3.quiesceCycles                       35972                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu3.committedInsts                     202534                       # Number of Instructions Simulated
system.cpu3.committedOps                       202534                       # Number of Ops (including micro ops) Simulated
system.cpu3.committedInsts_total               202534                       # Number of Instructions Simulated
system.cpu3.cpi                              0.922472                       # CPI: Cycles Per Instruction
system.cpu3.cpi_total                        0.922472                       # CPI: Total CPI of All Threads
system.cpu3.ipc                              1.084043                       # IPC: Instructions Per Cycle
system.cpu3.ipc_total                        1.084043                       # IPC: Total IPC of All Threads
system.cpu3.int_regfile_reads                  369217                       # number of integer regfile reads
system.cpu3.int_regfile_writes                 172842                       # number of integer regfile writes
system.cpu3.fp_regfile_writes                      64                       # number of floating regfile writes
system.cpu3.misc_regfile_reads                 104868                       # number of misc regfile reads
system.cpu3.misc_regfile_writes                   646                       # number of misc regfile writes
system.cpu3.icache.replacements                   320                       # number of replacements
system.cpu3.icache.tagsinuse                85.923076                       # Cycle average of tags in use
system.cpu3.icache.total_refs                   23951                       # Total number of references to valid blocks.
system.cpu3.icache.sampled_refs                   432                       # Sample count of references to valid blocks.
system.cpu3.icache.avg_refs                 55.442130                       # Average number of references to valid blocks.
system.cpu3.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu3.icache.occ_blocks::cpu3.inst    85.923076                       # Average occupied blocks per requestor
system.cpu3.icache.occ_percent::cpu3.inst     0.167819                       # Average percentage of cache occupancy
system.cpu3.icache.occ_percent::total        0.167819                       # Average percentage of cache occupancy
system.cpu3.icache.ReadReq_hits::cpu3.inst        23951                       # number of ReadReq hits
system.cpu3.icache.ReadReq_hits::total          23951                       # number of ReadReq hits
system.cpu3.icache.demand_hits::cpu3.inst        23951                       # number of demand (read+write) hits
system.cpu3.icache.demand_hits::total           23951                       # number of demand (read+write) hits
system.cpu3.icache.overall_hits::cpu3.inst        23951                       # number of overall hits
system.cpu3.icache.overall_hits::total          23951                       # number of overall hits
system.cpu3.icache.ReadReq_misses::cpu3.inst          503                       # number of ReadReq misses
system.cpu3.icache.ReadReq_misses::total          503                       # number of ReadReq misses
system.cpu3.icache.demand_misses::cpu3.inst          503                       # number of demand (read+write) misses
system.cpu3.icache.demand_misses::total           503                       # number of demand (read+write) misses
system.cpu3.icache.overall_misses::cpu3.inst          503                       # number of overall misses
system.cpu3.icache.overall_misses::total          503                       # number of overall misses
system.cpu3.icache.ReadReq_miss_latency::cpu3.inst      6843000                       # number of ReadReq miss cycles
system.cpu3.icache.ReadReq_miss_latency::total      6843000                       # number of ReadReq miss cycles
system.cpu3.icache.demand_miss_latency::cpu3.inst      6843000                       # number of demand (read+write) miss cycles
system.cpu3.icache.demand_miss_latency::total      6843000                       # number of demand (read+write) miss cycles
system.cpu3.icache.overall_miss_latency::cpu3.inst      6843000                       # number of overall miss cycles
system.cpu3.icache.overall_miss_latency::total      6843000                       # number of overall miss cycles
system.cpu3.icache.ReadReq_accesses::cpu3.inst        24454                       # number of ReadReq accesses(hits+misses)
system.cpu3.icache.ReadReq_accesses::total        24454                       # number of ReadReq accesses(hits+misses)
system.cpu3.icache.demand_accesses::cpu3.inst        24454                       # number of demand (read+write) accesses
system.cpu3.icache.demand_accesses::total        24454                       # number of demand (read+write) accesses
system.cpu3.icache.overall_accesses::cpu3.inst        24454                       # number of overall (read+write) accesses
system.cpu3.icache.overall_accesses::total        24454                       # number of overall (read+write) accesses
system.cpu3.icache.ReadReq_miss_rate::cpu3.inst     0.020569                       # miss rate for ReadReq accesses
system.cpu3.icache.demand_miss_rate::cpu3.inst     0.020569                       # miss rate for demand accesses
system.cpu3.icache.overall_miss_rate::cpu3.inst     0.020569                       # miss rate for overall accesses
system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13604.373757                       # average ReadReq miss latency
system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13604.373757                       # average overall miss latency
system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13604.373757                       # average overall miss latency
system.cpu3.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu3.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu3.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu3.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu3.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.cpu3.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu3.icache.fast_writes                      0                       # number of fast writes performed
system.cpu3.icache.cache_copies                     0                       # number of cache copies performed
system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst           71                       # number of ReadReq MSHR hits
system.cpu3.icache.ReadReq_mshr_hits::total           71                       # number of ReadReq MSHR hits
system.cpu3.icache.demand_mshr_hits::cpu3.inst           71                       # number of demand (read+write) MSHR hits
system.cpu3.icache.demand_mshr_hits::total           71                       # number of demand (read+write) MSHR hits
system.cpu3.icache.overall_mshr_hits::cpu3.inst           71                       # number of overall MSHR hits
system.cpu3.icache.overall_mshr_hits::total           71                       # number of overall MSHR hits
system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst          432                       # number of ReadReq MSHR misses
system.cpu3.icache.ReadReq_mshr_misses::total          432                       # number of ReadReq MSHR misses
system.cpu3.icache.demand_mshr_misses::cpu3.inst          432                       # number of demand (read+write) MSHR misses
system.cpu3.icache.demand_mshr_misses::total          432                       # number of demand (read+write) MSHR misses
system.cpu3.icache.overall_mshr_misses::cpu3.inst          432                       # number of overall MSHR misses
system.cpu3.icache.overall_mshr_misses::total          432                       # number of overall MSHR misses
system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst      4912000                       # number of ReadReq MSHR miss cycles
system.cpu3.icache.ReadReq_mshr_miss_latency::total      4912000                       # number of ReadReq MSHR miss cycles
system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst      4912000                       # number of demand (read+write) MSHR miss cycles
system.cpu3.icache.demand_mshr_miss_latency::total      4912000                       # number of demand (read+write) MSHR miss cycles
system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst      4912000                       # number of overall MSHR miss cycles
system.cpu3.icache.overall_mshr_miss_latency::total      4912000                       # number of overall MSHR miss cycles
system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst     0.017666                       # mshr miss rate for ReadReq accesses
system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst     0.017666                       # mshr miss rate for demand accesses
system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst     0.017666                       # mshr miss rate for overall accesses
system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 11370.370370                       # average ReadReq mshr miss latency
system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 11370.370370                       # average overall mshr miss latency
system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 11370.370370                       # average overall mshr miss latency
system.cpu3.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu3.dcache.replacements                     2                       # number of replacements
system.cpu3.dcache.tagsinuse                25.290478                       # Cycle average of tags in use
system.cpu3.dcache.total_refs                   37716                       # Total number of references to valid blocks.
system.cpu3.dcache.sampled_refs                    30                       # Sample count of references to valid blocks.
system.cpu3.dcache.avg_refs               1257.200000                       # Average number of references to valid blocks.
system.cpu3.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu3.dcache.occ_blocks::cpu3.data    25.290478                       # Average occupied blocks per requestor
system.cpu3.dcache.occ_percent::cpu3.data     0.049395                       # Average percentage of cache occupancy
system.cpu3.dcache.occ_percent::total        0.049395                       # Average percentage of cache occupancy
system.cpu3.dcache.ReadReq_hits::cpu3.data        42933                       # number of ReadReq hits
system.cpu3.dcache.ReadReq_hits::total          42933                       # number of ReadReq hits
system.cpu3.dcache.WriteReq_hits::cpu3.data        31189                       # number of WriteReq hits
system.cpu3.dcache.WriteReq_hits::total         31189                       # number of WriteReq hits
system.cpu3.dcache.SwapReq_hits::cpu3.data           14                       # number of SwapReq hits
system.cpu3.dcache.SwapReq_hits::total             14                       # number of SwapReq hits
system.cpu3.dcache.demand_hits::cpu3.data        74122                       # number of demand (read+write) hits
system.cpu3.dcache.demand_hits::total           74122                       # number of demand (read+write) hits
system.cpu3.dcache.overall_hits::cpu3.data        74122                       # number of overall hits
system.cpu3.dcache.overall_hits::total          74122                       # number of overall hits
system.cpu3.dcache.ReadReq_misses::cpu3.data          420                       # number of ReadReq misses
system.cpu3.dcache.ReadReq_misses::total          420                       # number of ReadReq misses
system.cpu3.dcache.WriteReq_misses::cpu3.data          149                       # number of WriteReq misses
system.cpu3.dcache.WriteReq_misses::total          149                       # number of WriteReq misses
system.cpu3.dcache.SwapReq_misses::cpu3.data           57                       # number of SwapReq misses
system.cpu3.dcache.SwapReq_misses::total           57                       # number of SwapReq misses
system.cpu3.dcache.demand_misses::cpu3.data          569                       # number of demand (read+write) misses
system.cpu3.dcache.demand_misses::total           569                       # number of demand (read+write) misses
system.cpu3.dcache.overall_misses::cpu3.data          569                       # number of overall misses
system.cpu3.dcache.overall_misses::total          569                       # number of overall misses
system.cpu3.dcache.ReadReq_miss_latency::cpu3.data      8616000                       # number of ReadReq miss cycles
system.cpu3.dcache.ReadReq_miss_latency::total      8616000                       # number of ReadReq miss cycles
system.cpu3.dcache.WriteReq_miss_latency::cpu3.data      3007500                       # number of WriteReq miss cycles
system.cpu3.dcache.WriteReq_miss_latency::total      3007500                       # number of WriteReq miss cycles
system.cpu3.dcache.SwapReq_miss_latency::cpu3.data      1198000                       # number of SwapReq miss cycles
system.cpu3.dcache.SwapReq_miss_latency::total      1198000                       # number of SwapReq miss cycles
system.cpu3.dcache.demand_miss_latency::cpu3.data     11623500                       # number of demand (read+write) miss cycles
system.cpu3.dcache.demand_miss_latency::total     11623500                       # number of demand (read+write) miss cycles
system.cpu3.dcache.overall_miss_latency::cpu3.data     11623500                       # number of overall miss cycles
system.cpu3.dcache.overall_miss_latency::total     11623500                       # number of overall miss cycles
system.cpu3.dcache.ReadReq_accesses::cpu3.data        43353                       # number of ReadReq accesses(hits+misses)
system.cpu3.dcache.ReadReq_accesses::total        43353                       # number of ReadReq accesses(hits+misses)
system.cpu3.dcache.WriteReq_accesses::cpu3.data        31338                       # number of WriteReq accesses(hits+misses)
system.cpu3.dcache.WriteReq_accesses::total        31338                       # number of WriteReq accesses(hits+misses)
system.cpu3.dcache.SwapReq_accesses::cpu3.data           71                       # number of SwapReq accesses(hits+misses)
system.cpu3.dcache.SwapReq_accesses::total           71                       # number of SwapReq accesses(hits+misses)
system.cpu3.dcache.demand_accesses::cpu3.data        74691                       # number of demand (read+write) accesses
system.cpu3.dcache.demand_accesses::total        74691                       # number of demand (read+write) accesses
system.cpu3.dcache.overall_accesses::cpu3.data        74691                       # number of overall (read+write) accesses
system.cpu3.dcache.overall_accesses::total        74691                       # number of overall (read+write) accesses
system.cpu3.dcache.ReadReq_miss_rate::cpu3.data     0.009688                       # miss rate for ReadReq accesses
system.cpu3.dcache.WriteReq_miss_rate::cpu3.data     0.004755                       # miss rate for WriteReq accesses
system.cpu3.dcache.SwapReq_miss_rate::cpu3.data     0.802817                       # miss rate for SwapReq accesses
system.cpu3.dcache.demand_miss_rate::cpu3.data     0.007618                       # miss rate for demand accesses
system.cpu3.dcache.overall_miss_rate::cpu3.data     0.007618                       # miss rate for overall accesses
system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 20514.285714                       # average ReadReq miss latency
system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 20184.563758                       # average WriteReq miss latency
system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 21017.543860                       # average SwapReq miss latency
system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 20427.943761                       # average overall miss latency
system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 20427.943761                       # average overall miss latency
system.cpu3.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu3.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu3.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu3.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu3.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.cpu3.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu3.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu3.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu3.dcache.writebacks::writebacks            1                       # number of writebacks
system.cpu3.dcache.writebacks::total                1                       # number of writebacks
system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data          257                       # number of ReadReq MSHR hits
system.cpu3.dcache.ReadReq_mshr_hits::total          257                       # number of ReadReq MSHR hits
system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data           45                       # number of WriteReq MSHR hits
system.cpu3.dcache.WriteReq_mshr_hits::total           45                       # number of WriteReq MSHR hits
system.cpu3.dcache.demand_mshr_hits::cpu3.data          302                       # number of demand (read+write) MSHR hits
system.cpu3.dcache.demand_mshr_hits::total          302                       # number of demand (read+write) MSHR hits
system.cpu3.dcache.overall_mshr_hits::cpu3.data          302                       # number of overall MSHR hits
system.cpu3.dcache.overall_mshr_hits::total          302                       # number of overall MSHR hits
system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data          163                       # number of ReadReq MSHR misses
system.cpu3.dcache.ReadReq_mshr_misses::total          163                       # number of ReadReq MSHR misses
system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data          104                       # number of WriteReq MSHR misses
system.cpu3.dcache.WriteReq_mshr_misses::total          104                       # number of WriteReq MSHR misses
system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data           57                       # number of SwapReq MSHR misses
system.cpu3.dcache.SwapReq_mshr_misses::total           57                       # number of SwapReq MSHR misses
system.cpu3.dcache.demand_mshr_misses::cpu3.data          267                       # number of demand (read+write) MSHR misses
system.cpu3.dcache.demand_mshr_misses::total          267                       # number of demand (read+write) MSHR misses
system.cpu3.dcache.overall_mshr_misses::cpu3.data          267                       # number of overall MSHR misses
system.cpu3.dcache.overall_mshr_misses::total          267                       # number of overall MSHR misses
system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data      2151000                       # number of ReadReq MSHR miss cycles
system.cpu3.dcache.ReadReq_mshr_miss_latency::total      2151000                       # number of ReadReq MSHR miss cycles
system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data      1621000                       # number of WriteReq MSHR miss cycles
system.cpu3.dcache.WriteReq_mshr_miss_latency::total      1621000                       # number of WriteReq MSHR miss cycles
system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data      1027000                       # number of SwapReq MSHR miss cycles
system.cpu3.dcache.SwapReq_mshr_miss_latency::total      1027000                       # number of SwapReq MSHR miss cycles
system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data      3772000                       # number of demand (read+write) MSHR miss cycles
system.cpu3.dcache.demand_mshr_miss_latency::total      3772000                       # number of demand (read+write) MSHR miss cycles
system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data      3772000                       # number of overall MSHR miss cycles
system.cpu3.dcache.overall_mshr_miss_latency::total      3772000                       # number of overall MSHR miss cycles
system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data     0.003760                       # mshr miss rate for ReadReq accesses
system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data     0.003319                       # mshr miss rate for WriteReq accesses
system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data     0.802817                       # mshr miss rate for SwapReq accesses
system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data     0.003575                       # mshr miss rate for demand accesses
system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data     0.003575                       # mshr miss rate for overall accesses
system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 13196.319018                       # average ReadReq mshr miss latency
system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 15586.538462                       # average WriteReq mshr miss latency
system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 18017.543860                       # average SwapReq mshr miss latency
system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 14127.340824                       # average overall mshr miss latency
system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 14127.340824                       # average overall mshr miss latency
system.cpu3.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.l2c.replacements                             0                       # number of replacements
system.l2c.tagsinuse                       441.136869                       # Cycle average of tags in use
system.l2c.total_refs                            1471                       # Total number of references to valid blocks.
system.l2c.sampled_refs                           544                       # Sample count of references to valid blocks.
system.l2c.avg_refs                          2.704044                       # Average number of references to valid blocks.
system.l2c.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
system.l2c.occ_blocks::writebacks            4.878414                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.inst           294.783080                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.data            59.595754                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.inst             9.493651                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.data             0.732946                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu2.inst            64.319288                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu2.data             5.723296                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu3.inst             0.834559                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu3.data             0.775880                       # Average occupied blocks per requestor
system.l2c.occ_percent::writebacks           0.000074                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.inst            0.004498                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.data            0.000909                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.inst            0.000145                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.data            0.000011                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu2.inst            0.000981                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu2.data            0.000087                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu3.inst            0.000013                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu3.data            0.000012                       # Average percentage of cache occupancy
system.l2c.occ_percent::total                0.006731                       # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu0.inst                231                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data                  5                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst                420                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data                 13                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.inst                355                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.data                  7                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu3.inst                430                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu3.data                 13                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                   1474                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks               9                       # number of Writeback hits
system.l2c.Writeback_hits::total                    9                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data               3                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                   3                       # number of UpgradeReq hits
system.l2c.demand_hits::cpu0.inst                 231                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data                   5                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst                 420                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data                  13                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.inst                 355                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.data                   7                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.inst                 430                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.data                  13                       # number of demand (read+write) hits
system.l2c.demand_hits::total                    1474                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.inst                231                       # number of overall hits
system.l2c.overall_hits::cpu0.data                  5                       # number of overall hits
system.l2c.overall_hits::cpu1.inst                420                       # number of overall hits
system.l2c.overall_hits::cpu1.data                 13                       # number of overall hits
system.l2c.overall_hits::cpu2.inst                355                       # number of overall hits
system.l2c.overall_hits::cpu2.data                  7                       # number of overall hits
system.l2c.overall_hits::cpu3.inst                430                       # number of overall hits
system.l2c.overall_hits::cpu3.data                 13                       # number of overall hits
system.l2c.overall_hits::total                   1474                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.inst              363                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data               75                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst               15                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data                1                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.inst               85                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.data                7                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu3.inst                2                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu3.data                1                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                  549                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data            22                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data            21                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu2.data            17                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu3.data            20                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total                80                       # number of UpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data             94                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data             12                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu2.data             13                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu3.data             12                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total                131                       # number of ReadExReq misses
system.l2c.demand_misses::cpu0.inst               363                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data               169                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst                15                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data                13                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.inst                85                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.data                20                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu3.inst                 2                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu3.data                13                       # number of demand (read+write) misses
system.l2c.demand_misses::total                   680                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.inst              363                       # number of overall misses
system.l2c.overall_misses::cpu0.data              169                       # number of overall misses
system.l2c.overall_misses::cpu1.inst               15                       # number of overall misses
system.l2c.overall_misses::cpu1.data               13                       # number of overall misses
system.l2c.overall_misses::cpu2.inst               85                       # number of overall misses
system.l2c.overall_misses::cpu2.data               20                       # number of overall misses
system.l2c.overall_misses::cpu3.inst                2                       # number of overall misses
system.l2c.overall_misses::cpu3.data               13                       # number of overall misses
system.l2c.overall_misses::total                  680                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.inst     18919500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data      3929500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst       744500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data        52500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.inst      4376000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.data       366000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu3.inst        99500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu3.data        52500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total       28540000                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data        52500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu2.data        52500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu3.data        52500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total       157500                       # number of UpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data      4939500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data       627500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu2.data       680500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu3.data       627500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total      6875000                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.inst     18919500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data      8869000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst       744500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data       680000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.inst      4376000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.data      1046500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu3.inst        99500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu3.data       680000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total        35415000                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.inst     18919500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data      8869000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst       744500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data       680000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.inst      4376000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.data      1046500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3.inst        99500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3.data       680000                       # number of overall miss cycles
system.l2c.overall_miss_latency::total       35415000                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.inst            594                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data             80                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst            435                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data             14                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.inst            440                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.data             14                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu3.inst            432                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu3.data             14                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total               2023                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks            9                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total                9                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data           25                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data           21                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu2.data           17                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu3.data           20                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total              83                       # number of UpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data           94                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data           12                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu2.data           13                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu3.data           12                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total              131                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.inst             594                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data             174                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst             435                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data              26                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.inst             440                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.data              27                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3.inst             432                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3.data              26                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total                2154                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.inst            594                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data            174                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst            435                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data             26                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.inst            440                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.data             27                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3.inst            432                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3.data             26                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total               2154                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.inst      0.611111                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data      0.937500                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst      0.034483                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data      0.071429                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.inst      0.193182                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.data      0.500000                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu3.inst      0.004630                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu3.data      0.071429                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.880000                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data            1                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu2.data            1                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu3.data            1                       # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data            1                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data            1                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu2.data            1                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu3.data            1                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.inst       0.611111                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.971264                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.034483                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.500000                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.inst       0.193182                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.data       0.740741                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3.inst       0.004630                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3.data       0.500000                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.inst      0.611111                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.971264                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.034483                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.500000                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.inst      0.193182                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.data      0.740741                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3.inst      0.004630                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3.data      0.500000                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52119.834711                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 52393.333333                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 49633.333333                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data        52500                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.inst 51482.352941                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.data 52285.714286                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu3.inst        49750                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu3.data        52500                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data         2500                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu2.data  3088.235294                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu3.data         2625                       # average UpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52547.872340                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52291.666667                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu2.data 52346.153846                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu3.data 52291.666667                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 52119.834711                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 52479.289941                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 49633.333333                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 52307.692308                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.inst 51482.352941                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.data        52325                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3.inst        49750                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3.data 52307.692308                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 52119.834711                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 52479.289941                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 49633.333333                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 52307.692308                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.inst 51482.352941                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.data        52325                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3.inst        49750                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3.data 52307.692308                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs      no_value                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.ReadReq_mshr_hits::cpu1.inst             1                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu2.inst             5                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu3.inst             1                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total                 7                       # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst              1                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu2.inst              5                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu3.inst              1                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                  7                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst             1                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu2.inst             5                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu3.inst             1                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                 7                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.inst          363                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data           75                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst           14                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data            1                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.inst           80                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.data            7                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu3.inst            1                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu3.data            1                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total             542                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data           22                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data           21                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu2.data           17                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu3.data           20                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total           80                       # number of UpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data           94                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data           12                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu2.data           13                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu3.data           12                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total           131                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst          363                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data          169                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst           14                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data           13                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.inst           80                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.data           20                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3.inst            1                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3.data           13                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total              673                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst          363                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data          169                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst           14                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data           13                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.inst           80                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.data           20                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3.inst            1                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3.data           13                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total             673                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst     14492500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data      3016500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst       560000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data        40000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.inst      3200000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.data       280000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu3.inst        40000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu3.data        40000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total     21669000                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data       880000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data       840000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data       680000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data       800000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total      3200000                       # number of UpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data      3793000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data       481500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu2.data       522500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu3.data       481500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total      5278500                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst     14492500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data      6809500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst       560000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data       521500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.inst      3200000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.data       802500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3.inst        40000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3.data       521500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total     26947500                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst     14492500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data      6809500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst       560000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data       521500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.inst      3200000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.data       802500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3.inst        40000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3.data       521500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total     26947500                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.611111                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.937500                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.032184                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.071429                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.inst     0.181818                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.data     0.500000                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu3.inst     0.002315                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu3.data     0.071429                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.880000                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data            1                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data            1                       # mshr miss rate for UpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu2.data            1                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu3.data            1                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.611111                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.971264                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.032184                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.500000                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.inst     0.181818                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.data     0.740741                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3.inst     0.002315                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3.data     0.500000                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.611111                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.971264                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.032184                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.500000                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.inst     0.181818                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.data     0.740741                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.inst     0.002315                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.data     0.500000                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 39924.242424                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data        40220                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst        40000                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data        40000                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst        40000                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data        40000                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst        40000                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data        40000                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data        40000                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data        40000                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data        40000                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data        40000                       # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40351.063830                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data        40125                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 40192.307692                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data        40125                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 39924.242424                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40292.899408                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst        40000                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40115.384615                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst        40000                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.data        40125                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3.inst        40000                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40115.384615                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 39924.242424                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40292.899408                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst        40000                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40115.384615                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst        40000                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.data        40125                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.inst        40000                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40115.384615                       # average overall mshr miss latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------