tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 eventq_index=0
   5 full_system=false
   6 sim_quantum=0
   7 time_sync_enable=false
   8 time_sync_period=100000000000
   9 time_sync_spin_threshold=100000000
  10
  11 [system]
  12 type=System
  13 children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu_clk_domain dvfs_handler l2c membus physmem toL2Bus voltage_domain
  14 boot_osflags=a
  15 cache_line_size=64
  16 clk_domain=system.clk_domain
  17 eventq_index=0
  18 init_param=0
  19 kernel=
  20 kernel_addr_check=true
  21 load_addr_mask=1099511627775
  22 load_offset=0
  23 mem_mode=atomic
  24 mem_ranges=
  25 memories=system.physmem
  26 num_work_ids=16
  27 readfile=
  28 symbolfile=
  29 work_begin_ckpt_count=0
  30 work_begin_cpu_id_exit=-1
  31 work_begin_exit_count=0
  32 work_cpus_ckpt_count=0
  33 work_end_ckpt_count=0
  34 work_end_exit_count=0
  35 work_item_id=-1
  36 system_port=system.membus.slave[0]
  37
  38 [system.clk_domain]
  39 type=SrcClockDomain
  40 clock=1000
  41 domain_id=-1
  42 eventq_index=0
  43 init_perf_level=0
  44 voltage_domain=system.voltage_domain
  45
  46 [system.cpu0]
  47 type=AtomicSimpleCPU
  48 children=dcache dtb icache interrupts isa itb tracer workload
  49 branchPred=Null
  50 checker=Null
  51 clk_domain=system.cpu_clk_domain
  52 cpu_id=0
  53 do_checkpoint_insts=true
  54 do_quiesce=true
  55 do_statistics_insts=true
  56 dtb=system.cpu0.dtb
  57 eventq_index=0
  58 fastmem=false
  59 function_trace=false
  60 function_trace_start=0
  61 interrupts=system.cpu0.interrupts
  62 isa=system.cpu0.isa
  63 itb=system.cpu0.itb
  64 max_insts_all_threads=0
  65 max_insts_any_thread=0
  66 max_loads_all_threads=0
  67 max_loads_any_thread=0
  68 numThreads=1
  69 profile=0
  70 progress_interval=0
  71 simpoint_interval=100000000
  72 simpoint_profile=false
  73 simpoint_profile_file=simpoint.bb.gz
  74 simpoint_start_insts=
  75 simulate_data_stalls=false
  76 simulate_inst_stalls=false
  77 socket_id=0
  78 switched_out=false
  79 system=system
  80 tracer=system.cpu0.tracer
  81 width=1
  82 workload=system.cpu0.workload
  83 dcache_port=system.cpu0.dcache.cpu_side
  84 icache_port=system.cpu0.icache.cpu_side
  85
  86 [system.cpu0.dcache]
  87 type=BaseCache
  88 children=tags
  89 addr_ranges=0:18446744073709551615
  90 assoc=4
  91 clk_domain=system.cpu_clk_domain
  92 eventq_index=0
  93 forward_snoops=true
  94 hit_latency=2
  95 is_top_level=true
  96 max_miss_count=0
  97 mshrs=4
  98 prefetch_on_access=false
  99 prefetcher=Null
 100 response_latency=2
 101 sequential_access=false
 102 size=32768
 103 system=system
 104 tags=system.cpu0.dcache.tags
 105 tgts_per_mshr=20
 106 two_queue=false
 107 write_buffers=8
 108 cpu_side=system.cpu0.dcache_port
 109 mem_side=system.toL2Bus.slave[1]
 110
 111 [system.cpu0.dcache.tags]
 112 type=LRU
 113 assoc=4
 114 block_size=64
 115 clk_domain=system.cpu_clk_domain
 116 eventq_index=0
 117 hit_latency=2
 118 sequential_access=false
 119 size=32768
 120
 121 [system.cpu0.dtb]
 122 type=SparcTLB
 123 eventq_index=0
 124 size=64
 125
 126 [system.cpu0.icache]
 127 type=BaseCache
 128 children=tags
 129 addr_ranges=0:18446744073709551615
 130 assoc=1
 131 clk_domain=system.cpu_clk_domain
 132 eventq_index=0
 133 forward_snoops=true
 134 hit_latency=2
 135 is_top_level=true
 136 max_miss_count=0
 137 mshrs=4
 138 prefetch_on_access=false
 139 prefetcher=Null
 140 response_latency=2
 141 sequential_access=false
 142 size=32768
 143 system=system
 144 tags=system.cpu0.icache.tags
 145 tgts_per_mshr=20
 146 two_queue=false
 147 write_buffers=8
 148 cpu_side=system.cpu0.icache_port
 149 mem_side=system.toL2Bus.slave[0]
 150
 151 [system.cpu0.icache.tags]
 152 type=LRU
 153 assoc=1
 154 block_size=64
 155 clk_domain=system.cpu_clk_domain
 156 eventq_index=0
 157 hit_latency=2
 158 sequential_access=false
 159 size=32768
 160
 161 [system.cpu0.interrupts]
 162 type=SparcInterrupts
 163 eventq_index=0
 164
 165 [system.cpu0.isa]
 166 type=SparcISA
 167 eventq_index=0
 168
 169 [system.cpu0.itb]
 170 type=SparcTLB
 171 eventq_index=0
 172 size=64
 173
 174 [system.cpu0.tracer]
 175 type=ExeTracer
 176 eventq_index=0
 177
 178 [system.cpu0.workload]
 179 type=LiveProcess
 180 cmd=test_atomic 4
 181 cwd=
 182 egid=100
 183 env=
 184 errout=cerr
 185 euid=100
 186 eventq_index=0
 187 executable=/scratch/nilay/GEM5/gem5/tests/test-progs/m5threads/bin/sparc/linux/test_atomic
 188 gid=100
 189 input=cin
 190 max_stack_size=67108864
 191 output=cout
 192 pid=100
 193 ppid=99
 194 simpoint=0
 195 system=system
 196 uid=100
 197
 198 [system.cpu1]
 199 type=AtomicSimpleCPU
 200 children=dcache dtb icache interrupts isa itb tracer
 201 branchPred=Null
 202 checker=Null
 203 clk_domain=system.cpu_clk_domain
 204 cpu_id=1
 205 do_checkpoint_insts=true
 206 do_quiesce=true
 207 do_statistics_insts=true
 208 dtb=system.cpu1.dtb
 209 eventq_index=0
 210 fastmem=false
 211 function_trace=false
 212 function_trace_start=0
 213 interrupts=system.cpu1.interrupts
 214 isa=system.cpu1.isa
 215 itb=system.cpu1.itb
 216 max_insts_all_threads=0
 217 max_insts_any_thread=0
 218 max_loads_all_threads=0
 219 max_loads_any_thread=0
 220 numThreads=1
 221 profile=0
 222 progress_interval=0
 223 simpoint_interval=100000000
 224 simpoint_profile=false
 225 simpoint_profile_file=simpoint.bb.gz
 226 simpoint_start_insts=
 227 simulate_data_stalls=false
 228 simulate_inst_stalls=false
 229 socket_id=0
 230 switched_out=false
 231 system=system
 232 tracer=system.cpu1.tracer
 233 width=1
 234 workload=system.cpu0.workload
 235 dcache_port=system.cpu1.dcache.cpu_side
 236 icache_port=system.cpu1.icache.cpu_side
 237
 238 [system.cpu1.dcache]
 239 type=BaseCache
 240 children=tags
 241 addr_ranges=0:18446744073709551615
 242 assoc=4
 243 clk_domain=system.cpu_clk_domain
 244 eventq_index=0
 245 forward_snoops=true
 246 hit_latency=2
 247 is_top_level=true
 248 max_miss_count=0
 249 mshrs=4
 250 prefetch_on_access=false
 251 prefetcher=Null
 252 response_latency=2
 253 sequential_access=false
 254 size=32768
 255 system=system
 256 tags=system.cpu1.dcache.tags
 257 tgts_per_mshr=20
 258 two_queue=false
 259 write_buffers=8
 260 cpu_side=system.cpu1.dcache_port
 261 mem_side=system.toL2Bus.slave[3]
 262
 263 [system.cpu1.dcache.tags]
 264 type=LRU
 265 assoc=4
 266 block_size=64
 267 clk_domain=system.cpu_clk_domain
 268 eventq_index=0
 269 hit_latency=2
 270 sequential_access=false
 271 size=32768
 272
 273 [system.cpu1.dtb]
 274 type=SparcTLB
 275 eventq_index=0
 276 size=64
 277
 278 [system.cpu1.icache]
 279 type=BaseCache
 280 children=tags
 281 addr_ranges=0:18446744073709551615
 282 assoc=1
 283 clk_domain=system.cpu_clk_domain
 284 eventq_index=0
 285 forward_snoops=true
 286 hit_latency=2
 287 is_top_level=true
 288 max_miss_count=0
 289 mshrs=4
 290 prefetch_on_access=false
 291 prefetcher=Null
 292 response_latency=2
 293 sequential_access=false
 294 size=32768
 295 system=system
 296 tags=system.cpu1.icache.tags
 297 tgts_per_mshr=20
 298 two_queue=false
 299 write_buffers=8
 300 cpu_side=system.cpu1.icache_port
 301 mem_side=system.toL2Bus.slave[2]
 302
 303 [system.cpu1.icache.tags]
 304 type=LRU
 305 assoc=1
 306 block_size=64
 307 clk_domain=system.cpu_clk_domain
 308 eventq_index=0
 309 hit_latency=2
 310 sequential_access=false
 311 size=32768
 312
 313 [system.cpu1.interrupts]
 314 type=SparcInterrupts
 315 eventq_index=0
 316
 317 [system.cpu1.isa]
 318 type=SparcISA
 319 eventq_index=0
 320
 321 [system.cpu1.itb]
 322 type=SparcTLB
 323 eventq_index=0
 324 size=64
 325
 326 [system.cpu1.tracer]
 327 type=ExeTracer
 328 eventq_index=0
 329
 330 [system.cpu2]
 331 type=AtomicSimpleCPU
 332 children=dcache dtb icache interrupts isa itb tracer
 333 branchPred=Null
 334 checker=Null
 335 clk_domain=system.cpu_clk_domain
 336 cpu_id=2
 337 do_checkpoint_insts=true
 338 do_quiesce=true
 339 do_statistics_insts=true
 340 dtb=system.cpu2.dtb
 341 eventq_index=0
 342 fastmem=false
 343 function_trace=false
 344 function_trace_start=0
 345 interrupts=system.cpu2.interrupts
 346 isa=system.cpu2.isa
 347 itb=system.cpu2.itb
 348 max_insts_all_threads=0
 349 max_insts_any_thread=0
 350 max_loads_all_threads=0
 351 max_loads_any_thread=0
 352 numThreads=1
 353 profile=0
 354 progress_interval=0
 355 simpoint_interval=100000000
 356 simpoint_profile=false
 357 simpoint_profile_file=simpoint.bb.gz
 358 simpoint_start_insts=
 359 simulate_data_stalls=false
 360 simulate_inst_stalls=false
 361 socket_id=0
 362 switched_out=false
 363 system=system
 364 tracer=system.cpu2.tracer
 365 width=1
 366 workload=system.cpu0.workload
 367 dcache_port=system.cpu2.dcache.cpu_side
 368 icache_port=system.cpu2.icache.cpu_side
 369
 370 [system.cpu2.dcache]
 371 type=BaseCache
 372 children=tags
 373 addr_ranges=0:18446744073709551615
 374 assoc=4
 375 clk_domain=system.cpu_clk_domain
 376 eventq_index=0
 377 forward_snoops=true
 378 hit_latency=2
 379 is_top_level=true
 380 max_miss_count=0
 381 mshrs=4
 382 prefetch_on_access=false
 383 prefetcher=Null
 384 response_latency=2
 385 sequential_access=false
 386 size=32768
 387 system=system
 388 tags=system.cpu2.dcache.tags
 389 tgts_per_mshr=20
 390 two_queue=false
 391 write_buffers=8
 392 cpu_side=system.cpu2.dcache_port
 393 mem_side=system.toL2Bus.slave[5]
 394
 395 [system.cpu2.dcache.tags]
 396 type=LRU
 397 assoc=4
 398 block_size=64
 399 clk_domain=system.cpu_clk_domain
 400 eventq_index=0
 401 hit_latency=2
 402 sequential_access=false
 403 size=32768
 404
 405 [system.cpu2.dtb]
 406 type=SparcTLB
 407 eventq_index=0
 408 size=64
 409
 410 [system.cpu2.icache]
 411 type=BaseCache
 412 children=tags
 413 addr_ranges=0:18446744073709551615
 414 assoc=1
 415 clk_domain=system.cpu_clk_domain
 416 eventq_index=0
 417 forward_snoops=true
 418 hit_latency=2
 419 is_top_level=true
 420 max_miss_count=0
 421 mshrs=4
 422 prefetch_on_access=false
 423 prefetcher=Null
 424 response_latency=2
 425 sequential_access=false
 426 size=32768
 427 system=system
 428 tags=system.cpu2.icache.tags
 429 tgts_per_mshr=20
 430 two_queue=false
 431 write_buffers=8
 432 cpu_side=system.cpu2.icache_port
 433 mem_side=system.toL2Bus.slave[4]
 434
 435 [system.cpu2.icache.tags]
 436 type=LRU
 437 assoc=1
 438 block_size=64
 439 clk_domain=system.cpu_clk_domain
 440 eventq_index=0
 441 hit_latency=2
 442 sequential_access=false
 443 size=32768
 444
 445 [system.cpu2.interrupts]
 446 type=SparcInterrupts
 447 eventq_index=0
 448
 449 [system.cpu2.isa]
 450 type=SparcISA
 451 eventq_index=0
 452
 453 [system.cpu2.itb]
 454 type=SparcTLB
 455 eventq_index=0
 456 size=64
 457
 458 [system.cpu2.tracer]
 459 type=ExeTracer
 460 eventq_index=0
 461
 462 [system.cpu3]
 463 type=AtomicSimpleCPU
 464 children=dcache dtb icache interrupts isa itb tracer
 465 branchPred=Null
 466 checker=Null
 467 clk_domain=system.cpu_clk_domain
 468 cpu_id=3
 469 do_checkpoint_insts=true
 470 do_quiesce=true
 471 do_statistics_insts=true
 472 dtb=system.cpu3.dtb
 473 eventq_index=0
 474 fastmem=false
 475 function_trace=false
 476 function_trace_start=0
 477 interrupts=system.cpu3.interrupts
 478 isa=system.cpu3.isa
 479 itb=system.cpu3.itb
 480 max_insts_all_threads=0
 481 max_insts_any_thread=0
 482 max_loads_all_threads=0
 483 max_loads_any_thread=0
 484 numThreads=1
 485 profile=0
 486 progress_interval=0
 487 simpoint_interval=100000000
 488 simpoint_profile=false
 489 simpoint_profile_file=simpoint.bb.gz
 490 simpoint_start_insts=
 491 simulate_data_stalls=false
 492 simulate_inst_stalls=false
 493 socket_id=0
 494 switched_out=false
 495 system=system
 496 tracer=system.cpu3.tracer
 497 width=1
 498 workload=system.cpu0.workload
 499 dcache_port=system.cpu3.dcache.cpu_side
 500 icache_port=system.cpu3.icache.cpu_side
 501
 502 [system.cpu3.dcache]
 503 type=BaseCache
 504 children=tags
 505 addr_ranges=0:18446744073709551615
 506 assoc=4
 507 clk_domain=system.cpu_clk_domain
 508 eventq_index=0
 509 forward_snoops=true
 510 hit_latency=2
 511 is_top_level=true
 512 max_miss_count=0
 513 mshrs=4
 514 prefetch_on_access=false
 515 prefetcher=Null
 516 response_latency=2
 517 sequential_access=false
 518 size=32768
 519 system=system
 520 tags=system.cpu3.dcache.tags
 521 tgts_per_mshr=20
 522 two_queue=false
 523 write_buffers=8
 524 cpu_side=system.cpu3.dcache_port
 525 mem_side=system.toL2Bus.slave[7]
 526
 527 [system.cpu3.dcache.tags]
 528 type=LRU
 529 assoc=4
 530 block_size=64
 531 clk_domain=system.cpu_clk_domain
 532 eventq_index=0
 533 hit_latency=2
 534 sequential_access=false
 535 size=32768
 536
 537 [system.cpu3.dtb]
 538 type=SparcTLB
 539 eventq_index=0
 540 size=64
 541
 542 [system.cpu3.icache]
 543 type=BaseCache
 544 children=tags
 545 addr_ranges=0:18446744073709551615
 546 assoc=1
 547 clk_domain=system.cpu_clk_domain
 548 eventq_index=0
 549 forward_snoops=true
 550 hit_latency=2
 551 is_top_level=true
 552 max_miss_count=0
 553 mshrs=4
 554 prefetch_on_access=false
 555 prefetcher=Null
 556 response_latency=2
 557 sequential_access=false
 558 size=32768
 559 system=system
 560 tags=system.cpu3.icache.tags
 561 tgts_per_mshr=20
 562 two_queue=false
 563 write_buffers=8
 564 cpu_side=system.cpu3.icache_port
 565 mem_side=system.toL2Bus.slave[6]
 566
 567 [system.cpu3.icache.tags]
 568 type=LRU
 569 assoc=1
 570 block_size=64
 571 clk_domain=system.cpu_clk_domain
 572 eventq_index=0
 573 hit_latency=2
 574 sequential_access=false
 575 size=32768
 576
 577 [system.cpu3.interrupts]
 578 type=SparcInterrupts
 579 eventq_index=0
 580
 581 [system.cpu3.isa]
 582 type=SparcISA
 583 eventq_index=0
 584
 585 [system.cpu3.itb]
 586 type=SparcTLB
 587 eventq_index=0
 588 size=64
 589
 590 [system.cpu3.tracer]
 591 type=ExeTracer
 592 eventq_index=0
 593
 594 [system.cpu_clk_domain]
 595 type=SrcClockDomain
 596 clock=500
 597 domain_id=-1
 598 eventq_index=0
 599 init_perf_level=0
 600 voltage_domain=system.voltage_domain
 601
 602 [system.dvfs_handler]
 603 type=DVFSHandler
 604 domains=
 605 enable=false
 606 eventq_index=0
 607 sys_clk_domain=system.clk_domain
 608 transition_latency=100000000
 609
 610 [system.l2c]
 611 type=BaseCache
 612 children=tags
 613 addr_ranges=0:18446744073709551615
 614 assoc=8
 615 clk_domain=system.cpu_clk_domain
 616 eventq_index=0
 617 forward_snoops=true
 618 hit_latency=20
 619 is_top_level=false
 620 max_miss_count=0
 621 mshrs=20
 622 prefetch_on_access=false
 623 prefetcher=Null
 624 response_latency=20
 625 sequential_access=false
 626 size=4194304
 627 system=system
 628 tags=system.l2c.tags
 629 tgts_per_mshr=12
 630 two_queue=false
 631 write_buffers=8
 632 cpu_side=system.toL2Bus.master[0]
 633 mem_side=system.membus.slave[1]
 634
 635 [system.l2c.tags]
 636 type=LRU
 637 assoc=8
 638 block_size=64
 639 clk_domain=system.cpu_clk_domain
 640 eventq_index=0
 641 hit_latency=20
 642 sequential_access=false
 643 size=4194304
 644
 645 [system.membus]
 646 type=CoherentBus
 647 clk_domain=system.clk_domain
 648 eventq_index=0
 649 header_cycles=1
 650 system=system
 651 use_default_range=false
 652 width=8
 653 master=system.physmem.port
 654 slave=system.system_port system.l2c.mem_side
 655
 656 [system.physmem]
 657 type=SimpleMemory
 658 bandwidth=73.000000
 659 clk_domain=system.clk_domain
 660 conf_table_reported=true
 661 eventq_index=0
 662 in_addr_map=true
 663 latency=30000
 664 latency_var=0
 665 null=false
 666 range=0:134217727
 667 port=system.membus.master[0]
 668
 669 [system.toL2Bus]
 670 type=CoherentBus
 671 clk_domain=system.cpu_clk_domain
 672 eventq_index=0
 673 header_cycles=1
 674 system=system
 675 use_default_range=false
 676 width=8
 677 master=system.l2c.cpu_side
 678 slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side
 679
 680 [system.voltage_domain]
 681 type=VoltageDomain
 682 eventq_index=0
 683 voltage=1.000000
 684