tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 eventq_index=0
   5 full_system=false
   6 sim_quantum=0
   7 time_sync_enable=false
   8 time_sync_period=100000000000
   9 time_sync_spin_threshold=100000000
  10
  11 [system]
  12 type=System
  13 children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu_clk_domain dvfs_handler l2c membus physmem toL2Bus voltage_domain
  14 boot_osflags=a
  15 cache_line_size=64
  16 clk_domain=system.clk_domain
  17 eventq_index=0
  18 init_param=0
  19 kernel=
  20 kernel_addr_check=true
  21 load_addr_mask=1099511627775
  22 load_offset=0
  23 mem_mode=atomic
  24 mem_ranges=
  25 memories=system.physmem
  26 mmap_using_noreserve=false
  27 multi_thread=false
  28 num_work_ids=16
  29 readfile=
  30 symbolfile=
  31 work_begin_ckpt_count=0
  32 work_begin_cpu_id_exit=-1
  33 work_begin_exit_count=0
  34 work_cpus_ckpt_count=0
  35 work_end_ckpt_count=0
  36 work_end_exit_count=0
  37 work_item_id=-1
  38 system_port=system.membus.slave[0]
  39
  40 [system.clk_domain]
  41 type=SrcClockDomain
  42 clock=1000
  43 domain_id=-1
  44 eventq_index=0
  45 init_perf_level=0
  46 voltage_domain=system.voltage_domain
  47
  48 [system.cpu0]
  49 type=AtomicSimpleCPU
  50 children=dcache dtb icache interrupts isa itb tracer workload
  51 branchPred=Null
  52 checker=Null
  53 clk_domain=system.cpu_clk_domain
  54 cpu_id=0
  55 do_checkpoint_insts=true
  56 do_quiesce=true
  57 do_statistics_insts=true
  58 dtb=system.cpu0.dtb
  59 eventq_index=0
  60 fastmem=false
  61 function_trace=false
  62 function_trace_start=0
  63 interrupts=system.cpu0.interrupts
  64 isa=system.cpu0.isa
  65 itb=system.cpu0.itb
  66 max_insts_all_threads=0
  67 max_insts_any_thread=0
  68 max_loads_all_threads=0
  69 max_loads_any_thread=0
  70 numThreads=1
  71 profile=0
  72 progress_interval=0
  73 simpoint_start_insts=
  74 simulate_data_stalls=false
  75 simulate_inst_stalls=false
  76 socket_id=0
  77 switched_out=false
  78 system=system
  79 tracer=system.cpu0.tracer
  80 width=1
  81 workload=system.cpu0.workload
  82 dcache_port=system.cpu0.dcache.cpu_side
  83 icache_port=system.cpu0.icache.cpu_side
  84
  85 [system.cpu0.dcache]
  86 type=Cache
  87 children=tags
  88 addr_ranges=0:18446744073709551615
  89 assoc=4
  90 clk_domain=system.cpu_clk_domain
  91 clusivity=mostly_incl
  92 demand_mshr_reserve=1
  93 eventq_index=0
  94 forward_snoops=true
  95 hit_latency=2
  96 is_read_only=false
  97 max_miss_count=0
  98 mshrs=4
  99 prefetch_on_access=false
 100 prefetcher=Null
 101 response_latency=2
 102 sequential_access=false
 103 size=32768
 104 system=system
 105 tags=system.cpu0.dcache.tags
 106 tgts_per_mshr=20
 107 write_buffers=8
 108 writeback_clean=false
 109 cpu_side=system.cpu0.dcache_port
 110 mem_side=system.toL2Bus.slave[1]
 111
 112 [system.cpu0.dcache.tags]
 113 type=LRU
 114 assoc=4
 115 block_size=64
 116 clk_domain=system.cpu_clk_domain
 117 eventq_index=0
 118 hit_latency=2
 119 sequential_access=false
 120 size=32768
 121
 122 [system.cpu0.dtb]
 123 type=SparcTLB
 124 eventq_index=0
 125 size=64
 126
 127 [system.cpu0.icache]
 128 type=Cache
 129 children=tags
 130 addr_ranges=0:18446744073709551615
 131 assoc=1
 132 clk_domain=system.cpu_clk_domain
 133 clusivity=mostly_incl
 134 demand_mshr_reserve=1
 135 eventq_index=0
 136 forward_snoops=true
 137 hit_latency=2
 138 is_read_only=true
 139 max_miss_count=0
 140 mshrs=4
 141 prefetch_on_access=false
 142 prefetcher=Null
 143 response_latency=2
 144 sequential_access=false
 145 size=32768
 146 system=system
 147 tags=system.cpu0.icache.tags
 148 tgts_per_mshr=20
 149 write_buffers=8
 150 writeback_clean=true
 151 cpu_side=system.cpu0.icache_port
 152 mem_side=system.toL2Bus.slave[0]
 153
 154 [system.cpu0.icache.tags]
 155 type=LRU
 156 assoc=1
 157 block_size=64
 158 clk_domain=system.cpu_clk_domain
 159 eventq_index=0
 160 hit_latency=2
 161 sequential_access=false
 162 size=32768
 163
 164 [system.cpu0.interrupts]
 165 type=SparcInterrupts
 166 eventq_index=0
 167
 168 [system.cpu0.isa]
 169 type=SparcISA
 170 eventq_index=0
 171
 172 [system.cpu0.itb]
 173 type=SparcTLB
 174 eventq_index=0
 175 size=64
 176
 177 [system.cpu0.tracer]
 178 type=ExeTracer
 179 eventq_index=0
 180
 181 [system.cpu0.workload]
 182 type=LiveProcess
 183 cmd=test_atomic 4
 184 cwd=
 185 drivers=
 186 egid=100
 187 env=
 188 errout=cerr
 189 euid=100
 190 eventq_index=0
 191 executable=/dist/m5/regression/test-progs/m5threads/bin/sparc/linux/test_atomic
 192 gid=100
 193 input=cin
 194 kvmInSE=false
 195 max_stack_size=67108864
 196 output=cout
 197 pid=100
 198 ppid=99
 199 simpoint=0
 200 system=system
 201 uid=100
 202 useArchPT=false
 203
 204 [system.cpu1]
 205 type=AtomicSimpleCPU
 206 children=dcache dtb icache interrupts isa itb tracer
 207 branchPred=Null
 208 checker=Null
 209 clk_domain=system.cpu_clk_domain
 210 cpu_id=1
 211 do_checkpoint_insts=true
 212 do_quiesce=true
 213 do_statistics_insts=true
 214 dtb=system.cpu1.dtb
 215 eventq_index=0
 216 fastmem=false
 217 function_trace=false
 218 function_trace_start=0
 219 interrupts=system.cpu1.interrupts
 220 isa=system.cpu1.isa
 221 itb=system.cpu1.itb
 222 max_insts_all_threads=0
 223 max_insts_any_thread=0
 224 max_loads_all_threads=0
 225 max_loads_any_thread=0
 226 numThreads=1
 227 profile=0
 228 progress_interval=0
 229 simpoint_start_insts=
 230 simulate_data_stalls=false
 231 simulate_inst_stalls=false
 232 socket_id=0
 233 switched_out=false
 234 system=system
 235 tracer=system.cpu1.tracer
 236 width=1
 237 workload=system.cpu0.workload
 238 dcache_port=system.cpu1.dcache.cpu_side
 239 icache_port=system.cpu1.icache.cpu_side
 240
 241 [system.cpu1.dcache]
 242 type=Cache
 243 children=tags
 244 addr_ranges=0:18446744073709551615
 245 assoc=4
 246 clk_domain=system.cpu_clk_domain
 247 clusivity=mostly_incl
 248 demand_mshr_reserve=1
 249 eventq_index=0
 250 forward_snoops=true
 251 hit_latency=2
 252 is_read_only=false
 253 max_miss_count=0
 254 mshrs=4
 255 prefetch_on_access=false
 256 prefetcher=Null
 257 response_latency=2
 258 sequential_access=false
 259 size=32768
 260 system=system
 261 tags=system.cpu1.dcache.tags
 262 tgts_per_mshr=20
 263 write_buffers=8
 264 writeback_clean=false
 265 cpu_side=system.cpu1.dcache_port
 266 mem_side=system.toL2Bus.slave[3]
 267
 268 [system.cpu1.dcache.tags]
 269 type=LRU
 270 assoc=4
 271 block_size=64
 272 clk_domain=system.cpu_clk_domain
 273 eventq_index=0
 274 hit_latency=2
 275 sequential_access=false
 276 size=32768
 277
 278 [system.cpu1.dtb]
 279 type=SparcTLB
 280 eventq_index=0
 281 size=64
 282
 283 [system.cpu1.icache]
 284 type=Cache
 285 children=tags
 286 addr_ranges=0:18446744073709551615
 287 assoc=1
 288 clk_domain=system.cpu_clk_domain
 289 clusivity=mostly_incl
 290 demand_mshr_reserve=1
 291 eventq_index=0
 292 forward_snoops=true
 293 hit_latency=2
 294 is_read_only=true
 295 max_miss_count=0
 296 mshrs=4
 297 prefetch_on_access=false
 298 prefetcher=Null
 299 response_latency=2
 300 sequential_access=false
 301 size=32768
 302 system=system
 303 tags=system.cpu1.icache.tags
 304 tgts_per_mshr=20
 305 write_buffers=8
 306 writeback_clean=true
 307 cpu_side=system.cpu1.icache_port
 308 mem_side=system.toL2Bus.slave[2]
 309
 310 [system.cpu1.icache.tags]
 311 type=LRU
 312 assoc=1
 313 block_size=64
 314 clk_domain=system.cpu_clk_domain
 315 eventq_index=0
 316 hit_latency=2
 317 sequential_access=false
 318 size=32768
 319
 320 [system.cpu1.interrupts]
 321 type=SparcInterrupts
 322 eventq_index=0
 323
 324 [system.cpu1.isa]
 325 type=SparcISA
 326 eventq_index=0
 327
 328 [system.cpu1.itb]
 329 type=SparcTLB
 330 eventq_index=0
 331 size=64
 332
 333 [system.cpu1.tracer]
 334 type=ExeTracer
 335 eventq_index=0
 336
 337 [system.cpu2]
 338 type=AtomicSimpleCPU
 339 children=dcache dtb icache interrupts isa itb tracer
 340 branchPred=Null
 341 checker=Null
 342 clk_domain=system.cpu_clk_domain
 343 cpu_id=2
 344 do_checkpoint_insts=true
 345 do_quiesce=true
 346 do_statistics_insts=true
 347 dtb=system.cpu2.dtb
 348 eventq_index=0
 349 fastmem=false
 350 function_trace=false
 351 function_trace_start=0
 352 interrupts=system.cpu2.interrupts
 353 isa=system.cpu2.isa
 354 itb=system.cpu2.itb
 355 max_insts_all_threads=0
 356 max_insts_any_thread=0
 357 max_loads_all_threads=0
 358 max_loads_any_thread=0
 359 numThreads=1
 360 profile=0
 361 progress_interval=0
 362 simpoint_start_insts=
 363 simulate_data_stalls=false
 364 simulate_inst_stalls=false
 365 socket_id=0
 366 switched_out=false
 367 system=system
 368 tracer=system.cpu2.tracer
 369 width=1
 370 workload=system.cpu0.workload
 371 dcache_port=system.cpu2.dcache.cpu_side
 372 icache_port=system.cpu2.icache.cpu_side
 373
 374 [system.cpu2.dcache]
 375 type=Cache
 376 children=tags
 377 addr_ranges=0:18446744073709551615
 378 assoc=4
 379 clk_domain=system.cpu_clk_domain
 380 clusivity=mostly_incl
 381 demand_mshr_reserve=1
 382 eventq_index=0
 383 forward_snoops=true
 384 hit_latency=2
 385 is_read_only=false
 386 max_miss_count=0
 387 mshrs=4
 388 prefetch_on_access=false
 389 prefetcher=Null
 390 response_latency=2
 391 sequential_access=false
 392 size=32768
 393 system=system
 394 tags=system.cpu2.dcache.tags
 395 tgts_per_mshr=20
 396 write_buffers=8
 397 writeback_clean=false
 398 cpu_side=system.cpu2.dcache_port
 399 mem_side=system.toL2Bus.slave[5]
 400
 401 [system.cpu2.dcache.tags]
 402 type=LRU
 403 assoc=4
 404 block_size=64
 405 clk_domain=system.cpu_clk_domain
 406 eventq_index=0
 407 hit_latency=2
 408 sequential_access=false
 409 size=32768
 410
 411 [system.cpu2.dtb]
 412 type=SparcTLB
 413 eventq_index=0
 414 size=64
 415
 416 [system.cpu2.icache]
 417 type=Cache
 418 children=tags
 419 addr_ranges=0:18446744073709551615
 420 assoc=1
 421 clk_domain=system.cpu_clk_domain
 422 clusivity=mostly_incl
 423 demand_mshr_reserve=1
 424 eventq_index=0
 425 forward_snoops=true
 426 hit_latency=2
 427 is_read_only=true
 428 max_miss_count=0
 429 mshrs=4
 430 prefetch_on_access=false
 431 prefetcher=Null
 432 response_latency=2
 433 sequential_access=false
 434 size=32768
 435 system=system
 436 tags=system.cpu2.icache.tags
 437 tgts_per_mshr=20
 438 write_buffers=8
 439 writeback_clean=true
 440 cpu_side=system.cpu2.icache_port
 441 mem_side=system.toL2Bus.slave[4]
 442
 443 [system.cpu2.icache.tags]
 444 type=LRU
 445 assoc=1
 446 block_size=64
 447 clk_domain=system.cpu_clk_domain
 448 eventq_index=0
 449 hit_latency=2
 450 sequential_access=false
 451 size=32768
 452
 453 [system.cpu2.interrupts]
 454 type=SparcInterrupts
 455 eventq_index=0
 456
 457 [system.cpu2.isa]
 458 type=SparcISA
 459 eventq_index=0
 460
 461 [system.cpu2.itb]
 462 type=SparcTLB
 463 eventq_index=0
 464 size=64
 465
 466 [system.cpu2.tracer]
 467 type=ExeTracer
 468 eventq_index=0
 469
 470 [system.cpu3]
 471 type=AtomicSimpleCPU
 472 children=dcache dtb icache interrupts isa itb tracer
 473 branchPred=Null
 474 checker=Null
 475 clk_domain=system.cpu_clk_domain
 476 cpu_id=3
 477 do_checkpoint_insts=true
 478 do_quiesce=true
 479 do_statistics_insts=true
 480 dtb=system.cpu3.dtb
 481 eventq_index=0
 482 fastmem=false
 483 function_trace=false
 484 function_trace_start=0
 485 interrupts=system.cpu3.interrupts
 486 isa=system.cpu3.isa
 487 itb=system.cpu3.itb
 488 max_insts_all_threads=0
 489 max_insts_any_thread=0
 490 max_loads_all_threads=0
 491 max_loads_any_thread=0
 492 numThreads=1
 493 profile=0
 494 progress_interval=0
 495 simpoint_start_insts=
 496 simulate_data_stalls=false
 497 simulate_inst_stalls=false
 498 socket_id=0
 499 switched_out=false
 500 system=system
 501 tracer=system.cpu3.tracer
 502 width=1
 503 workload=system.cpu0.workload
 504 dcache_port=system.cpu3.dcache.cpu_side
 505 icache_port=system.cpu3.icache.cpu_side
 506
 507 [system.cpu3.dcache]
 508 type=Cache
 509 children=tags
 510 addr_ranges=0:18446744073709551615
 511 assoc=4
 512 clk_domain=system.cpu_clk_domain
 513 clusivity=mostly_incl
 514 demand_mshr_reserve=1
 515 eventq_index=0
 516 forward_snoops=true
 517 hit_latency=2
 518 is_read_only=false
 519 max_miss_count=0
 520 mshrs=4
 521 prefetch_on_access=false
 522 prefetcher=Null
 523 response_latency=2
 524 sequential_access=false
 525 size=32768
 526 system=system
 527 tags=system.cpu3.dcache.tags
 528 tgts_per_mshr=20
 529 write_buffers=8
 530 writeback_clean=false
 531 cpu_side=system.cpu3.dcache_port
 532 mem_side=system.toL2Bus.slave[7]
 533
 534 [system.cpu3.dcache.tags]
 535 type=LRU
 536 assoc=4
 537 block_size=64
 538 clk_domain=system.cpu_clk_domain
 539 eventq_index=0
 540 hit_latency=2
 541 sequential_access=false
 542 size=32768
 543
 544 [system.cpu3.dtb]
 545 type=SparcTLB
 546 eventq_index=0
 547 size=64
 548
 549 [system.cpu3.icache]
 550 type=Cache
 551 children=tags
 552 addr_ranges=0:18446744073709551615
 553 assoc=1
 554 clk_domain=system.cpu_clk_domain
 555 clusivity=mostly_incl
 556 demand_mshr_reserve=1
 557 eventq_index=0
 558 forward_snoops=true
 559 hit_latency=2
 560 is_read_only=true
 561 max_miss_count=0
 562 mshrs=4
 563 prefetch_on_access=false
 564 prefetcher=Null
 565 response_latency=2
 566 sequential_access=false
 567 size=32768
 568 system=system
 569 tags=system.cpu3.icache.tags
 570 tgts_per_mshr=20
 571 write_buffers=8
 572 writeback_clean=true
 573 cpu_side=system.cpu3.icache_port
 574 mem_side=system.toL2Bus.slave[6]
 575
 576 [system.cpu3.icache.tags]
 577 type=LRU
 578 assoc=1
 579 block_size=64
 580 clk_domain=system.cpu_clk_domain
 581 eventq_index=0
 582 hit_latency=2
 583 sequential_access=false
 584 size=32768
 585
 586 [system.cpu3.interrupts]
 587 type=SparcInterrupts
 588 eventq_index=0
 589
 590 [system.cpu3.isa]
 591 type=SparcISA
 592 eventq_index=0
 593
 594 [system.cpu3.itb]
 595 type=SparcTLB
 596 eventq_index=0
 597 size=64
 598
 599 [system.cpu3.tracer]
 600 type=ExeTracer
 601 eventq_index=0
 602
 603 [system.cpu_clk_domain]
 604 type=SrcClockDomain
 605 clock=500
 606 domain_id=-1
 607 eventq_index=0
 608 init_perf_level=0
 609 voltage_domain=system.voltage_domain
 610
 611 [system.dvfs_handler]
 612 type=DVFSHandler
 613 domains=
 614 enable=false
 615 eventq_index=0
 616 sys_clk_domain=system.clk_domain
 617 transition_latency=100000000
 618
 619 [system.l2c]
 620 type=Cache
 621 children=tags
 622 addr_ranges=0:18446744073709551615
 623 assoc=8
 624 clk_domain=system.cpu_clk_domain
 625 clusivity=mostly_incl
 626 demand_mshr_reserve=1
 627 eventq_index=0
 628 forward_snoops=true
 629 hit_latency=20
 630 is_read_only=false
 631 max_miss_count=0
 632 mshrs=20
 633 prefetch_on_access=false
 634 prefetcher=Null
 635 response_latency=20
 636 sequential_access=false
 637 size=4194304
 638 system=system
 639 tags=system.l2c.tags
 640 tgts_per_mshr=12
 641 write_buffers=8
 642 writeback_clean=false
 643 cpu_side=system.toL2Bus.master[0]
 644 mem_side=system.membus.slave[1]
 645
 646 [system.l2c.tags]
 647 type=LRU
 648 assoc=8
 649 block_size=64
 650 clk_domain=system.cpu_clk_domain
 651 eventq_index=0
 652 hit_latency=20
 653 sequential_access=false
 654 size=4194304
 655
 656 [system.membus]
 657 type=CoherentXBar
 658 clk_domain=system.clk_domain
 659 eventq_index=0
 660 forward_latency=4
 661 frontend_latency=3
 662 response_latency=2
 663 snoop_filter=Null
 664 snoop_response_latency=4
 665 system=system
 666 use_default_range=false
 667 width=16
 668 master=system.physmem.port
 669 slave=system.system_port system.l2c.mem_side
 670
 671 [system.physmem]
 672 type=SimpleMemory
 673 bandwidth=73.000000
 674 clk_domain=system.clk_domain
 675 conf_table_reported=true
 676 eventq_index=0
 677 in_addr_map=true
 678 latency=30000
 679 latency_var=0
 680 null=false
 681 range=0:134217727
 682 port=system.membus.master[0]
 683
 684 [system.toL2Bus]
 685 type=CoherentXBar
 686 children=snoop_filter
 687 clk_domain=system.cpu_clk_domain
 688 eventq_index=0
 689 forward_latency=0
 690 frontend_latency=1
 691 response_latency=1
 692 snoop_filter=system.toL2Bus.snoop_filter
 693 snoop_response_latency=1
 694 system=system
 695 use_default_range=false
 696 width=32
 697 master=system.l2c.cpu_side
 698 slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side
 699
 700 [system.toL2Bus.snoop_filter]
 701 type=SnoopFilter
 702 eventq_index=0
 703 lookup_latency=0
 704 max_capacity=8388608
 705 system=system
 706
 707 [system.voltage_domain]
 708 type=VoltageDomain
 709 eventq_index=0
 710 voltage=1.000000
 711