2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.000088 # Number of seconds simulated
4 sim_ticks 87707000 # Number of ticks simulated
5 final_tick 87707000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 170274 # Simulator instruction rate (inst/s)
8 host_op_rate 170274 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 22048637 # Simulator tick rate (ticks/s)
10 host_mem_usage 246052 # Number of bytes of host memory used
11 host_seconds 3.98 # Real time elapsed on the host
12 sim_insts 677327 # Number of instructions simulated
13 sim_ops 677327 # Number of ops (including micro ops) simulated
14 system.physmem.bytes_read::cpu0.inst 18048 # Number of bytes read from this memory
15 system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory
16 system.physmem.bytes_read::cpu1.inst 3968 # Number of bytes read from this memory
17 system.physmem.bytes_read::cpu1.data 1280 # Number of bytes read from this memory
18 system.physmem.bytes_read::cpu2.inst 128 # Number of bytes read from this memory
19 system.physmem.bytes_read::cpu2.data 832 # Number of bytes read from this memory
20 system.physmem.bytes_read::cpu3.inst 128 # Number of bytes read from this memory
21 system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory
22 system.physmem.bytes_read::total 35776 # Number of bytes read from this memory
23 system.physmem.bytes_inst_read::cpu0.inst 18048 # Number of instructions bytes read from this memory
24 system.physmem.bytes_inst_read::cpu1.inst 3968 # Number of instructions bytes read from this memory
25 system.physmem.bytes_inst_read::cpu2.inst 128 # Number of instructions bytes read from this memory
26 system.physmem.bytes_inst_read::cpu3.inst 128 # Number of instructions bytes read from this memory
27 system.physmem.bytes_inst_read::total 22272 # Number of instructions bytes read from this memory
28 system.physmem.num_reads::cpu0.inst 282 # Number of read requests responded to by this memory
29 system.physmem.num_reads::cpu0.data 165 # Number of read requests responded to by this memory
30 system.physmem.num_reads::cpu1.inst 62 # Number of read requests responded to by this memory
31 system.physmem.num_reads::cpu1.data 20 # Number of read requests responded to by this memory
32 system.physmem.num_reads::cpu2.inst 2 # Number of read requests responded to by this memory
33 system.physmem.num_reads::cpu2.data 13 # Number of read requests responded to by this memory
34 system.physmem.num_reads::cpu3.inst 2 # Number of read requests responded to by this memory
35 system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory
36 system.physmem.num_reads::total 559 # Number of read requests responded to by this memory
37 system.physmem.bw_read::cpu0.inst 205776050 # Total read bandwidth from this memory (bytes/s)
38 system.physmem.bw_read::cpu0.data 120400880 # Total read bandwidth from this memory (bytes/s)
39 system.physmem.bw_read::cpu1.inst 45241543 # Total read bandwidth from this memory (bytes/s)
40 system.physmem.bw_read::cpu1.data 14594046 # Total read bandwidth from this memory (bytes/s)
41 system.physmem.bw_read::cpu2.inst 1459405 # Total read bandwidth from this memory (bytes/s)
42 system.physmem.bw_read::cpu2.data 9486130 # Total read bandwidth from this memory (bytes/s)
43 system.physmem.bw_read::cpu3.inst 1459405 # Total read bandwidth from this memory (bytes/s)
44 system.physmem.bw_read::cpu3.data 9486130 # Total read bandwidth from this memory (bytes/s)
45 system.physmem.bw_read::total 407903588 # Total read bandwidth from this memory (bytes/s)
46 system.physmem.bw_inst_read::cpu0.inst 205776050 # Instruction read bandwidth from this memory (bytes/s)
47 system.physmem.bw_inst_read::cpu1.inst 45241543 # Instruction read bandwidth from this memory (bytes/s)
48 system.physmem.bw_inst_read::cpu2.inst 1459405 # Instruction read bandwidth from this memory (bytes/s)
49 system.physmem.bw_inst_read::cpu3.inst 1459405 # Instruction read bandwidth from this memory (bytes/s)
50 system.physmem.bw_inst_read::total 253936402 # Instruction read bandwidth from this memory (bytes/s)
51 system.physmem.bw_total::cpu0.inst 205776050 # Total bandwidth to/from this memory (bytes/s)
52 system.physmem.bw_total::cpu0.data 120400880 # Total bandwidth to/from this memory (bytes/s)
53 system.physmem.bw_total::cpu1.inst 45241543 # Total bandwidth to/from this memory (bytes/s)
54 system.physmem.bw_total::cpu1.data 14594046 # Total bandwidth to/from this memory (bytes/s)
55 system.physmem.bw_total::cpu2.inst 1459405 # Total bandwidth to/from this memory (bytes/s)
56 system.physmem.bw_total::cpu2.data 9486130 # Total bandwidth to/from this memory (bytes/s)
57 system.physmem.bw_total::cpu3.inst 1459405 # Total bandwidth to/from this memory (bytes/s)
58 system.physmem.bw_total::cpu3.data 9486130 # Total bandwidth to/from this memory (bytes/s)
59 system.physmem.bw_total::total 407903588 # Total bandwidth to/from this memory (bytes/s)
60 system.membus.throughput 407903588 # Throughput (bytes/s)
61 system.membus.data_through_bus 35776 # Total data (bytes)
62 system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
63 system.l2c.tags.replacements 0 # number of replacements
64 system.l2c.tags.tagsinuse 366.582542 # Cycle average of tags in use
65 system.l2c.tags.total_refs 1220 # Total number of references to valid blocks.
66 system.l2c.tags.sampled_refs 421 # Sample count of references to valid blocks.
67 system.l2c.tags.avg_refs 2.897862 # Average number of references to valid blocks.
68 system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
69 system.l2c.tags.occ_blocks::writebacks 0.966439 # Average occupied blocks per requestor
70 system.l2c.tags.occ_blocks::cpu0.inst 239.426226 # Average occupied blocks per requestor
71 system.l2c.tags.occ_blocks::cpu0.data 55.207595 # Average occupied blocks per requestor
72 system.l2c.tags.occ_blocks::cpu1.inst 59.511852 # Average occupied blocks per requestor
73 system.l2c.tags.occ_blocks::cpu1.data 6.721145 # Average occupied blocks per requestor
74 system.l2c.tags.occ_blocks::cpu2.inst 1.930661 # Average occupied blocks per requestor
75 system.l2c.tags.occ_blocks::cpu2.data 0.935410 # Average occupied blocks per requestor
76 system.l2c.tags.occ_blocks::cpu3.inst 0.977573 # Average occupied blocks per requestor
77 system.l2c.tags.occ_blocks::cpu3.data 0.905640 # Average occupied blocks per requestor
78 system.l2c.tags.occ_percent::writebacks 0.000015 # Average percentage of cache occupancy
79 system.l2c.tags.occ_percent::cpu0.inst 0.003653 # Average percentage of cache occupancy
80 system.l2c.tags.occ_percent::cpu0.data 0.000842 # Average percentage of cache occupancy
81 system.l2c.tags.occ_percent::cpu1.inst 0.000908 # Average percentage of cache occupancy
82 system.l2c.tags.occ_percent::cpu1.data 0.000103 # Average percentage of cache occupancy
83 system.l2c.tags.occ_percent::cpu2.inst 0.000029 # Average percentage of cache occupancy
84 system.l2c.tags.occ_percent::cpu2.data 0.000014 # Average percentage of cache occupancy
85 system.l2c.tags.occ_percent::cpu3.inst 0.000015 # Average percentage of cache occupancy
86 system.l2c.tags.occ_percent::cpu3.data 0.000014 # Average percentage of cache occupancy
87 system.l2c.tags.occ_percent::total 0.005594 # Average percentage of cache occupancy
88 system.l2c.ReadReq_hits::cpu0.inst 185 # number of ReadReq hits
89 system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits
90 system.l2c.ReadReq_hits::cpu1.inst 296 # number of ReadReq hits
91 system.l2c.ReadReq_hits::cpu1.data 3 # number of ReadReq hits
92 system.l2c.ReadReq_hits::cpu2.inst 356 # number of ReadReq hits
93 system.l2c.ReadReq_hits::cpu2.data 9 # number of ReadReq hits
94 system.l2c.ReadReq_hits::cpu3.inst 357 # number of ReadReq hits
95 system.l2c.ReadReq_hits::cpu3.data 9 # number of ReadReq hits
96 system.l2c.ReadReq_hits::total 1220 # number of ReadReq hits
97 system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits
98 system.l2c.Writeback_hits::total 1 # number of Writeback hits
99 system.l2c.UpgradeReq_hits::cpu0.data 2 # number of UpgradeReq hits
100 system.l2c.UpgradeReq_hits::total 2 # number of UpgradeReq hits
101 system.l2c.demand_hits::cpu0.inst 185 # number of demand (read+write) hits
102 system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits
103 system.l2c.demand_hits::cpu1.inst 296 # number of demand (read+write) hits
104 system.l2c.demand_hits::cpu1.data 3 # number of demand (read+write) hits
105 system.l2c.demand_hits::cpu2.inst 356 # number of demand (read+write) hits
106 system.l2c.demand_hits::cpu2.data 9 # number of demand (read+write) hits
107 system.l2c.demand_hits::cpu3.inst 357 # number of demand (read+write) hits
108 system.l2c.demand_hits::cpu3.data 9 # number of demand (read+write) hits
109 system.l2c.demand_hits::total 1220 # number of demand (read+write) hits
110 system.l2c.overall_hits::cpu0.inst 185 # number of overall hits
111 system.l2c.overall_hits::cpu0.data 5 # number of overall hits
112 system.l2c.overall_hits::cpu1.inst 296 # number of overall hits
113 system.l2c.overall_hits::cpu1.data 3 # number of overall hits
114 system.l2c.overall_hits::cpu2.inst 356 # number of overall hits
115 system.l2c.overall_hits::cpu2.data 9 # number of overall hits
116 system.l2c.overall_hits::cpu3.inst 357 # number of overall hits
117 system.l2c.overall_hits::cpu3.data 9 # number of overall hits
118 system.l2c.overall_hits::total 1220 # number of overall hits
119 system.l2c.ReadReq_misses::cpu0.inst 282 # number of ReadReq misses
120 system.l2c.ReadReq_misses::cpu0.data 66 # number of ReadReq misses
121 system.l2c.ReadReq_misses::cpu1.inst 62 # number of ReadReq misses
122 system.l2c.ReadReq_misses::cpu1.data 7 # number of ReadReq misses
123 system.l2c.ReadReq_misses::cpu2.inst 2 # number of ReadReq misses
124 system.l2c.ReadReq_misses::cpu2.data 1 # number of ReadReq misses
125 system.l2c.ReadReq_misses::cpu3.inst 2 # number of ReadReq misses
126 system.l2c.ReadReq_misses::cpu3.data 1 # number of ReadReq misses
127 system.l2c.ReadReq_misses::total 423 # number of ReadReq misses
128 system.l2c.UpgradeReq_misses::cpu0.data 29 # number of UpgradeReq misses
129 system.l2c.UpgradeReq_misses::cpu1.data 18 # number of UpgradeReq misses
130 system.l2c.UpgradeReq_misses::cpu2.data 19 # number of UpgradeReq misses
131 system.l2c.UpgradeReq_misses::cpu3.data 18 # number of UpgradeReq misses
132 system.l2c.UpgradeReq_misses::total 84 # number of UpgradeReq misses
133 system.l2c.ReadExReq_misses::cpu0.data 99 # number of ReadExReq misses
134 system.l2c.ReadExReq_misses::cpu1.data 13 # number of ReadExReq misses
135 system.l2c.ReadExReq_misses::cpu2.data 12 # number of ReadExReq misses
136 system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses
137 system.l2c.ReadExReq_misses::total 136 # number of ReadExReq misses
138 system.l2c.demand_misses::cpu0.inst 282 # number of demand (read+write) misses
139 system.l2c.demand_misses::cpu0.data 165 # number of demand (read+write) misses
140 system.l2c.demand_misses::cpu1.inst 62 # number of demand (read+write) misses
141 system.l2c.demand_misses::cpu1.data 20 # number of demand (read+write) misses
142 system.l2c.demand_misses::cpu2.inst 2 # number of demand (read+write) misses
143 system.l2c.demand_misses::cpu2.data 13 # number of demand (read+write) misses
144 system.l2c.demand_misses::cpu3.inst 2 # number of demand (read+write) misses
145 system.l2c.demand_misses::cpu3.data 13 # number of demand (read+write) misses
146 system.l2c.demand_misses::total 559 # number of demand (read+write) misses
147 system.l2c.overall_misses::cpu0.inst 282 # number of overall misses
148 system.l2c.overall_misses::cpu0.data 165 # number of overall misses
149 system.l2c.overall_misses::cpu1.inst 62 # number of overall misses
150 system.l2c.overall_misses::cpu1.data 20 # number of overall misses
151 system.l2c.overall_misses::cpu2.inst 2 # number of overall misses
152 system.l2c.overall_misses::cpu2.data 13 # number of overall misses
153 system.l2c.overall_misses::cpu3.inst 2 # number of overall misses
154 system.l2c.overall_misses::cpu3.data 13 # number of overall misses
155 system.l2c.overall_misses::total 559 # number of overall misses
156 system.l2c.ReadReq_accesses::cpu0.inst 467 # number of ReadReq accesses(hits+misses)
157 system.l2c.ReadReq_accesses::cpu0.data 71 # number of ReadReq accesses(hits+misses)
158 system.l2c.ReadReq_accesses::cpu1.inst 358 # number of ReadReq accesses(hits+misses)
159 system.l2c.ReadReq_accesses::cpu1.data 10 # number of ReadReq accesses(hits+misses)
160 system.l2c.ReadReq_accesses::cpu2.inst 358 # number of ReadReq accesses(hits+misses)
161 system.l2c.ReadReq_accesses::cpu2.data 10 # number of ReadReq accesses(hits+misses)
162 system.l2c.ReadReq_accesses::cpu3.inst 359 # number of ReadReq accesses(hits+misses)
163 system.l2c.ReadReq_accesses::cpu3.data 10 # number of ReadReq accesses(hits+misses)
164 system.l2c.ReadReq_accesses::total 1643 # number of ReadReq accesses(hits+misses)
165 system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses)
166 system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses)
167 system.l2c.UpgradeReq_accesses::cpu0.data 31 # number of UpgradeReq accesses(hits+misses)
168 system.l2c.UpgradeReq_accesses::cpu1.data 18 # number of UpgradeReq accesses(hits+misses)
169 system.l2c.UpgradeReq_accesses::cpu2.data 19 # number of UpgradeReq accesses(hits+misses)
170 system.l2c.UpgradeReq_accesses::cpu3.data 18 # number of UpgradeReq accesses(hits+misses)
171 system.l2c.UpgradeReq_accesses::total 86 # number of UpgradeReq accesses(hits+misses)
172 system.l2c.ReadExReq_accesses::cpu0.data 99 # number of ReadExReq accesses(hits+misses)
173 system.l2c.ReadExReq_accesses::cpu1.data 13 # number of ReadExReq accesses(hits+misses)
174 system.l2c.ReadExReq_accesses::cpu2.data 12 # number of ReadExReq accesses(hits+misses)
175 system.l2c.ReadExReq_accesses::cpu3.data 12 # number of ReadExReq accesses(hits+misses)
176 system.l2c.ReadExReq_accesses::total 136 # number of ReadExReq accesses(hits+misses)
177 system.l2c.demand_accesses::cpu0.inst 467 # number of demand (read+write) accesses
178 system.l2c.demand_accesses::cpu0.data 170 # number of demand (read+write) accesses
179 system.l2c.demand_accesses::cpu1.inst 358 # number of demand (read+write) accesses
180 system.l2c.demand_accesses::cpu1.data 23 # number of demand (read+write) accesses
181 system.l2c.demand_accesses::cpu2.inst 358 # number of demand (read+write) accesses
182 system.l2c.demand_accesses::cpu2.data 22 # number of demand (read+write) accesses
183 system.l2c.demand_accesses::cpu3.inst 359 # number of demand (read+write) accesses
184 system.l2c.demand_accesses::cpu3.data 22 # number of demand (read+write) accesses
185 system.l2c.demand_accesses::total 1779 # number of demand (read+write) accesses
186 system.l2c.overall_accesses::cpu0.inst 467 # number of overall (read+write) accesses
187 system.l2c.overall_accesses::cpu0.data 170 # number of overall (read+write) accesses
188 system.l2c.overall_accesses::cpu1.inst 358 # number of overall (read+write) accesses
189 system.l2c.overall_accesses::cpu1.data 23 # number of overall (read+write) accesses
190 system.l2c.overall_accesses::cpu2.inst 358 # number of overall (read+write) accesses
191 system.l2c.overall_accesses::cpu2.data 22 # number of overall (read+write) accesses
192 system.l2c.overall_accesses::cpu3.inst 359 # number of overall (read+write) accesses
193 system.l2c.overall_accesses::cpu3.data 22 # number of overall (read+write) accesses
194 system.l2c.overall_accesses::total 1779 # number of overall (read+write) accesses
195 system.l2c.ReadReq_miss_rate::cpu0.inst 0.603854 # miss rate for ReadReq accesses
196 system.l2c.ReadReq_miss_rate::cpu0.data 0.929577 # miss rate for ReadReq accesses
197 system.l2c.ReadReq_miss_rate::cpu1.inst 0.173184 # miss rate for ReadReq accesses
198 system.l2c.ReadReq_miss_rate::cpu1.data 0.700000 # miss rate for ReadReq accesses
199 system.l2c.ReadReq_miss_rate::cpu2.inst 0.005587 # miss rate for ReadReq accesses
200 system.l2c.ReadReq_miss_rate::cpu2.data 0.100000 # miss rate for ReadReq accesses
201 system.l2c.ReadReq_miss_rate::cpu3.inst 0.005571 # miss rate for ReadReq accesses
202 system.l2c.ReadReq_miss_rate::cpu3.data 0.100000 # miss rate for ReadReq accesses
203 system.l2c.ReadReq_miss_rate::total 0.257456 # miss rate for ReadReq accesses
204 system.l2c.UpgradeReq_miss_rate::cpu0.data 0.935484 # miss rate for UpgradeReq accesses
205 system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses
206 system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses
207 system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses
208 system.l2c.UpgradeReq_miss_rate::total 0.976744 # miss rate for UpgradeReq accesses
209 system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses
210 system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses
211 system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses
212 system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses
213 system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
214 system.l2c.demand_miss_rate::cpu0.inst 0.603854 # miss rate for demand accesses
215 system.l2c.demand_miss_rate::cpu0.data 0.970588 # miss rate for demand accesses
216 system.l2c.demand_miss_rate::cpu1.inst 0.173184 # miss rate for demand accesses
217 system.l2c.demand_miss_rate::cpu1.data 0.869565 # miss rate for demand accesses
218 system.l2c.demand_miss_rate::cpu2.inst 0.005587 # miss rate for demand accesses
219 system.l2c.demand_miss_rate::cpu2.data 0.590909 # miss rate for demand accesses
220 system.l2c.demand_miss_rate::cpu3.inst 0.005571 # miss rate for demand accesses
221 system.l2c.demand_miss_rate::cpu3.data 0.590909 # miss rate for demand accesses
222 system.l2c.demand_miss_rate::total 0.314221 # miss rate for demand accesses
223 system.l2c.overall_miss_rate::cpu0.inst 0.603854 # miss rate for overall accesses
224 system.l2c.overall_miss_rate::cpu0.data 0.970588 # miss rate for overall accesses
225 system.l2c.overall_miss_rate::cpu1.inst 0.173184 # miss rate for overall accesses
226 system.l2c.overall_miss_rate::cpu1.data 0.869565 # miss rate for overall accesses
227 system.l2c.overall_miss_rate::cpu2.inst 0.005587 # miss rate for overall accesses
228 system.l2c.overall_miss_rate::cpu2.data 0.590909 # miss rate for overall accesses
229 system.l2c.overall_miss_rate::cpu3.inst 0.005571 # miss rate for overall accesses
230 system.l2c.overall_miss_rate::cpu3.data 0.590909 # miss rate for overall accesses
231 system.l2c.overall_miss_rate::total 0.314221 # miss rate for overall accesses
232 system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
233 system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
234 system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
235 system.l2c.blocked::no_targets 0 # number of cycles access was blocked
236 system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
237 system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
238 system.l2c.fast_writes 0 # number of fast writes performed
239 system.l2c.cache_copies 0 # number of cache copies performed
240 system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
241 system.toL2Bus.throughput 1893577480 # Throughput (bytes/s)
242 system.toL2Bus.data_through_bus 166080 # Total data (bytes)
243 system.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
244 system.cpu0.workload.num_syscalls 89 # Number of system calls
245 system.cpu0.numCycles 175415 # number of cpu cycles simulated
246 system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
247 system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
248 system.cpu0.committedInsts 175326 # Number of instructions committed
249 system.cpu0.committedOps 175326 # Number of ops (including micro ops) committed
250 system.cpu0.num_int_alu_accesses 120376 # Number of integer alu accesses
251 system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses
252 system.cpu0.num_func_calls 390 # number of times a function call or return occured
253 system.cpu0.num_conditional_control_insts 28824 # number of instructions that are conditional controls
254 system.cpu0.num_int_insts 120376 # number of integer instructions
255 system.cpu0.num_fp_insts 0 # number of float instructions
256 system.cpu0.num_int_register_reads 349286 # number of times the integer registers were read
257 system.cpu0.num_int_register_writes 121983 # number of times the integer registers were written
258 system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read
259 system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written
260 system.cpu0.num_mem_refs 82397 # number of memory refs
261 system.cpu0.num_load_insts 54591 # Number of load instructions
262 system.cpu0.num_store_insts 27806 # Number of store instructions
263 system.cpu0.num_idle_cycles 0 # Number of idle cycles
264 system.cpu0.num_busy_cycles 175415 # Number of busy cycles
265 system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles
266 system.cpu0.idle_fraction 0 # Percentage of idle cycles
267 system.cpu0.icache.tags.replacements 215 # number of replacements
268 system.cpu0.icache.tags.tagsinuse 222.772698 # Cycle average of tags in use
269 system.cpu0.icache.tags.total_refs 174921 # Total number of references to valid blocks.
270 system.cpu0.icache.tags.sampled_refs 467 # Sample count of references to valid blocks.
271 system.cpu0.icache.tags.avg_refs 374.563169 # Average number of references to valid blocks.
272 system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
273 system.cpu0.icache.tags.occ_blocks::cpu0.inst 222.772698 # Average occupied blocks per requestor
274 system.cpu0.icache.tags.occ_percent::cpu0.inst 0.435103 # Average percentage of cache occupancy
275 system.cpu0.icache.tags.occ_percent::total 0.435103 # Average percentage of cache occupancy
276 system.cpu0.icache.ReadReq_hits::cpu0.inst 174921 # number of ReadReq hits
277 system.cpu0.icache.ReadReq_hits::total 174921 # number of ReadReq hits
278 system.cpu0.icache.demand_hits::cpu0.inst 174921 # number of demand (read+write) hits
279 system.cpu0.icache.demand_hits::total 174921 # number of demand (read+write) hits
280 system.cpu0.icache.overall_hits::cpu0.inst 174921 # number of overall hits
281 system.cpu0.icache.overall_hits::total 174921 # number of overall hits
282 system.cpu0.icache.ReadReq_misses::cpu0.inst 467 # number of ReadReq misses
283 system.cpu0.icache.ReadReq_misses::total 467 # number of ReadReq misses
284 system.cpu0.icache.demand_misses::cpu0.inst 467 # number of demand (read+write) misses
285 system.cpu0.icache.demand_misses::total 467 # number of demand (read+write) misses
286 system.cpu0.icache.overall_misses::cpu0.inst 467 # number of overall misses
287 system.cpu0.icache.overall_misses::total 467 # number of overall misses
288 system.cpu0.icache.ReadReq_accesses::cpu0.inst 175388 # number of ReadReq accesses(hits+misses)
289 system.cpu0.icache.ReadReq_accesses::total 175388 # number of ReadReq accesses(hits+misses)
290 system.cpu0.icache.demand_accesses::cpu0.inst 175388 # number of demand (read+write) accesses
291 system.cpu0.icache.demand_accesses::total 175388 # number of demand (read+write) accesses
292 system.cpu0.icache.overall_accesses::cpu0.inst 175388 # number of overall (read+write) accesses
293 system.cpu0.icache.overall_accesses::total 175388 # number of overall (read+write) accesses
294 system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002663 # miss rate for ReadReq accesses
295 system.cpu0.icache.ReadReq_miss_rate::total 0.002663 # miss rate for ReadReq accesses
296 system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002663 # miss rate for demand accesses
297 system.cpu0.icache.demand_miss_rate::total 0.002663 # miss rate for demand accesses
298 system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002663 # miss rate for overall accesses
299 system.cpu0.icache.overall_miss_rate::total 0.002663 # miss rate for overall accesses
300 system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
301 system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
302 system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
303 system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
304 system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
305 system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
306 system.cpu0.icache.fast_writes 0 # number of fast writes performed
307 system.cpu0.icache.cache_copies 0 # number of cache copies performed
308 system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
309 system.cpu0.dcache.tags.replacements 2 # number of replacements
310 system.cpu0.dcache.tags.tagsinuse 150.745494 # Cycle average of tags in use
311 system.cpu0.dcache.tags.total_refs 81883 # Total number of references to valid blocks.
312 system.cpu0.dcache.tags.sampled_refs 167 # Sample count of references to valid blocks.
313 system.cpu0.dcache.tags.avg_refs 490.317365 # Average number of references to valid blocks.
314 system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
315 system.cpu0.dcache.tags.occ_blocks::cpu0.data 150.745494 # Average occupied blocks per requestor
316 system.cpu0.dcache.tags.occ_percent::cpu0.data 0.294425 # Average percentage of cache occupancy
317 system.cpu0.dcache.tags.occ_percent::total 0.294425 # Average percentage of cache occupancy
318 system.cpu0.dcache.ReadReq_hits::cpu0.data 54430 # number of ReadReq hits
319 system.cpu0.dcache.ReadReq_hits::total 54430 # number of ReadReq hits
320 system.cpu0.dcache.WriteReq_hits::cpu0.data 27578 # number of WriteReq hits
321 system.cpu0.dcache.WriteReq_hits::total 27578 # number of WriteReq hits
322 system.cpu0.dcache.SwapReq_hits::cpu0.data 15 # number of SwapReq hits
323 system.cpu0.dcache.SwapReq_hits::total 15 # number of SwapReq hits
324 system.cpu0.dcache.demand_hits::cpu0.data 82008 # number of demand (read+write) hits
325 system.cpu0.dcache.demand_hits::total 82008 # number of demand (read+write) hits
326 system.cpu0.dcache.overall_hits::cpu0.data 82008 # number of overall hits
327 system.cpu0.dcache.overall_hits::total 82008 # number of overall hits
328 system.cpu0.dcache.ReadReq_misses::cpu0.data 151 # number of ReadReq misses
329 system.cpu0.dcache.ReadReq_misses::total 151 # number of ReadReq misses
330 system.cpu0.dcache.WriteReq_misses::cpu0.data 177 # number of WriteReq misses
331 system.cpu0.dcache.WriteReq_misses::total 177 # number of WriteReq misses
332 system.cpu0.dcache.SwapReq_misses::cpu0.data 27 # number of SwapReq misses
333 system.cpu0.dcache.SwapReq_misses::total 27 # number of SwapReq misses
334 system.cpu0.dcache.demand_misses::cpu0.data 328 # number of demand (read+write) misses
335 system.cpu0.dcache.demand_misses::total 328 # number of demand (read+write) misses
336 system.cpu0.dcache.overall_misses::cpu0.data 328 # number of overall misses
337 system.cpu0.dcache.overall_misses::total 328 # number of overall misses
338 system.cpu0.dcache.ReadReq_accesses::cpu0.data 54581 # number of ReadReq accesses(hits+misses)
339 system.cpu0.dcache.ReadReq_accesses::total 54581 # number of ReadReq accesses(hits+misses)
340 system.cpu0.dcache.WriteReq_accesses::cpu0.data 27755 # number of WriteReq accesses(hits+misses)
341 system.cpu0.dcache.WriteReq_accesses::total 27755 # number of WriteReq accesses(hits+misses)
342 system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses)
343 system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses)
344 system.cpu0.dcache.demand_accesses::cpu0.data 82336 # number of demand (read+write) accesses
345 system.cpu0.dcache.demand_accesses::total 82336 # number of demand (read+write) accesses
346 system.cpu0.dcache.overall_accesses::cpu0.data 82336 # number of overall (read+write) accesses
347 system.cpu0.dcache.overall_accesses::total 82336 # number of overall (read+write) accesses
348 system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.002767 # miss rate for ReadReq accesses
349 system.cpu0.dcache.ReadReq_miss_rate::total 0.002767 # miss rate for ReadReq accesses
350 system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.006377 # miss rate for WriteReq accesses
351 system.cpu0.dcache.WriteReq_miss_rate::total 0.006377 # miss rate for WriteReq accesses
352 system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.642857 # miss rate for SwapReq accesses
353 system.cpu0.dcache.SwapReq_miss_rate::total 0.642857 # miss rate for SwapReq accesses
354 system.cpu0.dcache.demand_miss_rate::cpu0.data 0.003984 # miss rate for demand accesses
355 system.cpu0.dcache.demand_miss_rate::total 0.003984 # miss rate for demand accesses
356 system.cpu0.dcache.overall_miss_rate::cpu0.data 0.003984 # miss rate for overall accesses
357 system.cpu0.dcache.overall_miss_rate::total 0.003984 # miss rate for overall accesses
358 system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
359 system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
360 system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
361 system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
362 system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
363 system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
364 system.cpu0.dcache.fast_writes 0 # number of fast writes performed
365 system.cpu0.dcache.cache_copies 0 # number of cache copies performed
366 system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks
367 system.cpu0.dcache.writebacks::total 1 # number of writebacks
368 system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
369 system.cpu1.numCycles 173295 # number of cpu cycles simulated
370 system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
371 system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
372 system.cpu1.committedInsts 167398 # Number of instructions committed
373 system.cpu1.committedOps 167398 # Number of ops (including micro ops) committed
374 system.cpu1.num_int_alu_accesses 109926 # Number of integer alu accesses
375 system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses
376 system.cpu1.num_func_calls 633 # number of times a function call or return occured
377 system.cpu1.num_conditional_control_insts 32743 # number of instructions that are conditional controls
378 system.cpu1.num_int_insts 109926 # number of integer instructions
379 system.cpu1.num_fp_insts 0 # number of float instructions
380 system.cpu1.num_int_register_reads 270038 # number of times the integer registers were read
381 system.cpu1.num_int_register_writes 100721 # number of times the integer registers were written
382 system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read
383 system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written
384 system.cpu1.num_mem_refs 53394 # number of memory refs
385 system.cpu1.num_load_insts 40652 # Number of load instructions
386 system.cpu1.num_store_insts 12742 # Number of store instructions
387 system.cpu1.num_idle_cycles 7873.724337 # Number of idle cycles
388 system.cpu1.num_busy_cycles 165421.275663 # Number of busy cycles
389 system.cpu1.not_idle_fraction 0.954565 # Percentage of non-idle cycles
390 system.cpu1.idle_fraction 0.045435 # Percentage of idle cycles
391 system.cpu1.icache.tags.replacements 278 # number of replacements
392 system.cpu1.icache.tags.tagsinuse 76.751702 # Cycle average of tags in use
393 system.cpu1.icache.tags.total_refs 167072 # Total number of references to valid blocks.
394 system.cpu1.icache.tags.sampled_refs 358 # Sample count of references to valid blocks.
395 system.cpu1.icache.tags.avg_refs 466.681564 # Average number of references to valid blocks.
396 system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
397 system.cpu1.icache.tags.occ_blocks::cpu1.inst 76.751702 # Average occupied blocks per requestor
398 system.cpu1.icache.tags.occ_percent::cpu1.inst 0.149906 # Average percentage of cache occupancy
399 system.cpu1.icache.tags.occ_percent::total 0.149906 # Average percentage of cache occupancy
400 system.cpu1.icache.ReadReq_hits::cpu1.inst 167072 # number of ReadReq hits
401 system.cpu1.icache.ReadReq_hits::total 167072 # number of ReadReq hits
402 system.cpu1.icache.demand_hits::cpu1.inst 167072 # number of demand (read+write) hits
403 system.cpu1.icache.demand_hits::total 167072 # number of demand (read+write) hits
404 system.cpu1.icache.overall_hits::cpu1.inst 167072 # number of overall hits
405 system.cpu1.icache.overall_hits::total 167072 # number of overall hits
406 system.cpu1.icache.ReadReq_misses::cpu1.inst 358 # number of ReadReq misses
407 system.cpu1.icache.ReadReq_misses::total 358 # number of ReadReq misses
408 system.cpu1.icache.demand_misses::cpu1.inst 358 # number of demand (read+write) misses
409 system.cpu1.icache.demand_misses::total 358 # number of demand (read+write) misses
410 system.cpu1.icache.overall_misses::cpu1.inst 358 # number of overall misses
411 system.cpu1.icache.overall_misses::total 358 # number of overall misses
412 system.cpu1.icache.ReadReq_accesses::cpu1.inst 167430 # number of ReadReq accesses(hits+misses)
413 system.cpu1.icache.ReadReq_accesses::total 167430 # number of ReadReq accesses(hits+misses)
414 system.cpu1.icache.demand_accesses::cpu1.inst 167430 # number of demand (read+write) accesses
415 system.cpu1.icache.demand_accesses::total 167430 # number of demand (read+write) accesses
416 system.cpu1.icache.overall_accesses::cpu1.inst 167430 # number of overall (read+write) accesses
417 system.cpu1.icache.overall_accesses::total 167430 # number of overall (read+write) accesses
418 system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002138 # miss rate for ReadReq accesses
419 system.cpu1.icache.ReadReq_miss_rate::total 0.002138 # miss rate for ReadReq accesses
420 system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002138 # miss rate for demand accesses
421 system.cpu1.icache.demand_miss_rate::total 0.002138 # miss rate for demand accesses
422 system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002138 # miss rate for overall accesses
423 system.cpu1.icache.overall_miss_rate::total 0.002138 # miss rate for overall accesses
424 system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
425 system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
426 system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
427 system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
428 system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
429 system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
430 system.cpu1.icache.fast_writes 0 # number of fast writes performed
431 system.cpu1.icache.cache_copies 0 # number of cache copies performed
432 system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
433 system.cpu1.dcache.tags.replacements 0 # number of replacements
434 system.cpu1.dcache.tags.tagsinuse 30.316999 # Cycle average of tags in use
435 system.cpu1.dcache.tags.total_refs 26731 # Total number of references to valid blocks.
436 system.cpu1.dcache.tags.sampled_refs 26 # Sample count of references to valid blocks.
437 system.cpu1.dcache.tags.avg_refs 1028.115385 # Average number of references to valid blocks.
438 system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
439 system.cpu1.dcache.tags.occ_blocks::cpu1.data 30.316999 # Average occupied blocks per requestor
440 system.cpu1.dcache.tags.occ_percent::cpu1.data 0.059213 # Average percentage of cache occupancy
441 system.cpu1.dcache.tags.occ_percent::total 0.059213 # Average percentage of cache occupancy
442 system.cpu1.dcache.ReadReq_hits::cpu1.data 40470 # number of ReadReq hits
443 system.cpu1.dcache.ReadReq_hits::total 40470 # number of ReadReq hits
444 system.cpu1.dcache.WriteReq_hits::cpu1.data 12563 # number of WriteReq hits
445 system.cpu1.dcache.WriteReq_hits::total 12563 # number of WriteReq hits
446 system.cpu1.dcache.SwapReq_hits::cpu1.data 14 # number of SwapReq hits
447 system.cpu1.dcache.SwapReq_hits::total 14 # number of SwapReq hits
448 system.cpu1.dcache.demand_hits::cpu1.data 53033 # number of demand (read+write) hits
449 system.cpu1.dcache.demand_hits::total 53033 # number of demand (read+write) hits
450 system.cpu1.dcache.overall_hits::cpu1.data 53033 # number of overall hits
451 system.cpu1.dcache.overall_hits::total 53033 # number of overall hits
452 system.cpu1.dcache.ReadReq_misses::cpu1.data 174 # number of ReadReq misses
453 system.cpu1.dcache.ReadReq_misses::total 174 # number of ReadReq misses
454 system.cpu1.dcache.WriteReq_misses::cpu1.data 106 # number of WriteReq misses
455 system.cpu1.dcache.WriteReq_misses::total 106 # number of WriteReq misses
456 system.cpu1.dcache.SwapReq_misses::cpu1.data 57 # number of SwapReq misses
457 system.cpu1.dcache.SwapReq_misses::total 57 # number of SwapReq misses
458 system.cpu1.dcache.demand_misses::cpu1.data 280 # number of demand (read+write) misses
459 system.cpu1.dcache.demand_misses::total 280 # number of demand (read+write) misses
460 system.cpu1.dcache.overall_misses::cpu1.data 280 # number of overall misses
461 system.cpu1.dcache.overall_misses::total 280 # number of overall misses
462 system.cpu1.dcache.ReadReq_accesses::cpu1.data 40644 # number of ReadReq accesses(hits+misses)
463 system.cpu1.dcache.ReadReq_accesses::total 40644 # number of ReadReq accesses(hits+misses)
464 system.cpu1.dcache.WriteReq_accesses::cpu1.data 12669 # number of WriteReq accesses(hits+misses)
465 system.cpu1.dcache.WriteReq_accesses::total 12669 # number of WriteReq accesses(hits+misses)
466 system.cpu1.dcache.SwapReq_accesses::cpu1.data 71 # number of SwapReq accesses(hits+misses)
467 system.cpu1.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses)
468 system.cpu1.dcache.demand_accesses::cpu1.data 53313 # number of demand (read+write) accesses
469 system.cpu1.dcache.demand_accesses::total 53313 # number of demand (read+write) accesses
470 system.cpu1.dcache.overall_accesses::cpu1.data 53313 # number of overall (read+write) accesses
471 system.cpu1.dcache.overall_accesses::total 53313 # number of overall (read+write) accesses
472 system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.004281 # miss rate for ReadReq accesses
473 system.cpu1.dcache.ReadReq_miss_rate::total 0.004281 # miss rate for ReadReq accesses
474 system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.008367 # miss rate for WriteReq accesses
475 system.cpu1.dcache.WriteReq_miss_rate::total 0.008367 # miss rate for WriteReq accesses
476 system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.802817 # miss rate for SwapReq accesses
477 system.cpu1.dcache.SwapReq_miss_rate::total 0.802817 # miss rate for SwapReq accesses
478 system.cpu1.dcache.demand_miss_rate::cpu1.data 0.005252 # miss rate for demand accesses
479 system.cpu1.dcache.demand_miss_rate::total 0.005252 # miss rate for demand accesses
480 system.cpu1.dcache.overall_miss_rate::cpu1.data 0.005252 # miss rate for overall accesses
481 system.cpu1.dcache.overall_miss_rate::total 0.005252 # miss rate for overall accesses
482 system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
483 system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
484 system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
485 system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
486 system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
487 system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
488 system.cpu1.dcache.fast_writes 0 # number of fast writes performed
489 system.cpu1.dcache.cache_copies 0 # number of cache copies performed
490 system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
491 system.cpu2.numCycles 173295 # number of cpu cycles simulated
492 system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
493 system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
494 system.cpu2.committedInsts 167334 # Number of instructions committed
495 system.cpu2.committedOps 167334 # Number of ops (including micro ops) committed
496 system.cpu2.num_int_alu_accesses 113333 # Number of integer alu accesses
497 system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses
498 system.cpu2.num_func_calls 633 # number of times a function call or return occured
499 system.cpu2.num_conditional_control_insts 31007 # number of instructions that are conditional controls
500 system.cpu2.num_int_insts 113333 # number of integer instructions
501 system.cpu2.num_fp_insts 0 # number of float instructions
502 system.cpu2.num_int_register_reads 290613 # number of times the integer registers were read
503 system.cpu2.num_int_register_writes 109308 # number of times the integer registers were written
504 system.cpu2.num_fp_register_reads 0 # number of times the floating registers were read
505 system.cpu2.num_fp_register_writes 0 # number of times the floating registers were written
506 system.cpu2.num_mem_refs 58537 # number of memory refs
507 system.cpu2.num_load_insts 42362 # Number of load instructions
508 system.cpu2.num_store_insts 16175 # Number of store instructions
509 system.cpu2.num_idle_cycles 7936.951217 # Number of idle cycles
510 system.cpu2.num_busy_cycles 165358.048783 # Number of busy cycles
511 system.cpu2.not_idle_fraction 0.954200 # Percentage of non-idle cycles
512 system.cpu2.idle_fraction 0.045800 # Percentage of idle cycles
513 system.cpu2.icache.tags.replacements 278 # number of replacements
514 system.cpu2.icache.tags.tagsinuse 74.781015 # Cycle average of tags in use
515 system.cpu2.icache.tags.total_refs 167008 # Total number of references to valid blocks.
516 system.cpu2.icache.tags.sampled_refs 358 # Sample count of references to valid blocks.
517 system.cpu2.icache.tags.avg_refs 466.502793 # Average number of references to valid blocks.
518 system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
519 system.cpu2.icache.tags.occ_blocks::cpu2.inst 74.781015 # Average occupied blocks per requestor
520 system.cpu2.icache.tags.occ_percent::cpu2.inst 0.146057 # Average percentage of cache occupancy
521 system.cpu2.icache.tags.occ_percent::total 0.146057 # Average percentage of cache occupancy
522 system.cpu2.icache.ReadReq_hits::cpu2.inst 167008 # number of ReadReq hits
523 system.cpu2.icache.ReadReq_hits::total 167008 # number of ReadReq hits
524 system.cpu2.icache.demand_hits::cpu2.inst 167008 # number of demand (read+write) hits
525 system.cpu2.icache.demand_hits::total 167008 # number of demand (read+write) hits
526 system.cpu2.icache.overall_hits::cpu2.inst 167008 # number of overall hits
527 system.cpu2.icache.overall_hits::total 167008 # number of overall hits
528 system.cpu2.icache.ReadReq_misses::cpu2.inst 358 # number of ReadReq misses
529 system.cpu2.icache.ReadReq_misses::total 358 # number of ReadReq misses
530 system.cpu2.icache.demand_misses::cpu2.inst 358 # number of demand (read+write) misses
531 system.cpu2.icache.demand_misses::total 358 # number of demand (read+write) misses
532 system.cpu2.icache.overall_misses::cpu2.inst 358 # number of overall misses
533 system.cpu2.icache.overall_misses::total 358 # number of overall misses
534 system.cpu2.icache.ReadReq_accesses::cpu2.inst 167366 # number of ReadReq accesses(hits+misses)
535 system.cpu2.icache.ReadReq_accesses::total 167366 # number of ReadReq accesses(hits+misses)
536 system.cpu2.icache.demand_accesses::cpu2.inst 167366 # number of demand (read+write) accesses
537 system.cpu2.icache.demand_accesses::total 167366 # number of demand (read+write) accesses
538 system.cpu2.icache.overall_accesses::cpu2.inst 167366 # number of overall (read+write) accesses
539 system.cpu2.icache.overall_accesses::total 167366 # number of overall (read+write) accesses
540 system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002139 # miss rate for ReadReq accesses
541 system.cpu2.icache.ReadReq_miss_rate::total 0.002139 # miss rate for ReadReq accesses
542 system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002139 # miss rate for demand accesses
543 system.cpu2.icache.demand_miss_rate::total 0.002139 # miss rate for demand accesses
544 system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002139 # miss rate for overall accesses
545 system.cpu2.icache.overall_miss_rate::total 0.002139 # miss rate for overall accesses
546 system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
547 system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
548 system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked
549 system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked
550 system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
551 system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
552 system.cpu2.icache.fast_writes 0 # number of fast writes performed
553 system.cpu2.icache.cache_copies 0 # number of cache copies performed
554 system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate
555 system.cpu2.dcache.tags.replacements 0 # number of replacements
556 system.cpu2.dcache.tags.tagsinuse 29.605505 # Cycle average of tags in use
557 system.cpu2.dcache.tags.total_refs 33613 # Total number of references to valid blocks.
558 system.cpu2.dcache.tags.sampled_refs 26 # Sample count of references to valid blocks.
559 system.cpu2.dcache.tags.avg_refs 1292.807692 # Average number of references to valid blocks.
560 system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
561 system.cpu2.dcache.tags.occ_blocks::cpu2.data 29.605505 # Average occupied blocks per requestor
562 system.cpu2.dcache.tags.occ_percent::cpu2.data 0.057823 # Average percentage of cache occupancy
563 system.cpu2.dcache.tags.occ_percent::total 0.057823 # Average percentage of cache occupancy
564 system.cpu2.dcache.ReadReq_hits::cpu2.data 42194 # number of ReadReq hits
565 system.cpu2.dcache.ReadReq_hits::total 42194 # number of ReadReq hits
566 system.cpu2.dcache.WriteReq_hits::cpu2.data 15998 # number of WriteReq hits
567 system.cpu2.dcache.WriteReq_hits::total 15998 # number of WriteReq hits
568 system.cpu2.dcache.SwapReq_hits::cpu2.data 11 # number of SwapReq hits
569 system.cpu2.dcache.SwapReq_hits::total 11 # number of SwapReq hits
570 system.cpu2.dcache.demand_hits::cpu2.data 58192 # number of demand (read+write) hits
571 system.cpu2.dcache.demand_hits::total 58192 # number of demand (read+write) hits
572 system.cpu2.dcache.overall_hits::cpu2.data 58192 # number of overall hits
573 system.cpu2.dcache.overall_hits::total 58192 # number of overall hits
574 system.cpu2.dcache.ReadReq_misses::cpu2.data 160 # number of ReadReq misses
575 system.cpu2.dcache.ReadReq_misses::total 160 # number of ReadReq misses
576 system.cpu2.dcache.WriteReq_misses::cpu2.data 109 # number of WriteReq misses
577 system.cpu2.dcache.WriteReq_misses::total 109 # number of WriteReq misses
578 system.cpu2.dcache.SwapReq_misses::cpu2.data 55 # number of SwapReq misses
579 system.cpu2.dcache.SwapReq_misses::total 55 # number of SwapReq misses
580 system.cpu2.dcache.demand_misses::cpu2.data 269 # number of demand (read+write) misses
581 system.cpu2.dcache.demand_misses::total 269 # number of demand (read+write) misses
582 system.cpu2.dcache.overall_misses::cpu2.data 269 # number of overall misses
583 system.cpu2.dcache.overall_misses::total 269 # number of overall misses
584 system.cpu2.dcache.ReadReq_accesses::cpu2.data 42354 # number of ReadReq accesses(hits+misses)
585 system.cpu2.dcache.ReadReq_accesses::total 42354 # number of ReadReq accesses(hits+misses)
586 system.cpu2.dcache.WriteReq_accesses::cpu2.data 16107 # number of WriteReq accesses(hits+misses)
587 system.cpu2.dcache.WriteReq_accesses::total 16107 # number of WriteReq accesses(hits+misses)
588 system.cpu2.dcache.SwapReq_accesses::cpu2.data 66 # number of SwapReq accesses(hits+misses)
589 system.cpu2.dcache.SwapReq_accesses::total 66 # number of SwapReq accesses(hits+misses)
590 system.cpu2.dcache.demand_accesses::cpu2.data 58461 # number of demand (read+write) accesses
591 system.cpu2.dcache.demand_accesses::total 58461 # number of demand (read+write) accesses
592 system.cpu2.dcache.overall_accesses::cpu2.data 58461 # number of overall (read+write) accesses
593 system.cpu2.dcache.overall_accesses::total 58461 # number of overall (read+write) accesses
594 system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003778 # miss rate for ReadReq accesses
595 system.cpu2.dcache.ReadReq_miss_rate::total 0.003778 # miss rate for ReadReq accesses
596 system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.006767 # miss rate for WriteReq accesses
597 system.cpu2.dcache.WriteReq_miss_rate::total 0.006767 # miss rate for WriteReq accesses
598 system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.833333 # miss rate for SwapReq accesses
599 system.cpu2.dcache.SwapReq_miss_rate::total 0.833333 # miss rate for SwapReq accesses
600 system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004601 # miss rate for demand accesses
601 system.cpu2.dcache.demand_miss_rate::total 0.004601 # miss rate for demand accesses
602 system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004601 # miss rate for overall accesses
603 system.cpu2.dcache.overall_miss_rate::total 0.004601 # miss rate for overall accesses
604 system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
605 system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
606 system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
607 system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked
608 system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
609 system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
610 system.cpu2.dcache.fast_writes 0 # number of fast writes performed
611 system.cpu2.dcache.cache_copies 0 # number of cache copies performed
612 system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
613 system.cpu3.numCycles 173294 # number of cpu cycles simulated
614 system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
615 system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed
616 system.cpu3.committedInsts 167269 # Number of instructions committed
617 system.cpu3.committedOps 167269 # Number of ops (including micro ops) committed
618 system.cpu3.num_int_alu_accesses 111554 # Number of integer alu accesses
619 system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses
620 system.cpu3.num_func_calls 633 # number of times a function call or return occured
621 system.cpu3.num_conditional_control_insts 31865 # number of instructions that are conditional controls
622 system.cpu3.num_int_insts 111554 # number of integer instructions
623 system.cpu3.num_fp_insts 0 # number of float instructions
624 system.cpu3.num_int_register_reads 280060 # number of times the integer registers were read
625 system.cpu3.num_int_register_writes 104916 # number of times the integer registers were written
626 system.cpu3.num_fp_register_reads 0 # number of times the floating registers were read
627 system.cpu3.num_fp_register_writes 0 # number of times the floating registers were written
628 system.cpu3.num_mem_refs 55900 # number of memory refs
629 system.cpu3.num_load_insts 41466 # Number of load instructions
630 system.cpu3.num_store_insts 14434 # Number of store instructions
631 system.cpu3.num_idle_cycles 8001.119846 # Number of idle cycles
632 system.cpu3.num_busy_cycles 165292.880154 # Number of busy cycles
633 system.cpu3.not_idle_fraction 0.953829 # Percentage of non-idle cycles
634 system.cpu3.idle_fraction 0.046171 # Percentage of idle cycles
635 system.cpu3.icache.tags.replacements 279 # number of replacements
636 system.cpu3.icache.tags.tagsinuse 72.874497 # Cycle average of tags in use
637 system.cpu3.icache.tags.total_refs 166942 # Total number of references to valid blocks.
638 system.cpu3.icache.tags.sampled_refs 359 # Sample count of references to valid blocks.
639 system.cpu3.icache.tags.avg_refs 465.019499 # Average number of references to valid blocks.
640 system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
641 system.cpu3.icache.tags.occ_blocks::cpu3.inst 72.874497 # Average occupied blocks per requestor
642 system.cpu3.icache.tags.occ_percent::cpu3.inst 0.142333 # Average percentage of cache occupancy
643 system.cpu3.icache.tags.occ_percent::total 0.142333 # Average percentage of cache occupancy
644 system.cpu3.icache.ReadReq_hits::cpu3.inst 166942 # number of ReadReq hits
645 system.cpu3.icache.ReadReq_hits::total 166942 # number of ReadReq hits
646 system.cpu3.icache.demand_hits::cpu3.inst 166942 # number of demand (read+write) hits
647 system.cpu3.icache.demand_hits::total 166942 # number of demand (read+write) hits
648 system.cpu3.icache.overall_hits::cpu3.inst 166942 # number of overall hits
649 system.cpu3.icache.overall_hits::total 166942 # number of overall hits
650 system.cpu3.icache.ReadReq_misses::cpu3.inst 359 # number of ReadReq misses
651 system.cpu3.icache.ReadReq_misses::total 359 # number of ReadReq misses
652 system.cpu3.icache.demand_misses::cpu3.inst 359 # number of demand (read+write) misses
653 system.cpu3.icache.demand_misses::total 359 # number of demand (read+write) misses
654 system.cpu3.icache.overall_misses::cpu3.inst 359 # number of overall misses
655 system.cpu3.icache.overall_misses::total 359 # number of overall misses
656 system.cpu3.icache.ReadReq_accesses::cpu3.inst 167301 # number of ReadReq accesses(hits+misses)
657 system.cpu3.icache.ReadReq_accesses::total 167301 # number of ReadReq accesses(hits+misses)
658 system.cpu3.icache.demand_accesses::cpu3.inst 167301 # number of demand (read+write) accesses
659 system.cpu3.icache.demand_accesses::total 167301 # number of demand (read+write) accesses
660 system.cpu3.icache.overall_accesses::cpu3.inst 167301 # number of overall (read+write) accesses
661 system.cpu3.icache.overall_accesses::total 167301 # number of overall (read+write) accesses
662 system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002146 # miss rate for ReadReq accesses
663 system.cpu3.icache.ReadReq_miss_rate::total 0.002146 # miss rate for ReadReq accesses
664 system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002146 # miss rate for demand accesses
665 system.cpu3.icache.demand_miss_rate::total 0.002146 # miss rate for demand accesses
666 system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002146 # miss rate for overall accesses
667 system.cpu3.icache.overall_miss_rate::total 0.002146 # miss rate for overall accesses
668 system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
669 system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
670 system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked
671 system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked
672 system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
673 system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
674 system.cpu3.icache.fast_writes 0 # number of fast writes performed
675 system.cpu3.icache.cache_copies 0 # number of cache copies performed
676 system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate
677 system.cpu3.dcache.tags.replacements 0 # number of replacements
678 system.cpu3.dcache.tags.tagsinuse 28.795404 # Cycle average of tags in use
679 system.cpu3.dcache.tags.total_refs 30236 # Total number of references to valid blocks.
680 system.cpu3.dcache.tags.sampled_refs 27 # Sample count of references to valid blocks.
681 system.cpu3.dcache.tags.avg_refs 1119.851852 # Average number of references to valid blocks.
682 system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
683 system.cpu3.dcache.tags.occ_blocks::cpu3.data 28.795404 # Average occupied blocks per requestor
684 system.cpu3.dcache.tags.occ_percent::cpu3.data 0.056241 # Average percentage of cache occupancy
685 system.cpu3.dcache.tags.occ_percent::total 0.056241 # Average percentage of cache occupancy
686 system.cpu3.dcache.ReadReq_hits::cpu3.data 41301 # number of ReadReq hits
687 system.cpu3.dcache.ReadReq_hits::total 41301 # number of ReadReq hits
688 system.cpu3.dcache.WriteReq_hits::cpu3.data 14260 # number of WriteReq hits
689 system.cpu3.dcache.WriteReq_hits::total 14260 # number of WriteReq hits
690 system.cpu3.dcache.SwapReq_hits::cpu3.data 15 # number of SwapReq hits
691 system.cpu3.dcache.SwapReq_hits::total 15 # number of SwapReq hits
692 system.cpu3.dcache.demand_hits::cpu3.data 55561 # number of demand (read+write) hits
693 system.cpu3.dcache.demand_hits::total 55561 # number of demand (read+write) hits
694 system.cpu3.dcache.overall_hits::cpu3.data 55561 # number of overall hits
695 system.cpu3.dcache.overall_hits::total 55561 # number of overall hits
696 system.cpu3.dcache.ReadReq_misses::cpu3.data 157 # number of ReadReq misses
697 system.cpu3.dcache.ReadReq_misses::total 157 # number of ReadReq misses
698 system.cpu3.dcache.WriteReq_misses::cpu3.data 102 # number of WriteReq misses
699 system.cpu3.dcache.WriteReq_misses::total 102 # number of WriteReq misses
700 system.cpu3.dcache.SwapReq_misses::cpu3.data 55 # number of SwapReq misses
701 system.cpu3.dcache.SwapReq_misses::total 55 # number of SwapReq misses
702 system.cpu3.dcache.demand_misses::cpu3.data 259 # number of demand (read+write) misses
703 system.cpu3.dcache.demand_misses::total 259 # number of demand (read+write) misses
704 system.cpu3.dcache.overall_misses::cpu3.data 259 # number of overall misses
705 system.cpu3.dcache.overall_misses::total 259 # number of overall misses
706 system.cpu3.dcache.ReadReq_accesses::cpu3.data 41458 # number of ReadReq accesses(hits+misses)
707 system.cpu3.dcache.ReadReq_accesses::total 41458 # number of ReadReq accesses(hits+misses)
708 system.cpu3.dcache.WriteReq_accesses::cpu3.data 14362 # number of WriteReq accesses(hits+misses)
709 system.cpu3.dcache.WriteReq_accesses::total 14362 # number of WriteReq accesses(hits+misses)
710 system.cpu3.dcache.SwapReq_accesses::cpu3.data 70 # number of SwapReq accesses(hits+misses)
711 system.cpu3.dcache.SwapReq_accesses::total 70 # number of SwapReq accesses(hits+misses)
712 system.cpu3.dcache.demand_accesses::cpu3.data 55820 # number of demand (read+write) accesses
713 system.cpu3.dcache.demand_accesses::total 55820 # number of demand (read+write) accesses
714 system.cpu3.dcache.overall_accesses::cpu3.data 55820 # number of overall (read+write) accesses
715 system.cpu3.dcache.overall_accesses::total 55820 # number of overall (read+write) accesses
716 system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.003787 # miss rate for ReadReq accesses
717 system.cpu3.dcache.ReadReq_miss_rate::total 0.003787 # miss rate for ReadReq accesses
718 system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.007102 # miss rate for WriteReq accesses
719 system.cpu3.dcache.WriteReq_miss_rate::total 0.007102 # miss rate for WriteReq accesses
720 system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.785714 # miss rate for SwapReq accesses
721 system.cpu3.dcache.SwapReq_miss_rate::total 0.785714 # miss rate for SwapReq accesses
722 system.cpu3.dcache.demand_miss_rate::cpu3.data 0.004640 # miss rate for demand accesses
723 system.cpu3.dcache.demand_miss_rate::total 0.004640 # miss rate for demand accesses
724 system.cpu3.dcache.overall_miss_rate::cpu3.data 0.004640 # miss rate for overall accesses
725 system.cpu3.dcache.overall_miss_rate::total 0.004640 # miss rate for overall accesses
726 system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
727 system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
728 system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
729 system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked
730 system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
731 system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
732 system.cpu3.dcache.fast_writes 0 # number of fast writes performed
733 system.cpu3.dcache.cache_copies 0 # number of cache copies performed
734 system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
736 ---------- End Simulation Statistics ----------
projects / gem5.git / blob