2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.000088 # Number of seconds simulated
4 sim_ticks 87707000 # Number of ticks simulated
5 final_tick 87707000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 1618143 # Simulator instruction rate (inst/s)
8 host_op_rate 1618081 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 209518099 # Simulator tick rate (ticks/s)
10 host_mem_usage 283888 # Number of bytes of host memory used
11 host_seconds 0.42 # Real time elapsed on the host
12 sim_insts 677327 # Number of instructions simulated
13 sim_ops 677327 # Number of ops (including micro ops) simulated
14 system.voltage_domain.voltage 1 # Voltage in Volts
15 system.clk_domain.clock 1000 # Clock period in ticks
16 system.physmem.bytes_read::cpu0.inst 18048 # Number of bytes read from this memory
17 system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory
18 system.physmem.bytes_read::cpu1.inst 3968 # Number of bytes read from this memory
19 system.physmem.bytes_read::cpu1.data 1280 # Number of bytes read from this memory
20 system.physmem.bytes_read::cpu2.inst 128 # Number of bytes read from this memory
21 system.physmem.bytes_read::cpu2.data 832 # Number of bytes read from this memory
22 system.physmem.bytes_read::cpu3.inst 128 # Number of bytes read from this memory
23 system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory
24 system.physmem.bytes_read::total 35776 # Number of bytes read from this memory
25 system.physmem.bytes_inst_read::cpu0.inst 18048 # Number of instructions bytes read from this memory
26 system.physmem.bytes_inst_read::cpu1.inst 3968 # Number of instructions bytes read from this memory
27 system.physmem.bytes_inst_read::cpu2.inst 128 # Number of instructions bytes read from this memory
28 system.physmem.bytes_inst_read::cpu3.inst 128 # Number of instructions bytes read from this memory
29 system.physmem.bytes_inst_read::total 22272 # Number of instructions bytes read from this memory
30 system.physmem.num_reads::cpu0.inst 282 # Number of read requests responded to by this memory
31 system.physmem.num_reads::cpu0.data 165 # Number of read requests responded to by this memory
32 system.physmem.num_reads::cpu1.inst 62 # Number of read requests responded to by this memory
33 system.physmem.num_reads::cpu1.data 20 # Number of read requests responded to by this memory
34 system.physmem.num_reads::cpu2.inst 2 # Number of read requests responded to by this memory
35 system.physmem.num_reads::cpu2.data 13 # Number of read requests responded to by this memory
36 system.physmem.num_reads::cpu3.inst 2 # Number of read requests responded to by this memory
37 system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory
38 system.physmem.num_reads::total 559 # Number of read requests responded to by this memory
39 system.physmem.bw_read::cpu0.inst 205776050 # Total read bandwidth from this memory (bytes/s)
40 system.physmem.bw_read::cpu0.data 120400880 # Total read bandwidth from this memory (bytes/s)
41 system.physmem.bw_read::cpu1.inst 45241543 # Total read bandwidth from this memory (bytes/s)
42 system.physmem.bw_read::cpu1.data 14594046 # Total read bandwidth from this memory (bytes/s)
43 system.physmem.bw_read::cpu2.inst 1459405 # Total read bandwidth from this memory (bytes/s)
44 system.physmem.bw_read::cpu2.data 9486130 # Total read bandwidth from this memory (bytes/s)
45 system.physmem.bw_read::cpu3.inst 1459405 # Total read bandwidth from this memory (bytes/s)
46 system.physmem.bw_read::cpu3.data 9486130 # Total read bandwidth from this memory (bytes/s)
47 system.physmem.bw_read::total 407903588 # Total read bandwidth from this memory (bytes/s)
48 system.physmem.bw_inst_read::cpu0.inst 205776050 # Instruction read bandwidth from this memory (bytes/s)
49 system.physmem.bw_inst_read::cpu1.inst 45241543 # Instruction read bandwidth from this memory (bytes/s)
50 system.physmem.bw_inst_read::cpu2.inst 1459405 # Instruction read bandwidth from this memory (bytes/s)
51 system.physmem.bw_inst_read::cpu3.inst 1459405 # Instruction read bandwidth from this memory (bytes/s)
52 system.physmem.bw_inst_read::total 253936402 # Instruction read bandwidth from this memory (bytes/s)
53 system.physmem.bw_total::cpu0.inst 205776050 # Total bandwidth to/from this memory (bytes/s)
54 system.physmem.bw_total::cpu0.data 120400880 # Total bandwidth to/from this memory (bytes/s)
55 system.physmem.bw_total::cpu1.inst 45241543 # Total bandwidth to/from this memory (bytes/s)
56 system.physmem.bw_total::cpu1.data 14594046 # Total bandwidth to/from this memory (bytes/s)
57 system.physmem.bw_total::cpu2.inst 1459405 # Total bandwidth to/from this memory (bytes/s)
58 system.physmem.bw_total::cpu2.data 9486130 # Total bandwidth to/from this memory (bytes/s)
59 system.physmem.bw_total::cpu3.inst 1459405 # Total bandwidth to/from this memory (bytes/s)
60 system.physmem.bw_total::cpu3.data 9486130 # Total bandwidth to/from this memory (bytes/s)
61 system.physmem.bw_total::total 407903588 # Total bandwidth to/from this memory (bytes/s)
62 system.membus.throughput 407903588 # Throughput (bytes/s)
63 system.membus.data_through_bus 35776 # Total data (bytes)
64 system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
65 system.cpu_clk_domain.clock 500 # Clock period in ticks
66 system.l2c.tags.replacements 0 # number of replacements
67 system.l2c.tags.tagsinuse 366.582542 # Cycle average of tags in use
68 system.l2c.tags.total_refs 1220 # Total number of references to valid blocks.
69 system.l2c.tags.sampled_refs 421 # Sample count of references to valid blocks.
70 system.l2c.tags.avg_refs 2.897862 # Average number of references to valid blocks.
71 system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
72 system.l2c.tags.occ_blocks::writebacks 0.966439 # Average occupied blocks per requestor
73 system.l2c.tags.occ_blocks::cpu0.inst 239.426226 # Average occupied blocks per requestor
74 system.l2c.tags.occ_blocks::cpu0.data 55.207595 # Average occupied blocks per requestor
75 system.l2c.tags.occ_blocks::cpu1.inst 59.511852 # Average occupied blocks per requestor
76 system.l2c.tags.occ_blocks::cpu1.data 6.721145 # Average occupied blocks per requestor
77 system.l2c.tags.occ_blocks::cpu2.inst 1.930661 # Average occupied blocks per requestor
78 system.l2c.tags.occ_blocks::cpu2.data 0.935410 # Average occupied blocks per requestor
79 system.l2c.tags.occ_blocks::cpu3.inst 0.977573 # Average occupied blocks per requestor
80 system.l2c.tags.occ_blocks::cpu3.data 0.905640 # Average occupied blocks per requestor
81 system.l2c.tags.occ_percent::writebacks 0.000015 # Average percentage of cache occupancy
82 system.l2c.tags.occ_percent::cpu0.inst 0.003653 # Average percentage of cache occupancy
83 system.l2c.tags.occ_percent::cpu0.data 0.000842 # Average percentage of cache occupancy
84 system.l2c.tags.occ_percent::cpu1.inst 0.000908 # Average percentage of cache occupancy
85 system.l2c.tags.occ_percent::cpu1.data 0.000103 # Average percentage of cache occupancy
86 system.l2c.tags.occ_percent::cpu2.inst 0.000029 # Average percentage of cache occupancy
87 system.l2c.tags.occ_percent::cpu2.data 0.000014 # Average percentage of cache occupancy
88 system.l2c.tags.occ_percent::cpu3.inst 0.000015 # Average percentage of cache occupancy
89 system.l2c.tags.occ_percent::cpu3.data 0.000014 # Average percentage of cache occupancy
90 system.l2c.tags.occ_percent::total 0.005594 # Average percentage of cache occupancy
91 system.l2c.tags.occ_task_id_blocks::1024 421 # Occupied blocks per task id
92 system.l2c.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id
93 system.l2c.tags.age_task_id_blocks_1024::1 373 # Occupied blocks per task id
94 system.l2c.tags.occ_task_id_percent::1024 0.006424 # Percentage of cache occupancy per task id
95 system.l2c.tags.tag_accesses 15488 # Number of tag accesses
96 system.l2c.tags.data_accesses 15488 # Number of data accesses
97 system.l2c.ReadReq_hits::cpu0.inst 185 # number of ReadReq hits
98 system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits
99 system.l2c.ReadReq_hits::cpu1.inst 296 # number of ReadReq hits
100 system.l2c.ReadReq_hits::cpu1.data 3 # number of ReadReq hits
101 system.l2c.ReadReq_hits::cpu2.inst 356 # number of ReadReq hits
102 system.l2c.ReadReq_hits::cpu2.data 9 # number of ReadReq hits
103 system.l2c.ReadReq_hits::cpu3.inst 357 # number of ReadReq hits
104 system.l2c.ReadReq_hits::cpu3.data 9 # number of ReadReq hits
105 system.l2c.ReadReq_hits::total 1220 # number of ReadReq hits
106 system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits
107 system.l2c.Writeback_hits::total 1 # number of Writeback hits
108 system.l2c.UpgradeReq_hits::cpu0.data 2 # number of UpgradeReq hits
109 system.l2c.UpgradeReq_hits::total 2 # number of UpgradeReq hits
110 system.l2c.demand_hits::cpu0.inst 185 # number of demand (read+write) hits
111 system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits
112 system.l2c.demand_hits::cpu1.inst 296 # number of demand (read+write) hits
113 system.l2c.demand_hits::cpu1.data 3 # number of demand (read+write) hits
114 system.l2c.demand_hits::cpu2.inst 356 # number of demand (read+write) hits
115 system.l2c.demand_hits::cpu2.data 9 # number of demand (read+write) hits
116 system.l2c.demand_hits::cpu3.inst 357 # number of demand (read+write) hits
117 system.l2c.demand_hits::cpu3.data 9 # number of demand (read+write) hits
118 system.l2c.demand_hits::total 1220 # number of demand (read+write) hits
119 system.l2c.overall_hits::cpu0.inst 185 # number of overall hits
120 system.l2c.overall_hits::cpu0.data 5 # number of overall hits
121 system.l2c.overall_hits::cpu1.inst 296 # number of overall hits
122 system.l2c.overall_hits::cpu1.data 3 # number of overall hits
123 system.l2c.overall_hits::cpu2.inst 356 # number of overall hits
124 system.l2c.overall_hits::cpu2.data 9 # number of overall hits
125 system.l2c.overall_hits::cpu3.inst 357 # number of overall hits
126 system.l2c.overall_hits::cpu3.data 9 # number of overall hits
127 system.l2c.overall_hits::total 1220 # number of overall hits
128 system.l2c.ReadReq_misses::cpu0.inst 282 # number of ReadReq misses
129 system.l2c.ReadReq_misses::cpu0.data 66 # number of ReadReq misses
130 system.l2c.ReadReq_misses::cpu1.inst 62 # number of ReadReq misses
131 system.l2c.ReadReq_misses::cpu1.data 7 # number of ReadReq misses
132 system.l2c.ReadReq_misses::cpu2.inst 2 # number of ReadReq misses
133 system.l2c.ReadReq_misses::cpu2.data 1 # number of ReadReq misses
134 system.l2c.ReadReq_misses::cpu3.inst 2 # number of ReadReq misses
135 system.l2c.ReadReq_misses::cpu3.data 1 # number of ReadReq misses
136 system.l2c.ReadReq_misses::total 423 # number of ReadReq misses
137 system.l2c.UpgradeReq_misses::cpu0.data 29 # number of UpgradeReq misses
138 system.l2c.UpgradeReq_misses::cpu1.data 18 # number of UpgradeReq misses
139 system.l2c.UpgradeReq_misses::cpu2.data 19 # number of UpgradeReq misses
140 system.l2c.UpgradeReq_misses::cpu3.data 18 # number of UpgradeReq misses
141 system.l2c.UpgradeReq_misses::total 84 # number of UpgradeReq misses
142 system.l2c.ReadExReq_misses::cpu0.data 99 # number of ReadExReq misses
143 system.l2c.ReadExReq_misses::cpu1.data 13 # number of ReadExReq misses
144 system.l2c.ReadExReq_misses::cpu2.data 12 # number of ReadExReq misses
145 system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses
146 system.l2c.ReadExReq_misses::total 136 # number of ReadExReq misses
147 system.l2c.demand_misses::cpu0.inst 282 # number of demand (read+write) misses
148 system.l2c.demand_misses::cpu0.data 165 # number of demand (read+write) misses
149 system.l2c.demand_misses::cpu1.inst 62 # number of demand (read+write) misses
150 system.l2c.demand_misses::cpu1.data 20 # number of demand (read+write) misses
151 system.l2c.demand_misses::cpu2.inst 2 # number of demand (read+write) misses
152 system.l2c.demand_misses::cpu2.data 13 # number of demand (read+write) misses
153 system.l2c.demand_misses::cpu3.inst 2 # number of demand (read+write) misses
154 system.l2c.demand_misses::cpu3.data 13 # number of demand (read+write) misses
155 system.l2c.demand_misses::total 559 # number of demand (read+write) misses
156 system.l2c.overall_misses::cpu0.inst 282 # number of overall misses
157 system.l2c.overall_misses::cpu0.data 165 # number of overall misses
158 system.l2c.overall_misses::cpu1.inst 62 # number of overall misses
159 system.l2c.overall_misses::cpu1.data 20 # number of overall misses
160 system.l2c.overall_misses::cpu2.inst 2 # number of overall misses
161 system.l2c.overall_misses::cpu2.data 13 # number of overall misses
162 system.l2c.overall_misses::cpu3.inst 2 # number of overall misses
163 system.l2c.overall_misses::cpu3.data 13 # number of overall misses
164 system.l2c.overall_misses::total 559 # number of overall misses
165 system.l2c.ReadReq_accesses::cpu0.inst 467 # number of ReadReq accesses(hits+misses)
166 system.l2c.ReadReq_accesses::cpu0.data 71 # number of ReadReq accesses(hits+misses)
167 system.l2c.ReadReq_accesses::cpu1.inst 358 # number of ReadReq accesses(hits+misses)
168 system.l2c.ReadReq_accesses::cpu1.data 10 # number of ReadReq accesses(hits+misses)
169 system.l2c.ReadReq_accesses::cpu2.inst 358 # number of ReadReq accesses(hits+misses)
170 system.l2c.ReadReq_accesses::cpu2.data 10 # number of ReadReq accesses(hits+misses)
171 system.l2c.ReadReq_accesses::cpu3.inst 359 # number of ReadReq accesses(hits+misses)
172 system.l2c.ReadReq_accesses::cpu3.data 10 # number of ReadReq accesses(hits+misses)
173 system.l2c.ReadReq_accesses::total 1643 # number of ReadReq accesses(hits+misses)
174 system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses)
175 system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses)
176 system.l2c.UpgradeReq_accesses::cpu0.data 31 # number of UpgradeReq accesses(hits+misses)
177 system.l2c.UpgradeReq_accesses::cpu1.data 18 # number of UpgradeReq accesses(hits+misses)
178 system.l2c.UpgradeReq_accesses::cpu2.data 19 # number of UpgradeReq accesses(hits+misses)
179 system.l2c.UpgradeReq_accesses::cpu3.data 18 # number of UpgradeReq accesses(hits+misses)
180 system.l2c.UpgradeReq_accesses::total 86 # number of UpgradeReq accesses(hits+misses)
181 system.l2c.ReadExReq_accesses::cpu0.data 99 # number of ReadExReq accesses(hits+misses)
182 system.l2c.ReadExReq_accesses::cpu1.data 13 # number of ReadExReq accesses(hits+misses)
183 system.l2c.ReadExReq_accesses::cpu2.data 12 # number of ReadExReq accesses(hits+misses)
184 system.l2c.ReadExReq_accesses::cpu3.data 12 # number of ReadExReq accesses(hits+misses)
185 system.l2c.ReadExReq_accesses::total 136 # number of ReadExReq accesses(hits+misses)
186 system.l2c.demand_accesses::cpu0.inst 467 # number of demand (read+write) accesses
187 system.l2c.demand_accesses::cpu0.data 170 # number of demand (read+write) accesses
188 system.l2c.demand_accesses::cpu1.inst 358 # number of demand (read+write) accesses
189 system.l2c.demand_accesses::cpu1.data 23 # number of demand (read+write) accesses
190 system.l2c.demand_accesses::cpu2.inst 358 # number of demand (read+write) accesses
191 system.l2c.demand_accesses::cpu2.data 22 # number of demand (read+write) accesses
192 system.l2c.demand_accesses::cpu3.inst 359 # number of demand (read+write) accesses
193 system.l2c.demand_accesses::cpu3.data 22 # number of demand (read+write) accesses
194 system.l2c.demand_accesses::total 1779 # number of demand (read+write) accesses
195 system.l2c.overall_accesses::cpu0.inst 467 # number of overall (read+write) accesses
196 system.l2c.overall_accesses::cpu0.data 170 # number of overall (read+write) accesses
197 system.l2c.overall_accesses::cpu1.inst 358 # number of overall (read+write) accesses
198 system.l2c.overall_accesses::cpu1.data 23 # number of overall (read+write) accesses
199 system.l2c.overall_accesses::cpu2.inst 358 # number of overall (read+write) accesses
200 system.l2c.overall_accesses::cpu2.data 22 # number of overall (read+write) accesses
201 system.l2c.overall_accesses::cpu3.inst 359 # number of overall (read+write) accesses
202 system.l2c.overall_accesses::cpu3.data 22 # number of overall (read+write) accesses
203 system.l2c.overall_accesses::total 1779 # number of overall (read+write) accesses
204 system.l2c.ReadReq_miss_rate::cpu0.inst 0.603854 # miss rate for ReadReq accesses
205 system.l2c.ReadReq_miss_rate::cpu0.data 0.929577 # miss rate for ReadReq accesses
206 system.l2c.ReadReq_miss_rate::cpu1.inst 0.173184 # miss rate for ReadReq accesses
207 system.l2c.ReadReq_miss_rate::cpu1.data 0.700000 # miss rate for ReadReq accesses
208 system.l2c.ReadReq_miss_rate::cpu2.inst 0.005587 # miss rate for ReadReq accesses
209 system.l2c.ReadReq_miss_rate::cpu2.data 0.100000 # miss rate for ReadReq accesses
210 system.l2c.ReadReq_miss_rate::cpu3.inst 0.005571 # miss rate for ReadReq accesses
211 system.l2c.ReadReq_miss_rate::cpu3.data 0.100000 # miss rate for ReadReq accesses
212 system.l2c.ReadReq_miss_rate::total 0.257456 # miss rate for ReadReq accesses
213 system.l2c.UpgradeReq_miss_rate::cpu0.data 0.935484 # miss rate for UpgradeReq accesses
214 system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses
215 system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses
216 system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses
217 system.l2c.UpgradeReq_miss_rate::total 0.976744 # miss rate for UpgradeReq accesses
218 system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses
219 system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses
220 system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses
221 system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses
222 system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
223 system.l2c.demand_miss_rate::cpu0.inst 0.603854 # miss rate for demand accesses
224 system.l2c.demand_miss_rate::cpu0.data 0.970588 # miss rate for demand accesses
225 system.l2c.demand_miss_rate::cpu1.inst 0.173184 # miss rate for demand accesses
226 system.l2c.demand_miss_rate::cpu1.data 0.869565 # miss rate for demand accesses
227 system.l2c.demand_miss_rate::cpu2.inst 0.005587 # miss rate for demand accesses
228 system.l2c.demand_miss_rate::cpu2.data 0.590909 # miss rate for demand accesses
229 system.l2c.demand_miss_rate::cpu3.inst 0.005571 # miss rate for demand accesses
230 system.l2c.demand_miss_rate::cpu3.data 0.590909 # miss rate for demand accesses
231 system.l2c.demand_miss_rate::total 0.314221 # miss rate for demand accesses
232 system.l2c.overall_miss_rate::cpu0.inst 0.603854 # miss rate for overall accesses
233 system.l2c.overall_miss_rate::cpu0.data 0.970588 # miss rate for overall accesses
234 system.l2c.overall_miss_rate::cpu1.inst 0.173184 # miss rate for overall accesses
235 system.l2c.overall_miss_rate::cpu1.data 0.869565 # miss rate for overall accesses
236 system.l2c.overall_miss_rate::cpu2.inst 0.005587 # miss rate for overall accesses
237 system.l2c.overall_miss_rate::cpu2.data 0.590909 # miss rate for overall accesses
238 system.l2c.overall_miss_rate::cpu3.inst 0.005571 # miss rate for overall accesses
239 system.l2c.overall_miss_rate::cpu3.data 0.590909 # miss rate for overall accesses
240 system.l2c.overall_miss_rate::total 0.314221 # miss rate for overall accesses
241 system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
242 system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
243 system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
244 system.l2c.blocked::no_targets 0 # number of cycles access was blocked
245 system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
246 system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
247 system.l2c.fast_writes 0 # number of fast writes performed
248 system.l2c.cache_copies 0 # number of cache copies performed
249 system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
250 system.toL2Bus.throughput 1893577480 # Throughput (bytes/s)
251 system.toL2Bus.data_through_bus 166080 # Total data (bytes)
252 system.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
253 system.cpu0.workload.num_syscalls 89 # Number of system calls
254 system.cpu0.numCycles 175415 # number of cpu cycles simulated
255 system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
256 system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
257 system.cpu0.committedInsts 175326 # Number of instructions committed
258 system.cpu0.committedOps 175326 # Number of ops (including micro ops) committed
259 system.cpu0.num_int_alu_accesses 120376 # Number of integer alu accesses
260 system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses
261 system.cpu0.num_func_calls 390 # number of times a function call or return occured
262 system.cpu0.num_conditional_control_insts 28824 # number of instructions that are conditional controls
263 system.cpu0.num_int_insts 120376 # number of integer instructions
264 system.cpu0.num_fp_insts 0 # number of float instructions
265 system.cpu0.num_int_register_reads 349286 # number of times the integer registers were read
266 system.cpu0.num_int_register_writes 121983 # number of times the integer registers were written
267 system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read
268 system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written
269 system.cpu0.num_mem_refs 82397 # number of memory refs
270 system.cpu0.num_load_insts 54591 # Number of load instructions
271 system.cpu0.num_store_insts 27806 # Number of store instructions
272 system.cpu0.num_idle_cycles 0 # Number of idle cycles
273 system.cpu0.num_busy_cycles 175415 # Number of busy cycles
274 system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles
275 system.cpu0.idle_fraction 0 # Percentage of idle cycles
276 system.cpu0.Branches 29689 # Number of branches fetched
277 system.cpu0.op_class::No_OpClass 26416 15.06% 15.06% # Class of executed instruction
278 system.cpu0.op_class::IntAlu 66491 37.91% 52.97% # Class of executed instruction
279 system.cpu0.op_class::IntMult 0 0.00% 52.97% # Class of executed instruction
280 system.cpu0.op_class::IntDiv 0 0.00% 52.97% # Class of executed instruction
281 system.cpu0.op_class::FloatAdd 0 0.00% 52.97% # Class of executed instruction
282 system.cpu0.op_class::FloatCmp 0 0.00% 52.97% # Class of executed instruction
283 system.cpu0.op_class::FloatCvt 0 0.00% 52.97% # Class of executed instruction
284 system.cpu0.op_class::FloatMult 0 0.00% 52.97% # Class of executed instruction
285 system.cpu0.op_class::FloatDiv 0 0.00% 52.97% # Class of executed instruction
286 system.cpu0.op_class::FloatSqrt 0 0.00% 52.97% # Class of executed instruction
287 system.cpu0.op_class::SimdAdd 0 0.00% 52.97% # Class of executed instruction
288 system.cpu0.op_class::SimdAddAcc 0 0.00% 52.97% # Class of executed instruction
289 system.cpu0.op_class::SimdAlu 0 0.00% 52.97% # Class of executed instruction
290 system.cpu0.op_class::SimdCmp 0 0.00% 52.97% # Class of executed instruction
291 system.cpu0.op_class::SimdCvt 0 0.00% 52.97% # Class of executed instruction
292 system.cpu0.op_class::SimdMisc 0 0.00% 52.97% # Class of executed instruction
293 system.cpu0.op_class::SimdMult 0 0.00% 52.97% # Class of executed instruction
294 system.cpu0.op_class::SimdMultAcc 0 0.00% 52.97% # Class of executed instruction
295 system.cpu0.op_class::SimdShift 0 0.00% 52.97% # Class of executed instruction
296 system.cpu0.op_class::SimdShiftAcc 0 0.00% 52.97% # Class of executed instruction
297 system.cpu0.op_class::SimdSqrt 0 0.00% 52.97% # Class of executed instruction
298 system.cpu0.op_class::SimdFloatAdd 0 0.00% 52.97% # Class of executed instruction
299 system.cpu0.op_class::SimdFloatAlu 0 0.00% 52.97% # Class of executed instruction
300 system.cpu0.op_class::SimdFloatCmp 0 0.00% 52.97% # Class of executed instruction
301 system.cpu0.op_class::SimdFloatCvt 0 0.00% 52.97% # Class of executed instruction
302 system.cpu0.op_class::SimdFloatDiv 0 0.00% 52.97% # Class of executed instruction
303 system.cpu0.op_class::SimdFloatMisc 0 0.00% 52.97% # Class of executed instruction
304 system.cpu0.op_class::SimdFloatMult 0 0.00% 52.97% # Class of executed instruction
305 system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 52.97% # Class of executed instruction
306 system.cpu0.op_class::SimdFloatSqrt 0 0.00% 52.97% # Class of executed instruction
307 system.cpu0.op_class::MemRead 54675 31.17% 84.15% # Class of executed instruction
308 system.cpu0.op_class::MemWrite 27806 15.85% 100.00% # Class of executed instruction
309 system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
310 system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
311 system.cpu0.op_class::total 175388 # Class of executed instruction
312 system.cpu0.icache.tags.replacements 215 # number of replacements
313 system.cpu0.icache.tags.tagsinuse 222.772698 # Cycle average of tags in use
314 system.cpu0.icache.tags.total_refs 174921 # Total number of references to valid blocks.
315 system.cpu0.icache.tags.sampled_refs 467 # Sample count of references to valid blocks.
316 system.cpu0.icache.tags.avg_refs 374.563169 # Average number of references to valid blocks.
317 system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
318 system.cpu0.icache.tags.occ_blocks::cpu0.inst 222.772698 # Average occupied blocks per requestor
319 system.cpu0.icache.tags.occ_percent::cpu0.inst 0.435103 # Average percentage of cache occupancy
320 system.cpu0.icache.tags.occ_percent::total 0.435103 # Average percentage of cache occupancy
321 system.cpu0.icache.tags.occ_task_id_blocks::1024 252 # Occupied blocks per task id
322 system.cpu0.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id
323 system.cpu0.icache.tags.age_task_id_blocks_1024::1 199 # Occupied blocks per task id
324 system.cpu0.icache.tags.occ_task_id_percent::1024 0.492188 # Percentage of cache occupancy per task id
325 system.cpu0.icache.tags.tag_accesses 175855 # Number of tag accesses
326 system.cpu0.icache.tags.data_accesses 175855 # Number of data accesses
327 system.cpu0.icache.ReadReq_hits::cpu0.inst 174921 # number of ReadReq hits
328 system.cpu0.icache.ReadReq_hits::total 174921 # number of ReadReq hits
329 system.cpu0.icache.demand_hits::cpu0.inst 174921 # number of demand (read+write) hits
330 system.cpu0.icache.demand_hits::total 174921 # number of demand (read+write) hits
331 system.cpu0.icache.overall_hits::cpu0.inst 174921 # number of overall hits
332 system.cpu0.icache.overall_hits::total 174921 # number of overall hits
333 system.cpu0.icache.ReadReq_misses::cpu0.inst 467 # number of ReadReq misses
334 system.cpu0.icache.ReadReq_misses::total 467 # number of ReadReq misses
335 system.cpu0.icache.demand_misses::cpu0.inst 467 # number of demand (read+write) misses
336 system.cpu0.icache.demand_misses::total 467 # number of demand (read+write) misses
337 system.cpu0.icache.overall_misses::cpu0.inst 467 # number of overall misses
338 system.cpu0.icache.overall_misses::total 467 # number of overall misses
339 system.cpu0.icache.ReadReq_accesses::cpu0.inst 175388 # number of ReadReq accesses(hits+misses)
340 system.cpu0.icache.ReadReq_accesses::total 175388 # number of ReadReq accesses(hits+misses)
341 system.cpu0.icache.demand_accesses::cpu0.inst 175388 # number of demand (read+write) accesses
342 system.cpu0.icache.demand_accesses::total 175388 # number of demand (read+write) accesses
343 system.cpu0.icache.overall_accesses::cpu0.inst 175388 # number of overall (read+write) accesses
344 system.cpu0.icache.overall_accesses::total 175388 # number of overall (read+write) accesses
345 system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002663 # miss rate for ReadReq accesses
346 system.cpu0.icache.ReadReq_miss_rate::total 0.002663 # miss rate for ReadReq accesses
347 system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002663 # miss rate for demand accesses
348 system.cpu0.icache.demand_miss_rate::total 0.002663 # miss rate for demand accesses
349 system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002663 # miss rate for overall accesses
350 system.cpu0.icache.overall_miss_rate::total 0.002663 # miss rate for overall accesses
351 system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
352 system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
353 system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
354 system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
355 system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
356 system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
357 system.cpu0.icache.fast_writes 0 # number of fast writes performed
358 system.cpu0.icache.cache_copies 0 # number of cache copies performed
359 system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
360 system.cpu0.dcache.tags.replacements 2 # number of replacements
361 system.cpu0.dcache.tags.tagsinuse 150.745494 # Cycle average of tags in use
362 system.cpu0.dcache.tags.total_refs 81883 # Total number of references to valid blocks.
363 system.cpu0.dcache.tags.sampled_refs 167 # Sample count of references to valid blocks.
364 system.cpu0.dcache.tags.avg_refs 490.317365 # Average number of references to valid blocks.
365 system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
366 system.cpu0.dcache.tags.occ_blocks::cpu0.data 150.745494 # Average occupied blocks per requestor
367 system.cpu0.dcache.tags.occ_percent::cpu0.data 0.294425 # Average percentage of cache occupancy
368 system.cpu0.dcache.tags.occ_percent::total 0.294425 # Average percentage of cache occupancy
369 system.cpu0.dcache.tags.occ_task_id_blocks::1024 165 # Occupied blocks per task id
370 system.cpu0.dcache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id
371 system.cpu0.dcache.tags.age_task_id_blocks_1024::1 149 # Occupied blocks per task id
372 system.cpu0.dcache.tags.occ_task_id_percent::1024 0.322266 # Percentage of cache occupancy per task id
373 system.cpu0.dcache.tags.tag_accesses 329803 # Number of tag accesses
374 system.cpu0.dcache.tags.data_accesses 329803 # Number of data accesses
375 system.cpu0.dcache.ReadReq_hits::cpu0.data 54430 # number of ReadReq hits
376 system.cpu0.dcache.ReadReq_hits::total 54430 # number of ReadReq hits
377 system.cpu0.dcache.WriteReq_hits::cpu0.data 27578 # number of WriteReq hits
378 system.cpu0.dcache.WriteReq_hits::total 27578 # number of WriteReq hits
379 system.cpu0.dcache.SwapReq_hits::cpu0.data 15 # number of SwapReq hits
380 system.cpu0.dcache.SwapReq_hits::total 15 # number of SwapReq hits
381 system.cpu0.dcache.demand_hits::cpu0.data 82008 # number of demand (read+write) hits
382 system.cpu0.dcache.demand_hits::total 82008 # number of demand (read+write) hits
383 system.cpu0.dcache.overall_hits::cpu0.data 82008 # number of overall hits
384 system.cpu0.dcache.overall_hits::total 82008 # number of overall hits
385 system.cpu0.dcache.ReadReq_misses::cpu0.data 151 # number of ReadReq misses
386 system.cpu0.dcache.ReadReq_misses::total 151 # number of ReadReq misses
387 system.cpu0.dcache.WriteReq_misses::cpu0.data 177 # number of WriteReq misses
388 system.cpu0.dcache.WriteReq_misses::total 177 # number of WriteReq misses
389 system.cpu0.dcache.SwapReq_misses::cpu0.data 27 # number of SwapReq misses
390 system.cpu0.dcache.SwapReq_misses::total 27 # number of SwapReq misses
391 system.cpu0.dcache.demand_misses::cpu0.data 328 # number of demand (read+write) misses
392 system.cpu0.dcache.demand_misses::total 328 # number of demand (read+write) misses
393 system.cpu0.dcache.overall_misses::cpu0.data 328 # number of overall misses
394 system.cpu0.dcache.overall_misses::total 328 # number of overall misses
395 system.cpu0.dcache.ReadReq_accesses::cpu0.data 54581 # number of ReadReq accesses(hits+misses)
396 system.cpu0.dcache.ReadReq_accesses::total 54581 # number of ReadReq accesses(hits+misses)
397 system.cpu0.dcache.WriteReq_accesses::cpu0.data 27755 # number of WriteReq accesses(hits+misses)
398 system.cpu0.dcache.WriteReq_accesses::total 27755 # number of WriteReq accesses(hits+misses)
399 system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses)
400 system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses)
401 system.cpu0.dcache.demand_accesses::cpu0.data 82336 # number of demand (read+write) accesses
402 system.cpu0.dcache.demand_accesses::total 82336 # number of demand (read+write) accesses
403 system.cpu0.dcache.overall_accesses::cpu0.data 82336 # number of overall (read+write) accesses
404 system.cpu0.dcache.overall_accesses::total 82336 # number of overall (read+write) accesses
405 system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.002767 # miss rate for ReadReq accesses
406 system.cpu0.dcache.ReadReq_miss_rate::total 0.002767 # miss rate for ReadReq accesses
407 system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.006377 # miss rate for WriteReq accesses
408 system.cpu0.dcache.WriteReq_miss_rate::total 0.006377 # miss rate for WriteReq accesses
409 system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.642857 # miss rate for SwapReq accesses
410 system.cpu0.dcache.SwapReq_miss_rate::total 0.642857 # miss rate for SwapReq accesses
411 system.cpu0.dcache.demand_miss_rate::cpu0.data 0.003984 # miss rate for demand accesses
412 system.cpu0.dcache.demand_miss_rate::total 0.003984 # miss rate for demand accesses
413 system.cpu0.dcache.overall_miss_rate::cpu0.data 0.003984 # miss rate for overall accesses
414 system.cpu0.dcache.overall_miss_rate::total 0.003984 # miss rate for overall accesses
415 system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
416 system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
417 system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
418 system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
419 system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
420 system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
421 system.cpu0.dcache.fast_writes 0 # number of fast writes performed
422 system.cpu0.dcache.cache_copies 0 # number of cache copies performed
423 system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks
424 system.cpu0.dcache.writebacks::total 1 # number of writebacks
425 system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
426 system.cpu1.numCycles 173295 # number of cpu cycles simulated
427 system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
428 system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
429 system.cpu1.committedInsts 167398 # Number of instructions committed
430 system.cpu1.committedOps 167398 # Number of ops (including micro ops) committed
431 system.cpu1.num_int_alu_accesses 109926 # Number of integer alu accesses
432 system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses
433 system.cpu1.num_func_calls 633 # number of times a function call or return occured
434 system.cpu1.num_conditional_control_insts 32743 # number of instructions that are conditional controls
435 system.cpu1.num_int_insts 109926 # number of integer instructions
436 system.cpu1.num_fp_insts 0 # number of float instructions
437 system.cpu1.num_int_register_reads 270038 # number of times the integer registers were read
438 system.cpu1.num_int_register_writes 100721 # number of times the integer registers were written
439 system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read
440 system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written
441 system.cpu1.num_mem_refs 53394 # number of memory refs
442 system.cpu1.num_load_insts 40652 # Number of load instructions
443 system.cpu1.num_store_insts 12742 # Number of store instructions
444 system.cpu1.num_idle_cycles 7873.724337 # Number of idle cycles
445 system.cpu1.num_busy_cycles 165421.275663 # Number of busy cycles
446 system.cpu1.not_idle_fraction 0.954565 # Percentage of non-idle cycles
447 system.cpu1.idle_fraction 0.045435 # Percentage of idle cycles
448 system.cpu1.Branches 34390 # Number of branches fetched
449 system.cpu1.op_class::No_OpClass 25177 15.04% 15.04% # Class of executed instruction
450 system.cpu1.op_class::IntAlu 73170 43.70% 58.74% # Class of executed instruction
451 system.cpu1.op_class::IntMult 0 0.00% 58.74% # Class of executed instruction
452 system.cpu1.op_class::IntDiv 0 0.00% 58.74% # Class of executed instruction
453 system.cpu1.op_class::FloatAdd 0 0.00% 58.74% # Class of executed instruction
454 system.cpu1.op_class::FloatCmp 0 0.00% 58.74% # Class of executed instruction
455 system.cpu1.op_class::FloatCvt 0 0.00% 58.74% # Class of executed instruction
456 system.cpu1.op_class::FloatMult 0 0.00% 58.74% # Class of executed instruction
457 system.cpu1.op_class::FloatDiv 0 0.00% 58.74% # Class of executed instruction
458 system.cpu1.op_class::FloatSqrt 0 0.00% 58.74% # Class of executed instruction
459 system.cpu1.op_class::SimdAdd 0 0.00% 58.74% # Class of executed instruction
460 system.cpu1.op_class::SimdAddAcc 0 0.00% 58.74% # Class of executed instruction
461 system.cpu1.op_class::SimdAlu 0 0.00% 58.74% # Class of executed instruction
462 system.cpu1.op_class::SimdCmp 0 0.00% 58.74% # Class of executed instruction
463 system.cpu1.op_class::SimdCvt 0 0.00% 58.74% # Class of executed instruction
464 system.cpu1.op_class::SimdMisc 0 0.00% 58.74% # Class of executed instruction
465 system.cpu1.op_class::SimdMult 0 0.00% 58.74% # Class of executed instruction
466 system.cpu1.op_class::SimdMultAcc 0 0.00% 58.74% # Class of executed instruction
467 system.cpu1.op_class::SimdShift 0 0.00% 58.74% # Class of executed instruction
468 system.cpu1.op_class::SimdShiftAcc 0 0.00% 58.74% # Class of executed instruction
469 system.cpu1.op_class::SimdSqrt 0 0.00% 58.74% # Class of executed instruction
470 system.cpu1.op_class::SimdFloatAdd 0 0.00% 58.74% # Class of executed instruction
471 system.cpu1.op_class::SimdFloatAlu 0 0.00% 58.74% # Class of executed instruction
472 system.cpu1.op_class::SimdFloatCmp 0 0.00% 58.74% # Class of executed instruction
473 system.cpu1.op_class::SimdFloatCvt 0 0.00% 58.74% # Class of executed instruction
474 system.cpu1.op_class::SimdFloatDiv 0 0.00% 58.74% # Class of executed instruction
475 system.cpu1.op_class::SimdFloatMisc 0 0.00% 58.74% # Class of executed instruction
476 system.cpu1.op_class::SimdFloatMult 0 0.00% 58.74% # Class of executed instruction
477 system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 58.74% # Class of executed instruction
478 system.cpu1.op_class::SimdFloatSqrt 0 0.00% 58.74% # Class of executed instruction
479 system.cpu1.op_class::MemRead 56341 33.65% 92.39% # Class of executed instruction
480 system.cpu1.op_class::MemWrite 12742 7.61% 100.00% # Class of executed instruction
481 system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
482 system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
483 system.cpu1.op_class::total 167430 # Class of executed instruction
484 system.cpu1.icache.tags.replacements 278 # number of replacements
485 system.cpu1.icache.tags.tagsinuse 76.751702 # Cycle average of tags in use
486 system.cpu1.icache.tags.total_refs 167072 # Total number of references to valid blocks.
487 system.cpu1.icache.tags.sampled_refs 358 # Sample count of references to valid blocks.
488 system.cpu1.icache.tags.avg_refs 466.681564 # Average number of references to valid blocks.
489 system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
490 system.cpu1.icache.tags.occ_blocks::cpu1.inst 76.751702 # Average occupied blocks per requestor
491 system.cpu1.icache.tags.occ_percent::cpu1.inst 0.149906 # Average percentage of cache occupancy
492 system.cpu1.icache.tags.occ_percent::total 0.149906 # Average percentage of cache occupancy
493 system.cpu1.icache.tags.occ_task_id_blocks::1024 80 # Occupied blocks per task id
494 system.cpu1.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id
495 system.cpu1.icache.tags.age_task_id_blocks_1024::1 71 # Occupied blocks per task id
496 system.cpu1.icache.tags.occ_task_id_percent::1024 0.156250 # Percentage of cache occupancy per task id
497 system.cpu1.icache.tags.tag_accesses 167788 # Number of tag accesses
498 system.cpu1.icache.tags.data_accesses 167788 # Number of data accesses
499 system.cpu1.icache.ReadReq_hits::cpu1.inst 167072 # number of ReadReq hits
500 system.cpu1.icache.ReadReq_hits::total 167072 # number of ReadReq hits
501 system.cpu1.icache.demand_hits::cpu1.inst 167072 # number of demand (read+write) hits
502 system.cpu1.icache.demand_hits::total 167072 # number of demand (read+write) hits
503 system.cpu1.icache.overall_hits::cpu1.inst 167072 # number of overall hits
504 system.cpu1.icache.overall_hits::total 167072 # number of overall hits
505 system.cpu1.icache.ReadReq_misses::cpu1.inst 358 # number of ReadReq misses
506 system.cpu1.icache.ReadReq_misses::total 358 # number of ReadReq misses
507 system.cpu1.icache.demand_misses::cpu1.inst 358 # number of demand (read+write) misses
508 system.cpu1.icache.demand_misses::total 358 # number of demand (read+write) misses
509 system.cpu1.icache.overall_misses::cpu1.inst 358 # number of overall misses
510 system.cpu1.icache.overall_misses::total 358 # number of overall misses
511 system.cpu1.icache.ReadReq_accesses::cpu1.inst 167430 # number of ReadReq accesses(hits+misses)
512 system.cpu1.icache.ReadReq_accesses::total 167430 # number of ReadReq accesses(hits+misses)
513 system.cpu1.icache.demand_accesses::cpu1.inst 167430 # number of demand (read+write) accesses
514 system.cpu1.icache.demand_accesses::total 167430 # number of demand (read+write) accesses
515 system.cpu1.icache.overall_accesses::cpu1.inst 167430 # number of overall (read+write) accesses
516 system.cpu1.icache.overall_accesses::total 167430 # number of overall (read+write) accesses
517 system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002138 # miss rate for ReadReq accesses
518 system.cpu1.icache.ReadReq_miss_rate::total 0.002138 # miss rate for ReadReq accesses
519 system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002138 # miss rate for demand accesses
520 system.cpu1.icache.demand_miss_rate::total 0.002138 # miss rate for demand accesses
521 system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002138 # miss rate for overall accesses
522 system.cpu1.icache.overall_miss_rate::total 0.002138 # miss rate for overall accesses
523 system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
524 system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
525 system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
526 system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
527 system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
528 system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
529 system.cpu1.icache.fast_writes 0 # number of fast writes performed
530 system.cpu1.icache.cache_copies 0 # number of cache copies performed
531 system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
532 system.cpu1.dcache.tags.replacements 0 # number of replacements
533 system.cpu1.dcache.tags.tagsinuse 30.316999 # Cycle average of tags in use
534 system.cpu1.dcache.tags.total_refs 26731 # Total number of references to valid blocks.
535 system.cpu1.dcache.tags.sampled_refs 26 # Sample count of references to valid blocks.
536 system.cpu1.dcache.tags.avg_refs 1028.115385 # Average number of references to valid blocks.
537 system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
538 system.cpu1.dcache.tags.occ_blocks::cpu1.data 30.316999 # Average occupied blocks per requestor
539 system.cpu1.dcache.tags.occ_percent::cpu1.data 0.059213 # Average percentage of cache occupancy
540 system.cpu1.dcache.tags.occ_percent::total 0.059213 # Average percentage of cache occupancy
541 system.cpu1.dcache.tags.occ_task_id_blocks::1024 26 # Occupied blocks per task id
542 system.cpu1.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id
543 system.cpu1.dcache.tags.occ_task_id_percent::1024 0.050781 # Percentage of cache occupancy per task id
544 system.cpu1.dcache.tags.tag_accesses 213800 # Number of tag accesses
545 system.cpu1.dcache.tags.data_accesses 213800 # Number of data accesses
546 system.cpu1.dcache.ReadReq_hits::cpu1.data 40470 # number of ReadReq hits
547 system.cpu1.dcache.ReadReq_hits::total 40470 # number of ReadReq hits
548 system.cpu1.dcache.WriteReq_hits::cpu1.data 12563 # number of WriteReq hits
549 system.cpu1.dcache.WriteReq_hits::total 12563 # number of WriteReq hits
550 system.cpu1.dcache.SwapReq_hits::cpu1.data 14 # number of SwapReq hits
551 system.cpu1.dcache.SwapReq_hits::total 14 # number of SwapReq hits
552 system.cpu1.dcache.demand_hits::cpu1.data 53033 # number of demand (read+write) hits
553 system.cpu1.dcache.demand_hits::total 53033 # number of demand (read+write) hits
554 system.cpu1.dcache.overall_hits::cpu1.data 53033 # number of overall hits
555 system.cpu1.dcache.overall_hits::total 53033 # number of overall hits
556 system.cpu1.dcache.ReadReq_misses::cpu1.data 174 # number of ReadReq misses
557 system.cpu1.dcache.ReadReq_misses::total 174 # number of ReadReq misses
558 system.cpu1.dcache.WriteReq_misses::cpu1.data 106 # number of WriteReq misses
559 system.cpu1.dcache.WriteReq_misses::total 106 # number of WriteReq misses
560 system.cpu1.dcache.SwapReq_misses::cpu1.data 57 # number of SwapReq misses
561 system.cpu1.dcache.SwapReq_misses::total 57 # number of SwapReq misses
562 system.cpu1.dcache.demand_misses::cpu1.data 280 # number of demand (read+write) misses
563 system.cpu1.dcache.demand_misses::total 280 # number of demand (read+write) misses
564 system.cpu1.dcache.overall_misses::cpu1.data 280 # number of overall misses
565 system.cpu1.dcache.overall_misses::total 280 # number of overall misses
566 system.cpu1.dcache.ReadReq_accesses::cpu1.data 40644 # number of ReadReq accesses(hits+misses)
567 system.cpu1.dcache.ReadReq_accesses::total 40644 # number of ReadReq accesses(hits+misses)
568 system.cpu1.dcache.WriteReq_accesses::cpu1.data 12669 # number of WriteReq accesses(hits+misses)
569 system.cpu1.dcache.WriteReq_accesses::total 12669 # number of WriteReq accesses(hits+misses)
570 system.cpu1.dcache.SwapReq_accesses::cpu1.data 71 # number of SwapReq accesses(hits+misses)
571 system.cpu1.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses)
572 system.cpu1.dcache.demand_accesses::cpu1.data 53313 # number of demand (read+write) accesses
573 system.cpu1.dcache.demand_accesses::total 53313 # number of demand (read+write) accesses
574 system.cpu1.dcache.overall_accesses::cpu1.data 53313 # number of overall (read+write) accesses
575 system.cpu1.dcache.overall_accesses::total 53313 # number of overall (read+write) accesses
576 system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.004281 # miss rate for ReadReq accesses
577 system.cpu1.dcache.ReadReq_miss_rate::total 0.004281 # miss rate for ReadReq accesses
578 system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.008367 # miss rate for WriteReq accesses
579 system.cpu1.dcache.WriteReq_miss_rate::total 0.008367 # miss rate for WriteReq accesses
580 system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.802817 # miss rate for SwapReq accesses
581 system.cpu1.dcache.SwapReq_miss_rate::total 0.802817 # miss rate for SwapReq accesses
582 system.cpu1.dcache.demand_miss_rate::cpu1.data 0.005252 # miss rate for demand accesses
583 system.cpu1.dcache.demand_miss_rate::total 0.005252 # miss rate for demand accesses
584 system.cpu1.dcache.overall_miss_rate::cpu1.data 0.005252 # miss rate for overall accesses
585 system.cpu1.dcache.overall_miss_rate::total 0.005252 # miss rate for overall accesses
586 system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
587 system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
588 system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
589 system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
590 system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
591 system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
592 system.cpu1.dcache.fast_writes 0 # number of fast writes performed
593 system.cpu1.dcache.cache_copies 0 # number of cache copies performed
594 system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
595 system.cpu2.numCycles 173295 # number of cpu cycles simulated
596 system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
597 system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
598 system.cpu2.committedInsts 167334 # Number of instructions committed
599 system.cpu2.committedOps 167334 # Number of ops (including micro ops) committed
600 system.cpu2.num_int_alu_accesses 113333 # Number of integer alu accesses
601 system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses
602 system.cpu2.num_func_calls 633 # number of times a function call or return occured
603 system.cpu2.num_conditional_control_insts 31007 # number of instructions that are conditional controls
604 system.cpu2.num_int_insts 113333 # number of integer instructions
605 system.cpu2.num_fp_insts 0 # number of float instructions
606 system.cpu2.num_int_register_reads 290613 # number of times the integer registers were read
607 system.cpu2.num_int_register_writes 109308 # number of times the integer registers were written
608 system.cpu2.num_fp_register_reads 0 # number of times the floating registers were read
609 system.cpu2.num_fp_register_writes 0 # number of times the floating registers were written
610 system.cpu2.num_mem_refs 58537 # number of memory refs
611 system.cpu2.num_load_insts 42362 # Number of load instructions
612 system.cpu2.num_store_insts 16175 # Number of store instructions
613 system.cpu2.num_idle_cycles 7936.951217 # Number of idle cycles
614 system.cpu2.num_busy_cycles 165358.048783 # Number of busy cycles
615 system.cpu2.not_idle_fraction 0.954200 # Percentage of non-idle cycles
616 system.cpu2.idle_fraction 0.045800 # Percentage of idle cycles
617 system.cpu2.Branches 32652 # Number of branches fetched
618 system.cpu2.op_class::No_OpClass 23444 14.01% 14.01% # Class of executed instruction
619 system.cpu2.op_class::IntAlu 74873 44.74% 58.74% # Class of executed instruction
620 system.cpu2.op_class::IntMult 0 0.00% 58.74% # Class of executed instruction
621 system.cpu2.op_class::IntDiv 0 0.00% 58.74% # Class of executed instruction
622 system.cpu2.op_class::FloatAdd 0 0.00% 58.74% # Class of executed instruction
623 system.cpu2.op_class::FloatCmp 0 0.00% 58.74% # Class of executed instruction
624 system.cpu2.op_class::FloatCvt 0 0.00% 58.74% # Class of executed instruction
625 system.cpu2.op_class::FloatMult 0 0.00% 58.74% # Class of executed instruction
626 system.cpu2.op_class::FloatDiv 0 0.00% 58.74% # Class of executed instruction
627 system.cpu2.op_class::FloatSqrt 0 0.00% 58.74% # Class of executed instruction
628 system.cpu2.op_class::SimdAdd 0 0.00% 58.74% # Class of executed instruction
629 system.cpu2.op_class::SimdAddAcc 0 0.00% 58.74% # Class of executed instruction
630 system.cpu2.op_class::SimdAlu 0 0.00% 58.74% # Class of executed instruction
631 system.cpu2.op_class::SimdCmp 0 0.00% 58.74% # Class of executed instruction
632 system.cpu2.op_class::SimdCvt 0 0.00% 58.74% # Class of executed instruction
633 system.cpu2.op_class::SimdMisc 0 0.00% 58.74% # Class of executed instruction
634 system.cpu2.op_class::SimdMult 0 0.00% 58.74% # Class of executed instruction
635 system.cpu2.op_class::SimdMultAcc 0 0.00% 58.74% # Class of executed instruction
636 system.cpu2.op_class::SimdShift 0 0.00% 58.74% # Class of executed instruction
637 system.cpu2.op_class::SimdShiftAcc 0 0.00% 58.74% # Class of executed instruction
638 system.cpu2.op_class::SimdSqrt 0 0.00% 58.74% # Class of executed instruction
639 system.cpu2.op_class::SimdFloatAdd 0 0.00% 58.74% # Class of executed instruction
640 system.cpu2.op_class::SimdFloatAlu 0 0.00% 58.74% # Class of executed instruction
641 system.cpu2.op_class::SimdFloatCmp 0 0.00% 58.74% # Class of executed instruction
642 system.cpu2.op_class::SimdFloatCvt 0 0.00% 58.74% # Class of executed instruction
643 system.cpu2.op_class::SimdFloatDiv 0 0.00% 58.74% # Class of executed instruction
644 system.cpu2.op_class::SimdFloatMisc 0 0.00% 58.74% # Class of executed instruction
645 system.cpu2.op_class::SimdFloatMult 0 0.00% 58.74% # Class of executed instruction
646 system.cpu2.op_class::SimdFloatMultAcc 0 0.00% 58.74% # Class of executed instruction
647 system.cpu2.op_class::SimdFloatSqrt 0 0.00% 58.74% # Class of executed instruction
648 system.cpu2.op_class::MemRead 52874 31.59% 90.34% # Class of executed instruction
649 system.cpu2.op_class::MemWrite 16175 9.66% 100.00% # Class of executed instruction
650 system.cpu2.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
651 system.cpu2.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
652 system.cpu2.op_class::total 167366 # Class of executed instruction
653 system.cpu2.icache.tags.replacements 278 # number of replacements
654 system.cpu2.icache.tags.tagsinuse 74.781015 # Cycle average of tags in use
655 system.cpu2.icache.tags.total_refs 167008 # Total number of references to valid blocks.
656 system.cpu2.icache.tags.sampled_refs 358 # Sample count of references to valid blocks.
657 system.cpu2.icache.tags.avg_refs 466.502793 # Average number of references to valid blocks.
658 system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
659 system.cpu2.icache.tags.occ_blocks::cpu2.inst 74.781015 # Average occupied blocks per requestor
660 system.cpu2.icache.tags.occ_percent::cpu2.inst 0.146057 # Average percentage of cache occupancy
661 system.cpu2.icache.tags.occ_percent::total 0.146057 # Average percentage of cache occupancy
662 system.cpu2.icache.tags.occ_task_id_blocks::1024 80 # Occupied blocks per task id
663 system.cpu2.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id
664 system.cpu2.icache.tags.age_task_id_blocks_1024::1 71 # Occupied blocks per task id
665 system.cpu2.icache.tags.occ_task_id_percent::1024 0.156250 # Percentage of cache occupancy per task id
666 system.cpu2.icache.tags.tag_accesses 167724 # Number of tag accesses
667 system.cpu2.icache.tags.data_accesses 167724 # Number of data accesses
668 system.cpu2.icache.ReadReq_hits::cpu2.inst 167008 # number of ReadReq hits
669 system.cpu2.icache.ReadReq_hits::total 167008 # number of ReadReq hits
670 system.cpu2.icache.demand_hits::cpu2.inst 167008 # number of demand (read+write) hits
671 system.cpu2.icache.demand_hits::total 167008 # number of demand (read+write) hits
672 system.cpu2.icache.overall_hits::cpu2.inst 167008 # number of overall hits
673 system.cpu2.icache.overall_hits::total 167008 # number of overall hits
674 system.cpu2.icache.ReadReq_misses::cpu2.inst 358 # number of ReadReq misses
675 system.cpu2.icache.ReadReq_misses::total 358 # number of ReadReq misses
676 system.cpu2.icache.demand_misses::cpu2.inst 358 # number of demand (read+write) misses
677 system.cpu2.icache.demand_misses::total 358 # number of demand (read+write) misses
678 system.cpu2.icache.overall_misses::cpu2.inst 358 # number of overall misses
679 system.cpu2.icache.overall_misses::total 358 # number of overall misses
680 system.cpu2.icache.ReadReq_accesses::cpu2.inst 167366 # number of ReadReq accesses(hits+misses)
681 system.cpu2.icache.ReadReq_accesses::total 167366 # number of ReadReq accesses(hits+misses)
682 system.cpu2.icache.demand_accesses::cpu2.inst 167366 # number of demand (read+write) accesses
683 system.cpu2.icache.demand_accesses::total 167366 # number of demand (read+write) accesses
684 system.cpu2.icache.overall_accesses::cpu2.inst 167366 # number of overall (read+write) accesses
685 system.cpu2.icache.overall_accesses::total 167366 # number of overall (read+write) accesses
686 system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002139 # miss rate for ReadReq accesses
687 system.cpu2.icache.ReadReq_miss_rate::total 0.002139 # miss rate for ReadReq accesses
688 system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002139 # miss rate for demand accesses
689 system.cpu2.icache.demand_miss_rate::total 0.002139 # miss rate for demand accesses
690 system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002139 # miss rate for overall accesses
691 system.cpu2.icache.overall_miss_rate::total 0.002139 # miss rate for overall accesses
692 system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
693 system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
694 system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked
695 system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked
696 system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
697 system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
698 system.cpu2.icache.fast_writes 0 # number of fast writes performed
699 system.cpu2.icache.cache_copies 0 # number of cache copies performed
700 system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate
701 system.cpu2.dcache.tags.replacements 0 # number of replacements
702 system.cpu2.dcache.tags.tagsinuse 29.605505 # Cycle average of tags in use
703 system.cpu2.dcache.tags.total_refs 33613 # Total number of references to valid blocks.
704 system.cpu2.dcache.tags.sampled_refs 26 # Sample count of references to valid blocks.
705 system.cpu2.dcache.tags.avg_refs 1292.807692 # Average number of references to valid blocks.
706 system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
707 system.cpu2.dcache.tags.occ_blocks::cpu2.data 29.605505 # Average occupied blocks per requestor
708 system.cpu2.dcache.tags.occ_percent::cpu2.data 0.057823 # Average percentage of cache occupancy
709 system.cpu2.dcache.tags.occ_percent::total 0.057823 # Average percentage of cache occupancy
710 system.cpu2.dcache.tags.occ_task_id_blocks::1024 26 # Occupied blocks per task id
711 system.cpu2.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id
712 system.cpu2.dcache.tags.occ_task_id_percent::1024 0.050781 # Percentage of cache occupancy per task id
713 system.cpu2.dcache.tags.tag_accesses 234360 # Number of tag accesses
714 system.cpu2.dcache.tags.data_accesses 234360 # Number of data accesses
715 system.cpu2.dcache.ReadReq_hits::cpu2.data 42194 # number of ReadReq hits
716 system.cpu2.dcache.ReadReq_hits::total 42194 # number of ReadReq hits
717 system.cpu2.dcache.WriteReq_hits::cpu2.data 15998 # number of WriteReq hits
718 system.cpu2.dcache.WriteReq_hits::total 15998 # number of WriteReq hits
719 system.cpu2.dcache.SwapReq_hits::cpu2.data 11 # number of SwapReq hits
720 system.cpu2.dcache.SwapReq_hits::total 11 # number of SwapReq hits
721 system.cpu2.dcache.demand_hits::cpu2.data 58192 # number of demand (read+write) hits
722 system.cpu2.dcache.demand_hits::total 58192 # number of demand (read+write) hits
723 system.cpu2.dcache.overall_hits::cpu2.data 58192 # number of overall hits
724 system.cpu2.dcache.overall_hits::total 58192 # number of overall hits
725 system.cpu2.dcache.ReadReq_misses::cpu2.data 160 # number of ReadReq misses
726 system.cpu2.dcache.ReadReq_misses::total 160 # number of ReadReq misses
727 system.cpu2.dcache.WriteReq_misses::cpu2.data 109 # number of WriteReq misses
728 system.cpu2.dcache.WriteReq_misses::total 109 # number of WriteReq misses
729 system.cpu2.dcache.SwapReq_misses::cpu2.data 55 # number of SwapReq misses
730 system.cpu2.dcache.SwapReq_misses::total 55 # number of SwapReq misses
731 system.cpu2.dcache.demand_misses::cpu2.data 269 # number of demand (read+write) misses
732 system.cpu2.dcache.demand_misses::total 269 # number of demand (read+write) misses
733 system.cpu2.dcache.overall_misses::cpu2.data 269 # number of overall misses
734 system.cpu2.dcache.overall_misses::total 269 # number of overall misses
735 system.cpu2.dcache.ReadReq_accesses::cpu2.data 42354 # number of ReadReq accesses(hits+misses)
736 system.cpu2.dcache.ReadReq_accesses::total 42354 # number of ReadReq accesses(hits+misses)
737 system.cpu2.dcache.WriteReq_accesses::cpu2.data 16107 # number of WriteReq accesses(hits+misses)
738 system.cpu2.dcache.WriteReq_accesses::total 16107 # number of WriteReq accesses(hits+misses)
739 system.cpu2.dcache.SwapReq_accesses::cpu2.data 66 # number of SwapReq accesses(hits+misses)
740 system.cpu2.dcache.SwapReq_accesses::total 66 # number of SwapReq accesses(hits+misses)
741 system.cpu2.dcache.demand_accesses::cpu2.data 58461 # number of demand (read+write) accesses
742 system.cpu2.dcache.demand_accesses::total 58461 # number of demand (read+write) accesses
743 system.cpu2.dcache.overall_accesses::cpu2.data 58461 # number of overall (read+write) accesses
744 system.cpu2.dcache.overall_accesses::total 58461 # number of overall (read+write) accesses
745 system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003778 # miss rate for ReadReq accesses
746 system.cpu2.dcache.ReadReq_miss_rate::total 0.003778 # miss rate for ReadReq accesses
747 system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.006767 # miss rate for WriteReq accesses
748 system.cpu2.dcache.WriteReq_miss_rate::total 0.006767 # miss rate for WriteReq accesses
749 system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.833333 # miss rate for SwapReq accesses
750 system.cpu2.dcache.SwapReq_miss_rate::total 0.833333 # miss rate for SwapReq accesses
751 system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004601 # miss rate for demand accesses
752 system.cpu2.dcache.demand_miss_rate::total 0.004601 # miss rate for demand accesses
753 system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004601 # miss rate for overall accesses
754 system.cpu2.dcache.overall_miss_rate::total 0.004601 # miss rate for overall accesses
755 system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
756 system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
757 system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
758 system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked
759 system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
760 system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
761 system.cpu2.dcache.fast_writes 0 # number of fast writes performed
762 system.cpu2.dcache.cache_copies 0 # number of cache copies performed
763 system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
764 system.cpu3.numCycles 173294 # number of cpu cycles simulated
765 system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
766 system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed
767 system.cpu3.committedInsts 167269 # Number of instructions committed
768 system.cpu3.committedOps 167269 # Number of ops (including micro ops) committed
769 system.cpu3.num_int_alu_accesses 111554 # Number of integer alu accesses
770 system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses
771 system.cpu3.num_func_calls 633 # number of times a function call or return occured
772 system.cpu3.num_conditional_control_insts 31865 # number of instructions that are conditional controls
773 system.cpu3.num_int_insts 111554 # number of integer instructions
774 system.cpu3.num_fp_insts 0 # number of float instructions
775 system.cpu3.num_int_register_reads 280060 # number of times the integer registers were read
776 system.cpu3.num_int_register_writes 104916 # number of times the integer registers were written
777 system.cpu3.num_fp_register_reads 0 # number of times the floating registers were read
778 system.cpu3.num_fp_register_writes 0 # number of times the floating registers were written
779 system.cpu3.num_mem_refs 55900 # number of memory refs
780 system.cpu3.num_load_insts 41466 # Number of load instructions
781 system.cpu3.num_store_insts 14434 # Number of store instructions
782 system.cpu3.num_idle_cycles 8001.119846 # Number of idle cycles
783 system.cpu3.num_busy_cycles 165292.880154 # Number of busy cycles
784 system.cpu3.not_idle_fraction 0.953829 # Percentage of non-idle cycles
785 system.cpu3.idle_fraction 0.046171 # Percentage of idle cycles
786 system.cpu3.Branches 33511 # Number of branches fetched
787 system.cpu3.op_class::No_OpClass 24299 14.52% 14.52% # Class of executed instruction
788 system.cpu3.op_class::IntAlu 73982 44.22% 58.75% # Class of executed instruction
789 system.cpu3.op_class::IntMult 0 0.00% 58.75% # Class of executed instruction
790 system.cpu3.op_class::IntDiv 0 0.00% 58.75% # Class of executed instruction
791 system.cpu3.op_class::FloatAdd 0 0.00% 58.75% # Class of executed instruction
792 system.cpu3.op_class::FloatCmp 0 0.00% 58.75% # Class of executed instruction
793 system.cpu3.op_class::FloatCvt 0 0.00% 58.75% # Class of executed instruction
794 system.cpu3.op_class::FloatMult 0 0.00% 58.75% # Class of executed instruction
795 system.cpu3.op_class::FloatDiv 0 0.00% 58.75% # Class of executed instruction
796 system.cpu3.op_class::FloatSqrt 0 0.00% 58.75% # Class of executed instruction
797 system.cpu3.op_class::SimdAdd 0 0.00% 58.75% # Class of executed instruction
798 system.cpu3.op_class::SimdAddAcc 0 0.00% 58.75% # Class of executed instruction
799 system.cpu3.op_class::SimdAlu 0 0.00% 58.75% # Class of executed instruction
800 system.cpu3.op_class::SimdCmp 0 0.00% 58.75% # Class of executed instruction
801 system.cpu3.op_class::SimdCvt 0 0.00% 58.75% # Class of executed instruction
802 system.cpu3.op_class::SimdMisc 0 0.00% 58.75% # Class of executed instruction
803 system.cpu3.op_class::SimdMult 0 0.00% 58.75% # Class of executed instruction
804 system.cpu3.op_class::SimdMultAcc 0 0.00% 58.75% # Class of executed instruction
805 system.cpu3.op_class::SimdShift 0 0.00% 58.75% # Class of executed instruction
806 system.cpu3.op_class::SimdShiftAcc 0 0.00% 58.75% # Class of executed instruction
807 system.cpu3.op_class::SimdSqrt 0 0.00% 58.75% # Class of executed instruction
808 system.cpu3.op_class::SimdFloatAdd 0 0.00% 58.75% # Class of executed instruction
809 system.cpu3.op_class::SimdFloatAlu 0 0.00% 58.75% # Class of executed instruction
810 system.cpu3.op_class::SimdFloatCmp 0 0.00% 58.75% # Class of executed instruction
811 system.cpu3.op_class::SimdFloatCvt 0 0.00% 58.75% # Class of executed instruction
812 system.cpu3.op_class::SimdFloatDiv 0 0.00% 58.75% # Class of executed instruction
813 system.cpu3.op_class::SimdFloatMisc 0 0.00% 58.75% # Class of executed instruction
814 system.cpu3.op_class::SimdFloatMult 0 0.00% 58.75% # Class of executed instruction
815 system.cpu3.op_class::SimdFloatMultAcc 0 0.00% 58.75% # Class of executed instruction
816 system.cpu3.op_class::SimdFloatSqrt 0 0.00% 58.75% # Class of executed instruction
817 system.cpu3.op_class::MemRead 54586 32.63% 91.37% # Class of executed instruction
818 system.cpu3.op_class::MemWrite 14434 8.63% 100.00% # Class of executed instruction
819 system.cpu3.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
820 system.cpu3.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
821 system.cpu3.op_class::total 167301 # Class of executed instruction
822 system.cpu3.icache.tags.replacements 279 # number of replacements
823 system.cpu3.icache.tags.tagsinuse 72.874497 # Cycle average of tags in use
824 system.cpu3.icache.tags.total_refs 166942 # Total number of references to valid blocks.
825 system.cpu3.icache.tags.sampled_refs 359 # Sample count of references to valid blocks.
826 system.cpu3.icache.tags.avg_refs 465.019499 # Average number of references to valid blocks.
827 system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
828 system.cpu3.icache.tags.occ_blocks::cpu3.inst 72.874497 # Average occupied blocks per requestor
829 system.cpu3.icache.tags.occ_percent::cpu3.inst 0.142333 # Average percentage of cache occupancy
830 system.cpu3.icache.tags.occ_percent::total 0.142333 # Average percentage of cache occupancy
831 system.cpu3.icache.tags.occ_task_id_blocks::1024 80 # Occupied blocks per task id
832 system.cpu3.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id
833 system.cpu3.icache.tags.age_task_id_blocks_1024::1 71 # Occupied blocks per task id
834 system.cpu3.icache.tags.occ_task_id_percent::1024 0.156250 # Percentage of cache occupancy per task id
835 system.cpu3.icache.tags.tag_accesses 167660 # Number of tag accesses
836 system.cpu3.icache.tags.data_accesses 167660 # Number of data accesses
837 system.cpu3.icache.ReadReq_hits::cpu3.inst 166942 # number of ReadReq hits
838 system.cpu3.icache.ReadReq_hits::total 166942 # number of ReadReq hits
839 system.cpu3.icache.demand_hits::cpu3.inst 166942 # number of demand (read+write) hits
840 system.cpu3.icache.demand_hits::total 166942 # number of demand (read+write) hits
841 system.cpu3.icache.overall_hits::cpu3.inst 166942 # number of overall hits
842 system.cpu3.icache.overall_hits::total 166942 # number of overall hits
843 system.cpu3.icache.ReadReq_misses::cpu3.inst 359 # number of ReadReq misses
844 system.cpu3.icache.ReadReq_misses::total 359 # number of ReadReq misses
845 system.cpu3.icache.demand_misses::cpu3.inst 359 # number of demand (read+write) misses
846 system.cpu3.icache.demand_misses::total 359 # number of demand (read+write) misses
847 system.cpu3.icache.overall_misses::cpu3.inst 359 # number of overall misses
848 system.cpu3.icache.overall_misses::total 359 # number of overall misses
849 system.cpu3.icache.ReadReq_accesses::cpu3.inst 167301 # number of ReadReq accesses(hits+misses)
850 system.cpu3.icache.ReadReq_accesses::total 167301 # number of ReadReq accesses(hits+misses)
851 system.cpu3.icache.demand_accesses::cpu3.inst 167301 # number of demand (read+write) accesses
852 system.cpu3.icache.demand_accesses::total 167301 # number of demand (read+write) accesses
853 system.cpu3.icache.overall_accesses::cpu3.inst 167301 # number of overall (read+write) accesses
854 system.cpu3.icache.overall_accesses::total 167301 # number of overall (read+write) accesses
855 system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002146 # miss rate for ReadReq accesses
856 system.cpu3.icache.ReadReq_miss_rate::total 0.002146 # miss rate for ReadReq accesses
857 system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002146 # miss rate for demand accesses
858 system.cpu3.icache.demand_miss_rate::total 0.002146 # miss rate for demand accesses
859 system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002146 # miss rate for overall accesses
860 system.cpu3.icache.overall_miss_rate::total 0.002146 # miss rate for overall accesses
861 system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
862 system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
863 system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked
864 system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked
865 system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
866 system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
867 system.cpu3.icache.fast_writes 0 # number of fast writes performed
868 system.cpu3.icache.cache_copies 0 # number of cache copies performed
869 system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate
870 system.cpu3.dcache.tags.replacements 0 # number of replacements
871 system.cpu3.dcache.tags.tagsinuse 28.795404 # Cycle average of tags in use
872 system.cpu3.dcache.tags.total_refs 30236 # Total number of references to valid blocks.
873 system.cpu3.dcache.tags.sampled_refs 27 # Sample count of references to valid blocks.
874 system.cpu3.dcache.tags.avg_refs 1119.851852 # Average number of references to valid blocks.
875 system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
876 system.cpu3.dcache.tags.occ_blocks::cpu3.data 28.795404 # Average occupied blocks per requestor
877 system.cpu3.dcache.tags.occ_percent::cpu3.data 0.056241 # Average percentage of cache occupancy
878 system.cpu3.dcache.tags.occ_percent::total 0.056241 # Average percentage of cache occupancy
879 system.cpu3.dcache.tags.occ_task_id_blocks::1024 27 # Occupied blocks per task id
880 system.cpu3.dcache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id
881 system.cpu3.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id
882 system.cpu3.dcache.tags.occ_task_id_percent::1024 0.052734 # Percentage of cache occupancy per task id
883 system.cpu3.dcache.tags.tag_accesses 223805 # Number of tag accesses
884 system.cpu3.dcache.tags.data_accesses 223805 # Number of data accesses
885 system.cpu3.dcache.ReadReq_hits::cpu3.data 41301 # number of ReadReq hits
886 system.cpu3.dcache.ReadReq_hits::total 41301 # number of ReadReq hits
887 system.cpu3.dcache.WriteReq_hits::cpu3.data 14260 # number of WriteReq hits
888 system.cpu3.dcache.WriteReq_hits::total 14260 # number of WriteReq hits
889 system.cpu3.dcache.SwapReq_hits::cpu3.data 15 # number of SwapReq hits
890 system.cpu3.dcache.SwapReq_hits::total 15 # number of SwapReq hits
891 system.cpu3.dcache.demand_hits::cpu3.data 55561 # number of demand (read+write) hits
892 system.cpu3.dcache.demand_hits::total 55561 # number of demand (read+write) hits
893 system.cpu3.dcache.overall_hits::cpu3.data 55561 # number of overall hits
894 system.cpu3.dcache.overall_hits::total 55561 # number of overall hits
895 system.cpu3.dcache.ReadReq_misses::cpu3.data 157 # number of ReadReq misses
896 system.cpu3.dcache.ReadReq_misses::total 157 # number of ReadReq misses
897 system.cpu3.dcache.WriteReq_misses::cpu3.data 102 # number of WriteReq misses
898 system.cpu3.dcache.WriteReq_misses::total 102 # number of WriteReq misses
899 system.cpu3.dcache.SwapReq_misses::cpu3.data 55 # number of SwapReq misses
900 system.cpu3.dcache.SwapReq_misses::total 55 # number of SwapReq misses
901 system.cpu3.dcache.demand_misses::cpu3.data 259 # number of demand (read+write) misses
902 system.cpu3.dcache.demand_misses::total 259 # number of demand (read+write) misses
903 system.cpu3.dcache.overall_misses::cpu3.data 259 # number of overall misses
904 system.cpu3.dcache.overall_misses::total 259 # number of overall misses
905 system.cpu3.dcache.ReadReq_accesses::cpu3.data 41458 # number of ReadReq accesses(hits+misses)
906 system.cpu3.dcache.ReadReq_accesses::total 41458 # number of ReadReq accesses(hits+misses)
907 system.cpu3.dcache.WriteReq_accesses::cpu3.data 14362 # number of WriteReq accesses(hits+misses)
908 system.cpu3.dcache.WriteReq_accesses::total 14362 # number of WriteReq accesses(hits+misses)
909 system.cpu3.dcache.SwapReq_accesses::cpu3.data 70 # number of SwapReq accesses(hits+misses)
910 system.cpu3.dcache.SwapReq_accesses::total 70 # number of SwapReq accesses(hits+misses)
911 system.cpu3.dcache.demand_accesses::cpu3.data 55820 # number of demand (read+write) accesses
912 system.cpu3.dcache.demand_accesses::total 55820 # number of demand (read+write) accesses
913 system.cpu3.dcache.overall_accesses::cpu3.data 55820 # number of overall (read+write) accesses
914 system.cpu3.dcache.overall_accesses::total 55820 # number of overall (read+write) accesses
915 system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.003787 # miss rate for ReadReq accesses
916 system.cpu3.dcache.ReadReq_miss_rate::total 0.003787 # miss rate for ReadReq accesses
917 system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.007102 # miss rate for WriteReq accesses
918 system.cpu3.dcache.WriteReq_miss_rate::total 0.007102 # miss rate for WriteReq accesses
919 system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.785714 # miss rate for SwapReq accesses
920 system.cpu3.dcache.SwapReq_miss_rate::total 0.785714 # miss rate for SwapReq accesses
921 system.cpu3.dcache.demand_miss_rate::cpu3.data 0.004640 # miss rate for demand accesses
922 system.cpu3.dcache.demand_miss_rate::total 0.004640 # miss rate for demand accesses
923 system.cpu3.dcache.overall_miss_rate::cpu3.data 0.004640 # miss rate for overall accesses
924 system.cpu3.dcache.overall_miss_rate::total 0.004640 # miss rate for overall accesses
925 system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
926 system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
927 system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
928 system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked
929 system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
930 system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
931 system.cpu3.dcache.fast_writes 0 # number of fast writes performed
932 system.cpu3.dcache.cache_copies 0 # number of cache copies performed
933 system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
935 ---------- End Simulation Statistics ----------
projects / gem5.git / blob