tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 eventq_index=0
   5 full_system=false
   6 sim_quantum=0
   7 time_sync_enable=false
   8 time_sync_period=100000000000
   9 time_sync_spin_threshold=100000000
  10
  11 [system]
  12 type=System
  13 children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu_clk_domain dvfs_handler l2c membus physmem toL2Bus voltage_domain
  14 boot_osflags=a
  15 cache_line_size=64
  16 clk_domain=system.clk_domain
  17 default_p_state=UNDEFINED
  18 eventq_index=0
  19 exit_on_work_items=false
  20 init_param=0
  21 kernel=
  22 kernel_addr_check=true
  23 load_addr_mask=1099511627775
  24 load_offset=0
  25 mem_mode=timing
  26 mem_ranges=
  27 memories=system.physmem
  28 mmap_using_noreserve=false
  29 multi_thread=false
  30 num_work_ids=16
  31 p_state_clk_gate_bins=20
  32 p_state_clk_gate_max=1000000000000
  33 p_state_clk_gate_min=1000
  34 power_model=Null
  35 readfile=
  36 symbolfile=
  37 thermal_components=
  38 thermal_model=Null
  39 work_begin_ckpt_count=0
  40 work_begin_cpu_id_exit=-1
  41 work_begin_exit_count=0
  42 work_cpus_ckpt_count=0
  43 work_end_ckpt_count=0
  44 work_end_exit_count=0
  45 work_item_id=-1
  46 system_port=system.membus.slave[0]
  47
  48 [system.clk_domain]
  49 type=SrcClockDomain
  50 clock=1000
  51 domain_id=-1
  52 eventq_index=0
  53 init_perf_level=0
  54 voltage_domain=system.voltage_domain
  55
  56 [system.cpu0]
  57 type=TimingSimpleCPU
  58 children=dcache dtb icache interrupts isa itb tracer workload
  59 branchPred=Null
  60 checker=Null
  61 clk_domain=system.cpu_clk_domain
  62 cpu_id=0
  63 default_p_state=UNDEFINED
  64 do_checkpoint_insts=true
  65 do_quiesce=true
  66 do_statistics_insts=true
  67 dtb=system.cpu0.dtb
  68 eventq_index=0
  69 function_trace=false
  70 function_trace_start=0
  71 interrupts=system.cpu0.interrupts
  72 isa=system.cpu0.isa
  73 itb=system.cpu0.itb
  74 max_insts_all_threads=0
  75 max_insts_any_thread=0
  76 max_loads_all_threads=0
  77 max_loads_any_thread=0
  78 numThreads=1
  79 p_state_clk_gate_bins=20
  80 p_state_clk_gate_max=1000000000000
  81 p_state_clk_gate_min=1000
  82 power_model=Null
  83 profile=0
  84 progress_interval=0
  85 simpoint_start_insts=
  86 socket_id=0
  87 switched_out=false
  88 syscallRetryLatency=10000
  89 system=system
  90 tracer=system.cpu0.tracer
  91 workload=system.cpu0.workload
  92 dcache_port=system.cpu0.dcache.cpu_side
  93 icache_port=system.cpu0.icache.cpu_side
  94
  95 [system.cpu0.dcache]
  96 type=Cache
  97 children=tags
  98 addr_ranges=0:18446744073709551615:0:0:0:0
  99 assoc=4
 100 clk_domain=system.cpu_clk_domain
 101 clusivity=mostly_incl
 102 data_latency=2
 103 default_p_state=UNDEFINED
 104 demand_mshr_reserve=1
 105 eventq_index=0
 106 is_read_only=false
 107 max_miss_count=0
 108 mshrs=4
 109 p_state_clk_gate_bins=20
 110 p_state_clk_gate_max=1000000000000
 111 p_state_clk_gate_min=1000
 112 power_model=Null
 113 prefetch_on_access=false
 114 prefetcher=Null
 115 response_latency=2
 116 sequential_access=false
 117 size=32768
 118 system=system
 119 tag_latency=2
 120 tags=system.cpu0.dcache.tags
 121 tgts_per_mshr=20
 122 write_buffers=8
 123 writeback_clean=false
 124 cpu_side=system.cpu0.dcache_port
 125 mem_side=system.toL2Bus.slave[1]
 126
 127 [system.cpu0.dcache.tags]
 128 type=LRU
 129 assoc=4
 130 block_size=64
 131 clk_domain=system.cpu_clk_domain
 132 data_latency=2
 133 default_p_state=UNDEFINED
 134 eventq_index=0
 135 p_state_clk_gate_bins=20
 136 p_state_clk_gate_max=1000000000000
 137 p_state_clk_gate_min=1000
 138 power_model=Null
 139 sequential_access=false
 140 size=32768
 141 tag_latency=2
 142
 143 [system.cpu0.dtb]
 144 type=SparcTLB
 145 eventq_index=0
 146 size=64
 147
 148 [system.cpu0.icache]
 149 type=Cache
 150 children=tags
 151 addr_ranges=0:18446744073709551615:0:0:0:0
 152 assoc=1
 153 clk_domain=system.cpu_clk_domain
 154 clusivity=mostly_incl
 155 data_latency=2
 156 default_p_state=UNDEFINED
 157 demand_mshr_reserve=1
 158 eventq_index=0
 159 is_read_only=true
 160 max_miss_count=0
 161 mshrs=4
 162 p_state_clk_gate_bins=20
 163 p_state_clk_gate_max=1000000000000
 164 p_state_clk_gate_min=1000
 165 power_model=Null
 166 prefetch_on_access=false
 167 prefetcher=Null
 168 response_latency=2
 169 sequential_access=false
 170 size=32768
 171 system=system
 172 tag_latency=2
 173 tags=system.cpu0.icache.tags
 174 tgts_per_mshr=20
 175 write_buffers=8
 176 writeback_clean=true
 177 cpu_side=system.cpu0.icache_port
 178 mem_side=system.toL2Bus.slave[0]
 179
 180 [system.cpu0.icache.tags]
 181 type=LRU
 182 assoc=1
 183 block_size=64
 184 clk_domain=system.cpu_clk_domain
 185 data_latency=2
 186 default_p_state=UNDEFINED
 187 eventq_index=0
 188 p_state_clk_gate_bins=20
 189 p_state_clk_gate_max=1000000000000
 190 p_state_clk_gate_min=1000
 191 power_model=Null
 192 sequential_access=false
 193 size=32768
 194 tag_latency=2
 195
 196 [system.cpu0.interrupts]
 197 type=SparcInterrupts
 198 eventq_index=0
 199
 200 [system.cpu0.isa]
 201 type=SparcISA
 202 eventq_index=0
 203
 204 [system.cpu0.itb]
 205 type=SparcTLB
 206 eventq_index=0
 207 size=64
 208
 209 [system.cpu0.tracer]
 210 type=ExeTracer
 211 eventq_index=0
 212
 213 [system.cpu0.workload]
 214 type=Process
 215 cmd=test_atomic 4
 216 cwd=
 217 drivers=
 218 egid=100
 219 env=
 220 errout=cerr
 221 euid=100
 222 eventq_index=0
 223 executable=/usr/local/google/home/gabeblack/gem5/dist/m5/regression/test-progs/m5threads/bin/sparc/linux/test_atomic
 224 gid=100
 225 input=cin
 226 kvmInSE=false
 227 maxStackSize=67108864
 228 output=cout
 229 pgid=100
 230 pid=100
 231 ppid=0
 232 simpoint=0
 233 system=system
 234 uid=100
 235 useArchPT=false
 236
 237 [system.cpu1]
 238 type=TimingSimpleCPU
 239 children=dcache dtb icache interrupts isa itb tracer
 240 branchPred=Null
 241 checker=Null
 242 clk_domain=system.cpu_clk_domain
 243 cpu_id=1
 244 default_p_state=UNDEFINED
 245 do_checkpoint_insts=true
 246 do_quiesce=true
 247 do_statistics_insts=true
 248 dtb=system.cpu1.dtb
 249 eventq_index=0
 250 function_trace=false
 251 function_trace_start=0
 252 interrupts=system.cpu1.interrupts
 253 isa=system.cpu1.isa
 254 itb=system.cpu1.itb
 255 max_insts_all_threads=0
 256 max_insts_any_thread=0
 257 max_loads_all_threads=0
 258 max_loads_any_thread=0
 259 numThreads=1
 260 p_state_clk_gate_bins=20
 261 p_state_clk_gate_max=1000000000000
 262 p_state_clk_gate_min=1000
 263 power_model=Null
 264 profile=0
 265 progress_interval=0
 266 simpoint_start_insts=
 267 socket_id=0
 268 switched_out=false
 269 syscallRetryLatency=10000
 270 system=system
 271 tracer=system.cpu1.tracer
 272 workload=system.cpu0.workload
 273 dcache_port=system.cpu1.dcache.cpu_side
 274 icache_port=system.cpu1.icache.cpu_side
 275
 276 [system.cpu1.dcache]
 277 type=Cache
 278 children=tags
 279 addr_ranges=0:18446744073709551615:0:0:0:0
 280 assoc=4
 281 clk_domain=system.cpu_clk_domain
 282 clusivity=mostly_incl
 283 data_latency=2
 284 default_p_state=UNDEFINED
 285 demand_mshr_reserve=1
 286 eventq_index=0
 287 is_read_only=false
 288 max_miss_count=0
 289 mshrs=4
 290 p_state_clk_gate_bins=20
 291 p_state_clk_gate_max=1000000000000
 292 p_state_clk_gate_min=1000
 293 power_model=Null
 294 prefetch_on_access=false
 295 prefetcher=Null
 296 response_latency=2
 297 sequential_access=false
 298 size=32768
 299 system=system
 300 tag_latency=2
 301 tags=system.cpu1.dcache.tags
 302 tgts_per_mshr=20
 303 write_buffers=8
 304 writeback_clean=false
 305 cpu_side=system.cpu1.dcache_port
 306 mem_side=system.toL2Bus.slave[3]
 307
 308 [system.cpu1.dcache.tags]
 309 type=LRU
 310 assoc=4
 311 block_size=64
 312 clk_domain=system.cpu_clk_domain
 313 data_latency=2
 314 default_p_state=UNDEFINED
 315 eventq_index=0
 316 p_state_clk_gate_bins=20
 317 p_state_clk_gate_max=1000000000000
 318 p_state_clk_gate_min=1000
 319 power_model=Null
 320 sequential_access=false
 321 size=32768
 322 tag_latency=2
 323
 324 [system.cpu1.dtb]
 325 type=SparcTLB
 326 eventq_index=0
 327 size=64
 328
 329 [system.cpu1.icache]
 330 type=Cache
 331 children=tags
 332 addr_ranges=0:18446744073709551615:0:0:0:0
 333 assoc=1
 334 clk_domain=system.cpu_clk_domain
 335 clusivity=mostly_incl
 336 data_latency=2
 337 default_p_state=UNDEFINED
 338 demand_mshr_reserve=1
 339 eventq_index=0
 340 is_read_only=true
 341 max_miss_count=0
 342 mshrs=4
 343 p_state_clk_gate_bins=20
 344 p_state_clk_gate_max=1000000000000
 345 p_state_clk_gate_min=1000
 346 power_model=Null
 347 prefetch_on_access=false
 348 prefetcher=Null
 349 response_latency=2
 350 sequential_access=false
 351 size=32768
 352 system=system
 353 tag_latency=2
 354 tags=system.cpu1.icache.tags
 355 tgts_per_mshr=20
 356 write_buffers=8
 357 writeback_clean=true
 358 cpu_side=system.cpu1.icache_port
 359 mem_side=system.toL2Bus.slave[2]
 360
 361 [system.cpu1.icache.tags]
 362 type=LRU
 363 assoc=1
 364 block_size=64
 365 clk_domain=system.cpu_clk_domain
 366 data_latency=2
 367 default_p_state=UNDEFINED
 368 eventq_index=0
 369 p_state_clk_gate_bins=20
 370 p_state_clk_gate_max=1000000000000
 371 p_state_clk_gate_min=1000
 372 power_model=Null
 373 sequential_access=false
 374 size=32768
 375 tag_latency=2
 376
 377 [system.cpu1.interrupts]
 378 type=SparcInterrupts
 379 eventq_index=0
 380
 381 [system.cpu1.isa]
 382 type=SparcISA
 383 eventq_index=0
 384
 385 [system.cpu1.itb]
 386 type=SparcTLB
 387 eventq_index=0
 388 size=64
 389
 390 [system.cpu1.tracer]
 391 type=ExeTracer
 392 eventq_index=0
 393
 394 [system.cpu2]
 395 type=TimingSimpleCPU
 396 children=dcache dtb icache interrupts isa itb tracer
 397 branchPred=Null
 398 checker=Null
 399 clk_domain=system.cpu_clk_domain
 400 cpu_id=2
 401 default_p_state=UNDEFINED
 402 do_checkpoint_insts=true
 403 do_quiesce=true
 404 do_statistics_insts=true
 405 dtb=system.cpu2.dtb
 406 eventq_index=0
 407 function_trace=false
 408 function_trace_start=0
 409 interrupts=system.cpu2.interrupts
 410 isa=system.cpu2.isa
 411 itb=system.cpu2.itb
 412 max_insts_all_threads=0
 413 max_insts_any_thread=0
 414 max_loads_all_threads=0
 415 max_loads_any_thread=0
 416 numThreads=1
 417 p_state_clk_gate_bins=20
 418 p_state_clk_gate_max=1000000000000
 419 p_state_clk_gate_min=1000
 420 power_model=Null
 421 profile=0
 422 progress_interval=0
 423 simpoint_start_insts=
 424 socket_id=0
 425 switched_out=false
 426 syscallRetryLatency=10000
 427 system=system
 428 tracer=system.cpu2.tracer
 429 workload=system.cpu0.workload
 430 dcache_port=system.cpu2.dcache.cpu_side
 431 icache_port=system.cpu2.icache.cpu_side
 432
 433 [system.cpu2.dcache]
 434 type=Cache
 435 children=tags
 436 addr_ranges=0:18446744073709551615:0:0:0:0
 437 assoc=4
 438 clk_domain=system.cpu_clk_domain
 439 clusivity=mostly_incl
 440 data_latency=2
 441 default_p_state=UNDEFINED
 442 demand_mshr_reserve=1
 443 eventq_index=0
 444 is_read_only=false
 445 max_miss_count=0
 446 mshrs=4
 447 p_state_clk_gate_bins=20
 448 p_state_clk_gate_max=1000000000000
 449 p_state_clk_gate_min=1000
 450 power_model=Null
 451 prefetch_on_access=false
 452 prefetcher=Null
 453 response_latency=2
 454 sequential_access=false
 455 size=32768
 456 system=system
 457 tag_latency=2
 458 tags=system.cpu2.dcache.tags
 459 tgts_per_mshr=20
 460 write_buffers=8
 461 writeback_clean=false
 462 cpu_side=system.cpu2.dcache_port
 463 mem_side=system.toL2Bus.slave[5]
 464
 465 [system.cpu2.dcache.tags]
 466 type=LRU
 467 assoc=4
 468 block_size=64
 469 clk_domain=system.cpu_clk_domain
 470 data_latency=2
 471 default_p_state=UNDEFINED
 472 eventq_index=0
 473 p_state_clk_gate_bins=20
 474 p_state_clk_gate_max=1000000000000
 475 p_state_clk_gate_min=1000
 476 power_model=Null
 477 sequential_access=false
 478 size=32768
 479 tag_latency=2
 480
 481 [system.cpu2.dtb]
 482 type=SparcTLB
 483 eventq_index=0
 484 size=64
 485
 486 [system.cpu2.icache]
 487 type=Cache
 488 children=tags
 489 addr_ranges=0:18446744073709551615:0:0:0:0
 490 assoc=1
 491 clk_domain=system.cpu_clk_domain
 492 clusivity=mostly_incl
 493 data_latency=2
 494 default_p_state=UNDEFINED
 495 demand_mshr_reserve=1
 496 eventq_index=0
 497 is_read_only=true
 498 max_miss_count=0
 499 mshrs=4
 500 p_state_clk_gate_bins=20
 501 p_state_clk_gate_max=1000000000000
 502 p_state_clk_gate_min=1000
 503 power_model=Null
 504 prefetch_on_access=false
 505 prefetcher=Null
 506 response_latency=2
 507 sequential_access=false
 508 size=32768
 509 system=system
 510 tag_latency=2
 511 tags=system.cpu2.icache.tags
 512 tgts_per_mshr=20
 513 write_buffers=8
 514 writeback_clean=true
 515 cpu_side=system.cpu2.icache_port
 516 mem_side=system.toL2Bus.slave[4]
 517
 518 [system.cpu2.icache.tags]
 519 type=LRU
 520 assoc=1
 521 block_size=64
 522 clk_domain=system.cpu_clk_domain
 523 data_latency=2
 524 default_p_state=UNDEFINED
 525 eventq_index=0
 526 p_state_clk_gate_bins=20
 527 p_state_clk_gate_max=1000000000000
 528 p_state_clk_gate_min=1000
 529 power_model=Null
 530 sequential_access=false
 531 size=32768
 532 tag_latency=2
 533
 534 [system.cpu2.interrupts]
 535 type=SparcInterrupts
 536 eventq_index=0
 537
 538 [system.cpu2.isa]
 539 type=SparcISA
 540 eventq_index=0
 541
 542 [system.cpu2.itb]
 543 type=SparcTLB
 544 eventq_index=0
 545 size=64
 546
 547 [system.cpu2.tracer]
 548 type=ExeTracer
 549 eventq_index=0
 550
 551 [system.cpu3]
 552 type=TimingSimpleCPU
 553 children=dcache dtb icache interrupts isa itb tracer
 554 branchPred=Null
 555 checker=Null
 556 clk_domain=system.cpu_clk_domain
 557 cpu_id=3
 558 default_p_state=UNDEFINED
 559 do_checkpoint_insts=true
 560 do_quiesce=true
 561 do_statistics_insts=true
 562 dtb=system.cpu3.dtb
 563 eventq_index=0
 564 function_trace=false
 565 function_trace_start=0
 566 interrupts=system.cpu3.interrupts
 567 isa=system.cpu3.isa
 568 itb=system.cpu3.itb
 569 max_insts_all_threads=0
 570 max_insts_any_thread=0
 571 max_loads_all_threads=0
 572 max_loads_any_thread=0
 573 numThreads=1
 574 p_state_clk_gate_bins=20
 575 p_state_clk_gate_max=1000000000000
 576 p_state_clk_gate_min=1000
 577 power_model=Null
 578 profile=0
 579 progress_interval=0
 580 simpoint_start_insts=
 581 socket_id=0
 582 switched_out=false
 583 syscallRetryLatency=10000
 584 system=system
 585 tracer=system.cpu3.tracer
 586 workload=system.cpu0.workload
 587 dcache_port=system.cpu3.dcache.cpu_side
 588 icache_port=system.cpu3.icache.cpu_side
 589
 590 [system.cpu3.dcache]
 591 type=Cache
 592 children=tags
 593 addr_ranges=0:18446744073709551615:0:0:0:0
 594 assoc=4
 595 clk_domain=system.cpu_clk_domain
 596 clusivity=mostly_incl
 597 data_latency=2
 598 default_p_state=UNDEFINED
 599 demand_mshr_reserve=1
 600 eventq_index=0
 601 is_read_only=false
 602 max_miss_count=0
 603 mshrs=4
 604 p_state_clk_gate_bins=20
 605 p_state_clk_gate_max=1000000000000
 606 p_state_clk_gate_min=1000
 607 power_model=Null
 608 prefetch_on_access=false
 609 prefetcher=Null
 610 response_latency=2
 611 sequential_access=false
 612 size=32768
 613 system=system
 614 tag_latency=2
 615 tags=system.cpu3.dcache.tags
 616 tgts_per_mshr=20
 617 write_buffers=8
 618 writeback_clean=false
 619 cpu_side=system.cpu3.dcache_port
 620 mem_side=system.toL2Bus.slave[7]
 621
 622 [system.cpu3.dcache.tags]
 623 type=LRU
 624 assoc=4
 625 block_size=64
 626 clk_domain=system.cpu_clk_domain
 627 data_latency=2
 628 default_p_state=UNDEFINED
 629 eventq_index=0
 630 p_state_clk_gate_bins=20
 631 p_state_clk_gate_max=1000000000000
 632 p_state_clk_gate_min=1000
 633 power_model=Null
 634 sequential_access=false
 635 size=32768
 636 tag_latency=2
 637
 638 [system.cpu3.dtb]
 639 type=SparcTLB
 640 eventq_index=0
 641 size=64
 642
 643 [system.cpu3.icache]
 644 type=Cache
 645 children=tags
 646 addr_ranges=0:18446744073709551615:0:0:0:0
 647 assoc=1
 648 clk_domain=system.cpu_clk_domain
 649 clusivity=mostly_incl
 650 data_latency=2
 651 default_p_state=UNDEFINED
 652 demand_mshr_reserve=1
 653 eventq_index=0
 654 is_read_only=true
 655 max_miss_count=0
 656 mshrs=4
 657 p_state_clk_gate_bins=20
 658 p_state_clk_gate_max=1000000000000
 659 p_state_clk_gate_min=1000
 660 power_model=Null
 661 prefetch_on_access=false
 662 prefetcher=Null
 663 response_latency=2
 664 sequential_access=false
 665 size=32768
 666 system=system
 667 tag_latency=2
 668 tags=system.cpu3.icache.tags
 669 tgts_per_mshr=20
 670 write_buffers=8
 671 writeback_clean=true
 672 cpu_side=system.cpu3.icache_port
 673 mem_side=system.toL2Bus.slave[6]
 674
 675 [system.cpu3.icache.tags]
 676 type=LRU
 677 assoc=1
 678 block_size=64
 679 clk_domain=system.cpu_clk_domain
 680 data_latency=2
 681 default_p_state=UNDEFINED
 682 eventq_index=0
 683 p_state_clk_gate_bins=20
 684 p_state_clk_gate_max=1000000000000
 685 p_state_clk_gate_min=1000
 686 power_model=Null
 687 sequential_access=false
 688 size=32768
 689 tag_latency=2
 690
 691 [system.cpu3.interrupts]
 692 type=SparcInterrupts
 693 eventq_index=0
 694
 695 [system.cpu3.isa]
 696 type=SparcISA
 697 eventq_index=0
 698
 699 [system.cpu3.itb]
 700 type=SparcTLB
 701 eventq_index=0
 702 size=64
 703
 704 [system.cpu3.tracer]
 705 type=ExeTracer
 706 eventq_index=0
 707
 708 [system.cpu_clk_domain]
 709 type=SrcClockDomain
 710 clock=500
 711 domain_id=-1
 712 eventq_index=0
 713 init_perf_level=0
 714 voltage_domain=system.voltage_domain
 715
 716 [system.dvfs_handler]
 717 type=DVFSHandler
 718 domains=
 719 enable=false
 720 eventq_index=0
 721 sys_clk_domain=system.clk_domain
 722 transition_latency=100000000
 723
 724 [system.l2c]
 725 type=Cache
 726 children=tags
 727 addr_ranges=0:18446744073709551615:0:0:0:0
 728 assoc=8
 729 clk_domain=system.cpu_clk_domain
 730 clusivity=mostly_incl
 731 data_latency=20
 732 default_p_state=UNDEFINED
 733 demand_mshr_reserve=1
 734 eventq_index=0
 735 is_read_only=false
 736 max_miss_count=0
 737 mshrs=20
 738 p_state_clk_gate_bins=20
 739 p_state_clk_gate_max=1000000000000
 740 p_state_clk_gate_min=1000
 741 power_model=Null
 742 prefetch_on_access=false
 743 prefetcher=Null
 744 response_latency=20
 745 sequential_access=false
 746 size=4194304
 747 system=system
 748 tag_latency=20
 749 tags=system.l2c.tags
 750 tgts_per_mshr=12
 751 write_buffers=8
 752 writeback_clean=false
 753 cpu_side=system.toL2Bus.master[0]
 754 mem_side=system.membus.slave[1]
 755
 756 [system.l2c.tags]
 757 type=LRU
 758 assoc=8
 759 block_size=64
 760 clk_domain=system.cpu_clk_domain
 761 data_latency=20
 762 default_p_state=UNDEFINED
 763 eventq_index=0
 764 p_state_clk_gate_bins=20
 765 p_state_clk_gate_max=1000000000000
 766 p_state_clk_gate_min=1000
 767 power_model=Null
 768 sequential_access=false
 769 size=4194304
 770 tag_latency=20
 771
 772 [system.membus]
 773 type=CoherentXBar
 774 children=snoop_filter
 775 clk_domain=system.clk_domain
 776 default_p_state=UNDEFINED
 777 eventq_index=0
 778 forward_latency=4
 779 frontend_latency=3
 780 p_state_clk_gate_bins=20
 781 p_state_clk_gate_max=1000000000000
 782 p_state_clk_gate_min=1000
 783 point_of_coherency=true
 784 power_model=Null
 785 response_latency=2
 786 snoop_filter=system.membus.snoop_filter
 787 snoop_response_latency=4
 788 system=system
 789 use_default_range=false
 790 width=16
 791 master=system.physmem.port
 792 slave=system.system_port system.l2c.mem_side
 793
 794 [system.membus.snoop_filter]
 795 type=SnoopFilter
 796 eventq_index=0
 797 lookup_latency=1
 798 max_capacity=8388608
 799 system=system
 800
 801 [system.physmem]
 802 type=SimpleMemory
 803 bandwidth=73.000000
 804 clk_domain=system.clk_domain
 805 conf_table_reported=true
 806 default_p_state=UNDEFINED
 807 eventq_index=0
 808 in_addr_map=true
 809 kvm_map=true
 810 latency=30000
 811 latency_var=0
 812 null=false
 813 p_state_clk_gate_bins=20
 814 p_state_clk_gate_max=1000000000000
 815 p_state_clk_gate_min=1000
 816 power_model=Null
 817 range=0:134217727:0:0:0:0
 818 port=system.membus.master[0]
 819
 820 [system.toL2Bus]
 821 type=CoherentXBar
 822 children=snoop_filter
 823 clk_domain=system.cpu_clk_domain
 824 default_p_state=UNDEFINED
 825 eventq_index=0
 826 forward_latency=0
 827 frontend_latency=1
 828 p_state_clk_gate_bins=20
 829 p_state_clk_gate_max=1000000000000
 830 p_state_clk_gate_min=1000
 831 point_of_coherency=false
 832 power_model=Null
 833 response_latency=1
 834 snoop_filter=system.toL2Bus.snoop_filter
 835 snoop_response_latency=1
 836 system=system
 837 use_default_range=false
 838 width=32
 839 master=system.l2c.cpu_side
 840 slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side
 841
 842 [system.toL2Bus.snoop_filter]
 843 type=SnoopFilter
 844 eventq_index=0
 845 lookup_latency=0
 846 max_capacity=8388608
 847 system=system
 848
 849 [system.voltage_domain]
 850 type=VoltageDomain
 851 eventq_index=0
 852 voltage=1.000000
 853