tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 eventq_index=0
   5 full_system=false
   6 sim_quantum=0
   7 time_sync_enable=false
   8 time_sync_period=100000000000
   9 time_sync_spin_threshold=100000000
  10
  11 [system]
  12 type=System
  13 children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu_clk_domain dvfs_handler l2c membus physmem toL2Bus voltage_domain
  14 boot_osflags=a
  15 cache_line_size=64
  16 clk_domain=system.clk_domain
  17 eventq_index=0
  18 init_param=0
  19 kernel=
  20 kernel_addr_check=true
  21 load_addr_mask=1099511627775
  22 load_offset=0
  23 mem_mode=timing
  24 mem_ranges=
  25 memories=system.physmem
  26 num_work_ids=16
  27 readfile=
  28 symbolfile=
  29 work_begin_ckpt_count=0
  30 work_begin_cpu_id_exit=-1
  31 work_begin_exit_count=0
  32 work_cpus_ckpt_count=0
  33 work_end_ckpt_count=0
  34 work_end_exit_count=0
  35 work_item_id=-1
  36 system_port=system.membus.slave[0]
  37
  38 [system.clk_domain]
  39 type=SrcClockDomain
  40 clock=1000
  41 domain_id=-1
  42 eventq_index=0
  43 init_perf_level=0
  44 voltage_domain=system.voltage_domain
  45
  46 [system.cpu0]
  47 type=TimingSimpleCPU
  48 children=dcache dtb icache interrupts isa itb tracer workload
  49 branchPred=Null
  50 checker=Null
  51 clk_domain=system.cpu_clk_domain
  52 cpu_id=0
  53 do_checkpoint_insts=true
  54 do_quiesce=true
  55 do_statistics_insts=true
  56 dtb=system.cpu0.dtb
  57 eventq_index=0
  58 function_trace=false
  59 function_trace_start=0
  60 interrupts=system.cpu0.interrupts
  61 isa=system.cpu0.isa
  62 itb=system.cpu0.itb
  63 max_insts_all_threads=0
  64 max_insts_any_thread=0
  65 max_loads_all_threads=0
  66 max_loads_any_thread=0
  67 numThreads=1
  68 profile=0
  69 progress_interval=0
  70 simpoint_start_insts=
  71 socket_id=0
  72 switched_out=false
  73 system=system
  74 tracer=system.cpu0.tracer
  75 workload=system.cpu0.workload
  76 dcache_port=system.cpu0.dcache.cpu_side
  77 icache_port=system.cpu0.icache.cpu_side
  78
  79 [system.cpu0.dcache]
  80 type=BaseCache
  81 children=tags
  82 addr_ranges=0:18446744073709551615
  83 assoc=4
  84 clk_domain=system.cpu_clk_domain
  85 eventq_index=0
  86 forward_snoops=true
  87 hit_latency=2
  88 is_top_level=true
  89 max_miss_count=0
  90 mshrs=4
  91 prefetch_on_access=false
  92 prefetcher=Null
  93 response_latency=2
  94 sequential_access=false
  95 size=32768
  96 system=system
  97 tags=system.cpu0.dcache.tags
  98 tgts_per_mshr=20
  99 two_queue=false
 100 write_buffers=8
 101 cpu_side=system.cpu0.dcache_port
 102 mem_side=system.toL2Bus.slave[1]
 103
 104 [system.cpu0.dcache.tags]
 105 type=LRU
 106 assoc=4
 107 block_size=64
 108 clk_domain=system.cpu_clk_domain
 109 eventq_index=0
 110 hit_latency=2
 111 sequential_access=false
 112 size=32768
 113
 114 [system.cpu0.dtb]
 115 type=SparcTLB
 116 eventq_index=0
 117 size=64
 118
 119 [system.cpu0.icache]
 120 type=BaseCache
 121 children=tags
 122 addr_ranges=0:18446744073709551615
 123 assoc=1
 124 clk_domain=system.cpu_clk_domain
 125 eventq_index=0
 126 forward_snoops=true
 127 hit_latency=2
 128 is_top_level=true
 129 max_miss_count=0
 130 mshrs=4
 131 prefetch_on_access=false
 132 prefetcher=Null
 133 response_latency=2
 134 sequential_access=false
 135 size=32768
 136 system=system
 137 tags=system.cpu0.icache.tags
 138 tgts_per_mshr=20
 139 two_queue=false
 140 write_buffers=8
 141 cpu_side=system.cpu0.icache_port
 142 mem_side=system.toL2Bus.slave[0]
 143
 144 [system.cpu0.icache.tags]
 145 type=LRU
 146 assoc=1
 147 block_size=64
 148 clk_domain=system.cpu_clk_domain
 149 eventq_index=0
 150 hit_latency=2
 151 sequential_access=false
 152 size=32768
 153
 154 [system.cpu0.interrupts]
 155 type=SparcInterrupts
 156 eventq_index=0
 157
 158 [system.cpu0.isa]
 159 type=SparcISA
 160 eventq_index=0
 161
 162 [system.cpu0.itb]
 163 type=SparcTLB
 164 eventq_index=0
 165 size=64
 166
 167 [system.cpu0.tracer]
 168 type=ExeTracer
 169 eventq_index=0
 170
 171 [system.cpu0.workload]
 172 type=LiveProcess
 173 cmd=test_atomic 4
 174 cwd=
 175 egid=100
 176 env=
 177 errout=cerr
 178 euid=100
 179 eventq_index=0
 180 executable=/scratch/nilay/GEM5/gem5/tests/test-progs/m5threads/bin/sparc/linux/test_atomic
 181 gid=100
 182 input=cin
 183 max_stack_size=67108864
 184 output=cout
 185 pid=100
 186 ppid=99
 187 simpoint=0
 188 system=system
 189 uid=100
 190 useArchPT=false
 191
 192 [system.cpu1]
 193 type=TimingSimpleCPU
 194 children=dcache dtb icache interrupts isa itb tracer
 195 branchPred=Null
 196 checker=Null
 197 clk_domain=system.cpu_clk_domain
 198 cpu_id=1
 199 do_checkpoint_insts=true
 200 do_quiesce=true
 201 do_statistics_insts=true
 202 dtb=system.cpu1.dtb
 203 eventq_index=0
 204 function_trace=false
 205 function_trace_start=0
 206 interrupts=system.cpu1.interrupts
 207 isa=system.cpu1.isa
 208 itb=system.cpu1.itb
 209 max_insts_all_threads=0
 210 max_insts_any_thread=0
 211 max_loads_all_threads=0
 212 max_loads_any_thread=0
 213 numThreads=1
 214 profile=0
 215 progress_interval=0
 216 simpoint_start_insts=
 217 socket_id=0
 218 switched_out=false
 219 system=system
 220 tracer=system.cpu1.tracer
 221 workload=system.cpu0.workload
 222 dcache_port=system.cpu1.dcache.cpu_side
 223 icache_port=system.cpu1.icache.cpu_side
 224
 225 [system.cpu1.dcache]
 226 type=BaseCache
 227 children=tags
 228 addr_ranges=0:18446744073709551615
 229 assoc=4
 230 clk_domain=system.cpu_clk_domain
 231 eventq_index=0
 232 forward_snoops=true
 233 hit_latency=2
 234 is_top_level=true
 235 max_miss_count=0
 236 mshrs=4
 237 prefetch_on_access=false
 238 prefetcher=Null
 239 response_latency=2
 240 sequential_access=false
 241 size=32768
 242 system=system
 243 tags=system.cpu1.dcache.tags
 244 tgts_per_mshr=20
 245 two_queue=false
 246 write_buffers=8
 247 cpu_side=system.cpu1.dcache_port
 248 mem_side=system.toL2Bus.slave[3]
 249
 250 [system.cpu1.dcache.tags]
 251 type=LRU
 252 assoc=4
 253 block_size=64
 254 clk_domain=system.cpu_clk_domain
 255 eventq_index=0
 256 hit_latency=2
 257 sequential_access=false
 258 size=32768
 259
 260 [system.cpu1.dtb]
 261 type=SparcTLB
 262 eventq_index=0
 263 size=64
 264
 265 [system.cpu1.icache]
 266 type=BaseCache
 267 children=tags
 268 addr_ranges=0:18446744073709551615
 269 assoc=1
 270 clk_domain=system.cpu_clk_domain
 271 eventq_index=0
 272 forward_snoops=true
 273 hit_latency=2
 274 is_top_level=true
 275 max_miss_count=0
 276 mshrs=4
 277 prefetch_on_access=false
 278 prefetcher=Null
 279 response_latency=2
 280 sequential_access=false
 281 size=32768
 282 system=system
 283 tags=system.cpu1.icache.tags
 284 tgts_per_mshr=20
 285 two_queue=false
 286 write_buffers=8
 287 cpu_side=system.cpu1.icache_port
 288 mem_side=system.toL2Bus.slave[2]
 289
 290 [system.cpu1.icache.tags]
 291 type=LRU
 292 assoc=1
 293 block_size=64
 294 clk_domain=system.cpu_clk_domain
 295 eventq_index=0
 296 hit_latency=2
 297 sequential_access=false
 298 size=32768
 299
 300 [system.cpu1.interrupts]
 301 type=SparcInterrupts
 302 eventq_index=0
 303
 304 [system.cpu1.isa]
 305 type=SparcISA
 306 eventq_index=0
 307
 308 [system.cpu1.itb]
 309 type=SparcTLB
 310 eventq_index=0
 311 size=64
 312
 313 [system.cpu1.tracer]
 314 type=ExeTracer
 315 eventq_index=0
 316
 317 [system.cpu2]
 318 type=TimingSimpleCPU
 319 children=dcache dtb icache interrupts isa itb tracer
 320 branchPred=Null
 321 checker=Null
 322 clk_domain=system.cpu_clk_domain
 323 cpu_id=2
 324 do_checkpoint_insts=true
 325 do_quiesce=true
 326 do_statistics_insts=true
 327 dtb=system.cpu2.dtb
 328 eventq_index=0
 329 function_trace=false
 330 function_trace_start=0
 331 interrupts=system.cpu2.interrupts
 332 isa=system.cpu2.isa
 333 itb=system.cpu2.itb
 334 max_insts_all_threads=0
 335 max_insts_any_thread=0
 336 max_loads_all_threads=0
 337 max_loads_any_thread=0
 338 numThreads=1
 339 profile=0
 340 progress_interval=0
 341 simpoint_start_insts=
 342 socket_id=0
 343 switched_out=false
 344 system=system
 345 tracer=system.cpu2.tracer
 346 workload=system.cpu0.workload
 347 dcache_port=system.cpu2.dcache.cpu_side
 348 icache_port=system.cpu2.icache.cpu_side
 349
 350 [system.cpu2.dcache]
 351 type=BaseCache
 352 children=tags
 353 addr_ranges=0:18446744073709551615
 354 assoc=4
 355 clk_domain=system.cpu_clk_domain
 356 eventq_index=0
 357 forward_snoops=true
 358 hit_latency=2
 359 is_top_level=true
 360 max_miss_count=0
 361 mshrs=4
 362 prefetch_on_access=false
 363 prefetcher=Null
 364 response_latency=2
 365 sequential_access=false
 366 size=32768
 367 system=system
 368 tags=system.cpu2.dcache.tags
 369 tgts_per_mshr=20
 370 two_queue=false
 371 write_buffers=8
 372 cpu_side=system.cpu2.dcache_port
 373 mem_side=system.toL2Bus.slave[5]
 374
 375 [system.cpu2.dcache.tags]
 376 type=LRU
 377 assoc=4
 378 block_size=64
 379 clk_domain=system.cpu_clk_domain
 380 eventq_index=0
 381 hit_latency=2
 382 sequential_access=false
 383 size=32768
 384
 385 [system.cpu2.dtb]
 386 type=SparcTLB
 387 eventq_index=0
 388 size=64
 389
 390 [system.cpu2.icache]
 391 type=BaseCache
 392 children=tags
 393 addr_ranges=0:18446744073709551615
 394 assoc=1
 395 clk_domain=system.cpu_clk_domain
 396 eventq_index=0
 397 forward_snoops=true
 398 hit_latency=2
 399 is_top_level=true
 400 max_miss_count=0
 401 mshrs=4
 402 prefetch_on_access=false
 403 prefetcher=Null
 404 response_latency=2
 405 sequential_access=false
 406 size=32768
 407 system=system
 408 tags=system.cpu2.icache.tags
 409 tgts_per_mshr=20
 410 two_queue=false
 411 write_buffers=8
 412 cpu_side=system.cpu2.icache_port
 413 mem_side=system.toL2Bus.slave[4]
 414
 415 [system.cpu2.icache.tags]
 416 type=LRU
 417 assoc=1
 418 block_size=64
 419 clk_domain=system.cpu_clk_domain
 420 eventq_index=0
 421 hit_latency=2
 422 sequential_access=false
 423 size=32768
 424
 425 [system.cpu2.interrupts]
 426 type=SparcInterrupts
 427 eventq_index=0
 428
 429 [system.cpu2.isa]
 430 type=SparcISA
 431 eventq_index=0
 432
 433 [system.cpu2.itb]
 434 type=SparcTLB
 435 eventq_index=0
 436 size=64
 437
 438 [system.cpu2.tracer]
 439 type=ExeTracer
 440 eventq_index=0
 441
 442 [system.cpu3]
 443 type=TimingSimpleCPU
 444 children=dcache dtb icache interrupts isa itb tracer
 445 branchPred=Null
 446 checker=Null
 447 clk_domain=system.cpu_clk_domain
 448 cpu_id=3
 449 do_checkpoint_insts=true
 450 do_quiesce=true
 451 do_statistics_insts=true
 452 dtb=system.cpu3.dtb
 453 eventq_index=0
 454 function_trace=false
 455 function_trace_start=0
 456 interrupts=system.cpu3.interrupts
 457 isa=system.cpu3.isa
 458 itb=system.cpu3.itb
 459 max_insts_all_threads=0
 460 max_insts_any_thread=0
 461 max_loads_all_threads=0
 462 max_loads_any_thread=0
 463 numThreads=1
 464 profile=0
 465 progress_interval=0
 466 simpoint_start_insts=
 467 socket_id=0
 468 switched_out=false
 469 system=system
 470 tracer=system.cpu3.tracer
 471 workload=system.cpu0.workload
 472 dcache_port=system.cpu3.dcache.cpu_side
 473 icache_port=system.cpu3.icache.cpu_side
 474
 475 [system.cpu3.dcache]
 476 type=BaseCache
 477 children=tags
 478 addr_ranges=0:18446744073709551615
 479 assoc=4
 480 clk_domain=system.cpu_clk_domain
 481 eventq_index=0
 482 forward_snoops=true
 483 hit_latency=2
 484 is_top_level=true
 485 max_miss_count=0
 486 mshrs=4
 487 prefetch_on_access=false
 488 prefetcher=Null
 489 response_latency=2
 490 sequential_access=false
 491 size=32768
 492 system=system
 493 tags=system.cpu3.dcache.tags
 494 tgts_per_mshr=20
 495 two_queue=false
 496 write_buffers=8
 497 cpu_side=system.cpu3.dcache_port
 498 mem_side=system.toL2Bus.slave[7]
 499
 500 [system.cpu3.dcache.tags]
 501 type=LRU
 502 assoc=4
 503 block_size=64
 504 clk_domain=system.cpu_clk_domain
 505 eventq_index=0
 506 hit_latency=2
 507 sequential_access=false
 508 size=32768
 509
 510 [system.cpu3.dtb]
 511 type=SparcTLB
 512 eventq_index=0
 513 size=64
 514
 515 [system.cpu3.icache]
 516 type=BaseCache
 517 children=tags
 518 addr_ranges=0:18446744073709551615
 519 assoc=1
 520 clk_domain=system.cpu_clk_domain
 521 eventq_index=0
 522 forward_snoops=true
 523 hit_latency=2
 524 is_top_level=true
 525 max_miss_count=0
 526 mshrs=4
 527 prefetch_on_access=false
 528 prefetcher=Null
 529 response_latency=2
 530 sequential_access=false
 531 size=32768
 532 system=system
 533 tags=system.cpu3.icache.tags
 534 tgts_per_mshr=20
 535 two_queue=false
 536 write_buffers=8
 537 cpu_side=system.cpu3.icache_port
 538 mem_side=system.toL2Bus.slave[6]
 539
 540 [system.cpu3.icache.tags]
 541 type=LRU
 542 assoc=1
 543 block_size=64
 544 clk_domain=system.cpu_clk_domain
 545 eventq_index=0
 546 hit_latency=2
 547 sequential_access=false
 548 size=32768
 549
 550 [system.cpu3.interrupts]
 551 type=SparcInterrupts
 552 eventq_index=0
 553
 554 [system.cpu3.isa]
 555 type=SparcISA
 556 eventq_index=0
 557
 558 [system.cpu3.itb]
 559 type=SparcTLB
 560 eventq_index=0
 561 size=64
 562
 563 [system.cpu3.tracer]
 564 type=ExeTracer
 565 eventq_index=0
 566
 567 [system.cpu_clk_domain]
 568 type=SrcClockDomain
 569 clock=500
 570 domain_id=-1
 571 eventq_index=0
 572 init_perf_level=0
 573 voltage_domain=system.voltage_domain
 574
 575 [system.dvfs_handler]
 576 type=DVFSHandler
 577 domains=
 578 enable=false
 579 eventq_index=0
 580 sys_clk_domain=system.clk_domain
 581 transition_latency=100000000
 582
 583 [system.l2c]
 584 type=BaseCache
 585 children=tags
 586 addr_ranges=0:18446744073709551615
 587 assoc=8
 588 clk_domain=system.cpu_clk_domain
 589 eventq_index=0
 590 forward_snoops=true
 591 hit_latency=20
 592 is_top_level=false
 593 max_miss_count=0
 594 mshrs=20
 595 prefetch_on_access=false
 596 prefetcher=Null
 597 response_latency=20
 598 sequential_access=false
 599 size=4194304
 600 system=system
 601 tags=system.l2c.tags
 602 tgts_per_mshr=12
 603 two_queue=false
 604 write_buffers=8
 605 cpu_side=system.toL2Bus.master[0]
 606 mem_side=system.membus.slave[1]
 607
 608 [system.l2c.tags]
 609 type=LRU
 610 assoc=8
 611 block_size=64
 612 clk_domain=system.cpu_clk_domain
 613 eventq_index=0
 614 hit_latency=20
 615 sequential_access=false
 616 size=4194304
 617
 618 [system.membus]
 619 type=CoherentXBar
 620 clk_domain=system.clk_domain
 621 eventq_index=0
 622 header_cycles=1
 623 snoop_filter=Null
 624 system=system
 625 use_default_range=false
 626 width=8
 627 master=system.physmem.port
 628 slave=system.system_port system.l2c.mem_side
 629
 630 [system.physmem]
 631 type=SimpleMemory
 632 bandwidth=73.000000
 633 clk_domain=system.clk_domain
 634 conf_table_reported=true
 635 eventq_index=0
 636 in_addr_map=true
 637 latency=30000
 638 latency_var=0
 639 null=false
 640 range=0:134217727
 641 port=system.membus.master[0]
 642
 643 [system.toL2Bus]
 644 type=CoherentXBar
 645 clk_domain=system.cpu_clk_domain
 646 eventq_index=0
 647 header_cycles=1
 648 snoop_filter=Null
 649 system=system
 650 use_default_range=false
 651 width=8
 652 master=system.l2c.cpu_side
 653 slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side
 654
 655 [system.voltage_domain]
 656 type=VoltageDomain
 657 eventq_index=0
 658 voltage=1.000000
 659