tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 eventq_index=0
   5 full_system=false
   6 sim_quantum=0
   7 time_sync_enable=false
   8 time_sync_period=100000000000
   9 time_sync_spin_threshold=100000000
  10
  11 [system]
  12 type=System
  13 children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu_clk_domain dvfs_handler l2c membus physmem toL2Bus voltage_domain
  14 boot_osflags=a
  15 cache_line_size=64
  16 clk_domain=system.clk_domain
  17 eventq_index=0
  18 init_param=0
  19 kernel=
  20 kernel_addr_check=true
  21 load_addr_mask=1099511627775
  22 load_offset=0
  23 mem_mode=timing
  24 mem_ranges=
  25 memories=system.physmem
  26 mmap_using_noreserve=false
  27 multi_thread=false
  28 num_work_ids=16
  29 readfile=
  30 symbolfile=
  31 work_begin_ckpt_count=0
  32 work_begin_cpu_id_exit=-1
  33 work_begin_exit_count=0
  34 work_cpus_ckpt_count=0
  35 work_end_ckpt_count=0
  36 work_end_exit_count=0
  37 work_item_id=-1
  38 system_port=system.membus.slave[0]
  39
  40 [system.clk_domain]
  41 type=SrcClockDomain
  42 clock=1000
  43 domain_id=-1
  44 eventq_index=0
  45 init_perf_level=0
  46 voltage_domain=system.voltage_domain
  47
  48 [system.cpu0]
  49 type=TimingSimpleCPU
  50 children=dcache dtb icache interrupts isa itb tracer workload
  51 branchPred=Null
  52 checker=Null
  53 clk_domain=system.cpu_clk_domain
  54 cpu_id=0
  55 do_checkpoint_insts=true
  56 do_quiesce=true
  57 do_statistics_insts=true
  58 dtb=system.cpu0.dtb
  59 eventq_index=0
  60 function_trace=false
  61 function_trace_start=0
  62 interrupts=system.cpu0.interrupts
  63 isa=system.cpu0.isa
  64 itb=system.cpu0.itb
  65 max_insts_all_threads=0
  66 max_insts_any_thread=0
  67 max_loads_all_threads=0
  68 max_loads_any_thread=0
  69 numThreads=1
  70 profile=0
  71 progress_interval=0
  72 simpoint_start_insts=
  73 socket_id=0
  74 switched_out=false
  75 system=system
  76 tracer=system.cpu0.tracer
  77 workload=system.cpu0.workload
  78 dcache_port=system.cpu0.dcache.cpu_side
  79 icache_port=system.cpu0.icache.cpu_side
  80
  81 [system.cpu0.dcache]
  82 type=Cache
  83 children=tags
  84 addr_ranges=0:18446744073709551615
  85 assoc=4
  86 clk_domain=system.cpu_clk_domain
  87 clusivity=mostly_incl
  88 demand_mshr_reserve=1
  89 eventq_index=0
  90 forward_snoops=true
  91 hit_latency=2
  92 is_read_only=false
  93 max_miss_count=0
  94 mshrs=4
  95 prefetch_on_access=false
  96 prefetcher=Null
  97 response_latency=2
  98 sequential_access=false
  99 size=32768
 100 system=system
 101 tags=system.cpu0.dcache.tags
 102 tgts_per_mshr=20
 103 write_buffers=8
 104 writeback_clean=false
 105 cpu_side=system.cpu0.dcache_port
 106 mem_side=system.toL2Bus.slave[1]
 107
 108 [system.cpu0.dcache.tags]
 109 type=LRU
 110 assoc=4
 111 block_size=64
 112 clk_domain=system.cpu_clk_domain
 113 eventq_index=0
 114 hit_latency=2
 115 sequential_access=false
 116 size=32768
 117
 118 [system.cpu0.dtb]
 119 type=SparcTLB
 120 eventq_index=0
 121 size=64
 122
 123 [system.cpu0.icache]
 124 type=Cache
 125 children=tags
 126 addr_ranges=0:18446744073709551615
 127 assoc=1
 128 clk_domain=system.cpu_clk_domain
 129 clusivity=mostly_incl
 130 demand_mshr_reserve=1
 131 eventq_index=0
 132 forward_snoops=true
 133 hit_latency=2
 134 is_read_only=true
 135 max_miss_count=0
 136 mshrs=4
 137 prefetch_on_access=false
 138 prefetcher=Null
 139 response_latency=2
 140 sequential_access=false
 141 size=32768
 142 system=system
 143 tags=system.cpu0.icache.tags
 144 tgts_per_mshr=20
 145 write_buffers=8
 146 writeback_clean=true
 147 cpu_side=system.cpu0.icache_port
 148 mem_side=system.toL2Bus.slave[0]
 149
 150 [system.cpu0.icache.tags]
 151 type=LRU
 152 assoc=1
 153 block_size=64
 154 clk_domain=system.cpu_clk_domain
 155 eventq_index=0
 156 hit_latency=2
 157 sequential_access=false
 158 size=32768
 159
 160 [system.cpu0.interrupts]
 161 type=SparcInterrupts
 162 eventq_index=0
 163
 164 [system.cpu0.isa]
 165 type=SparcISA
 166 eventq_index=0
 167
 168 [system.cpu0.itb]
 169 type=SparcTLB
 170 eventq_index=0
 171 size=64
 172
 173 [system.cpu0.tracer]
 174 type=ExeTracer
 175 eventq_index=0
 176
 177 [system.cpu0.workload]
 178 type=LiveProcess
 179 cmd=test_atomic 4
 180 cwd=
 181 drivers=
 182 egid=100
 183 env=
 184 errout=cerr
 185 euid=100
 186 eventq_index=0
 187 executable=/dist/m5/regression/test-progs/m5threads/bin/sparc/linux/test_atomic
 188 gid=100
 189 input=cin
 190 kvmInSE=false
 191 max_stack_size=67108864
 192 output=cout
 193 pid=100
 194 ppid=99
 195 simpoint=0
 196 system=system
 197 uid=100
 198 useArchPT=false
 199
 200 [system.cpu1]
 201 type=TimingSimpleCPU
 202 children=dcache dtb icache interrupts isa itb tracer
 203 branchPred=Null
 204 checker=Null
 205 clk_domain=system.cpu_clk_domain
 206 cpu_id=1
 207 do_checkpoint_insts=true
 208 do_quiesce=true
 209 do_statistics_insts=true
 210 dtb=system.cpu1.dtb
 211 eventq_index=0
 212 function_trace=false
 213 function_trace_start=0
 214 interrupts=system.cpu1.interrupts
 215 isa=system.cpu1.isa
 216 itb=system.cpu1.itb
 217 max_insts_all_threads=0
 218 max_insts_any_thread=0
 219 max_loads_all_threads=0
 220 max_loads_any_thread=0
 221 numThreads=1
 222 profile=0
 223 progress_interval=0
 224 simpoint_start_insts=
 225 socket_id=0
 226 switched_out=false
 227 system=system
 228 tracer=system.cpu1.tracer
 229 workload=system.cpu0.workload
 230 dcache_port=system.cpu1.dcache.cpu_side
 231 icache_port=system.cpu1.icache.cpu_side
 232
 233 [system.cpu1.dcache]
 234 type=Cache
 235 children=tags
 236 addr_ranges=0:18446744073709551615
 237 assoc=4
 238 clk_domain=system.cpu_clk_domain
 239 clusivity=mostly_incl
 240 demand_mshr_reserve=1
 241 eventq_index=0
 242 forward_snoops=true
 243 hit_latency=2
 244 is_read_only=false
 245 max_miss_count=0
 246 mshrs=4
 247 prefetch_on_access=false
 248 prefetcher=Null
 249 response_latency=2
 250 sequential_access=false
 251 size=32768
 252 system=system
 253 tags=system.cpu1.dcache.tags
 254 tgts_per_mshr=20
 255 write_buffers=8
 256 writeback_clean=false
 257 cpu_side=system.cpu1.dcache_port
 258 mem_side=system.toL2Bus.slave[3]
 259
 260 [system.cpu1.dcache.tags]
 261 type=LRU
 262 assoc=4
 263 block_size=64
 264 clk_domain=system.cpu_clk_domain
 265 eventq_index=0
 266 hit_latency=2
 267 sequential_access=false
 268 size=32768
 269
 270 [system.cpu1.dtb]
 271 type=SparcTLB
 272 eventq_index=0
 273 size=64
 274
 275 [system.cpu1.icache]
 276 type=Cache
 277 children=tags
 278 addr_ranges=0:18446744073709551615
 279 assoc=1
 280 clk_domain=system.cpu_clk_domain
 281 clusivity=mostly_incl
 282 demand_mshr_reserve=1
 283 eventq_index=0
 284 forward_snoops=true
 285 hit_latency=2
 286 is_read_only=true
 287 max_miss_count=0
 288 mshrs=4
 289 prefetch_on_access=false
 290 prefetcher=Null
 291 response_latency=2
 292 sequential_access=false
 293 size=32768
 294 system=system
 295 tags=system.cpu1.icache.tags
 296 tgts_per_mshr=20
 297 write_buffers=8
 298 writeback_clean=true
 299 cpu_side=system.cpu1.icache_port
 300 mem_side=system.toL2Bus.slave[2]
 301
 302 [system.cpu1.icache.tags]
 303 type=LRU
 304 assoc=1
 305 block_size=64
 306 clk_domain=system.cpu_clk_domain
 307 eventq_index=0
 308 hit_latency=2
 309 sequential_access=false
 310 size=32768
 311
 312 [system.cpu1.interrupts]
 313 type=SparcInterrupts
 314 eventq_index=0
 315
 316 [system.cpu1.isa]
 317 type=SparcISA
 318 eventq_index=0
 319
 320 [system.cpu1.itb]
 321 type=SparcTLB
 322 eventq_index=0
 323 size=64
 324
 325 [system.cpu1.tracer]
 326 type=ExeTracer
 327 eventq_index=0
 328
 329 [system.cpu2]
 330 type=TimingSimpleCPU
 331 children=dcache dtb icache interrupts isa itb tracer
 332 branchPred=Null
 333 checker=Null
 334 clk_domain=system.cpu_clk_domain
 335 cpu_id=2
 336 do_checkpoint_insts=true
 337 do_quiesce=true
 338 do_statistics_insts=true
 339 dtb=system.cpu2.dtb
 340 eventq_index=0
 341 function_trace=false
 342 function_trace_start=0
 343 interrupts=system.cpu2.interrupts
 344 isa=system.cpu2.isa
 345 itb=system.cpu2.itb
 346 max_insts_all_threads=0
 347 max_insts_any_thread=0
 348 max_loads_all_threads=0
 349 max_loads_any_thread=0
 350 numThreads=1
 351 profile=0
 352 progress_interval=0
 353 simpoint_start_insts=
 354 socket_id=0
 355 switched_out=false
 356 system=system
 357 tracer=system.cpu2.tracer
 358 workload=system.cpu0.workload
 359 dcache_port=system.cpu2.dcache.cpu_side
 360 icache_port=system.cpu2.icache.cpu_side
 361
 362 [system.cpu2.dcache]
 363 type=Cache
 364 children=tags
 365 addr_ranges=0:18446744073709551615
 366 assoc=4
 367 clk_domain=system.cpu_clk_domain
 368 clusivity=mostly_incl
 369 demand_mshr_reserve=1
 370 eventq_index=0
 371 forward_snoops=true
 372 hit_latency=2
 373 is_read_only=false
 374 max_miss_count=0
 375 mshrs=4
 376 prefetch_on_access=false
 377 prefetcher=Null
 378 response_latency=2
 379 sequential_access=false
 380 size=32768
 381 system=system
 382 tags=system.cpu2.dcache.tags
 383 tgts_per_mshr=20
 384 write_buffers=8
 385 writeback_clean=false
 386 cpu_side=system.cpu2.dcache_port
 387 mem_side=system.toL2Bus.slave[5]
 388
 389 [system.cpu2.dcache.tags]
 390 type=LRU
 391 assoc=4
 392 block_size=64
 393 clk_domain=system.cpu_clk_domain
 394 eventq_index=0
 395 hit_latency=2
 396 sequential_access=false
 397 size=32768
 398
 399 [system.cpu2.dtb]
 400 type=SparcTLB
 401 eventq_index=0
 402 size=64
 403
 404 [system.cpu2.icache]
 405 type=Cache
 406 children=tags
 407 addr_ranges=0:18446744073709551615
 408 assoc=1
 409 clk_domain=system.cpu_clk_domain
 410 clusivity=mostly_incl
 411 demand_mshr_reserve=1
 412 eventq_index=0
 413 forward_snoops=true
 414 hit_latency=2
 415 is_read_only=true
 416 max_miss_count=0
 417 mshrs=4
 418 prefetch_on_access=false
 419 prefetcher=Null
 420 response_latency=2
 421 sequential_access=false
 422 size=32768
 423 system=system
 424 tags=system.cpu2.icache.tags
 425 tgts_per_mshr=20
 426 write_buffers=8
 427 writeback_clean=true
 428 cpu_side=system.cpu2.icache_port
 429 mem_side=system.toL2Bus.slave[4]
 430
 431 [system.cpu2.icache.tags]
 432 type=LRU
 433 assoc=1
 434 block_size=64
 435 clk_domain=system.cpu_clk_domain
 436 eventq_index=0
 437 hit_latency=2
 438 sequential_access=false
 439 size=32768
 440
 441 [system.cpu2.interrupts]
 442 type=SparcInterrupts
 443 eventq_index=0
 444
 445 [system.cpu2.isa]
 446 type=SparcISA
 447 eventq_index=0
 448
 449 [system.cpu2.itb]
 450 type=SparcTLB
 451 eventq_index=0
 452 size=64
 453
 454 [system.cpu2.tracer]
 455 type=ExeTracer
 456 eventq_index=0
 457
 458 [system.cpu3]
 459 type=TimingSimpleCPU
 460 children=dcache dtb icache interrupts isa itb tracer
 461 branchPred=Null
 462 checker=Null
 463 clk_domain=system.cpu_clk_domain
 464 cpu_id=3
 465 do_checkpoint_insts=true
 466 do_quiesce=true
 467 do_statistics_insts=true
 468 dtb=system.cpu3.dtb
 469 eventq_index=0
 470 function_trace=false
 471 function_trace_start=0
 472 interrupts=system.cpu3.interrupts
 473 isa=system.cpu3.isa
 474 itb=system.cpu3.itb
 475 max_insts_all_threads=0
 476 max_insts_any_thread=0
 477 max_loads_all_threads=0
 478 max_loads_any_thread=0
 479 numThreads=1
 480 profile=0
 481 progress_interval=0
 482 simpoint_start_insts=
 483 socket_id=0
 484 switched_out=false
 485 system=system
 486 tracer=system.cpu3.tracer
 487 workload=system.cpu0.workload
 488 dcache_port=system.cpu3.dcache.cpu_side
 489 icache_port=system.cpu3.icache.cpu_side
 490
 491 [system.cpu3.dcache]
 492 type=Cache
 493 children=tags
 494 addr_ranges=0:18446744073709551615
 495 assoc=4
 496 clk_domain=system.cpu_clk_domain
 497 clusivity=mostly_incl
 498 demand_mshr_reserve=1
 499 eventq_index=0
 500 forward_snoops=true
 501 hit_latency=2
 502 is_read_only=false
 503 max_miss_count=0
 504 mshrs=4
 505 prefetch_on_access=false
 506 prefetcher=Null
 507 response_latency=2
 508 sequential_access=false
 509 size=32768
 510 system=system
 511 tags=system.cpu3.dcache.tags
 512 tgts_per_mshr=20
 513 write_buffers=8
 514 writeback_clean=false
 515 cpu_side=system.cpu3.dcache_port
 516 mem_side=system.toL2Bus.slave[7]
 517
 518 [system.cpu3.dcache.tags]
 519 type=LRU
 520 assoc=4
 521 block_size=64
 522 clk_domain=system.cpu_clk_domain
 523 eventq_index=0
 524 hit_latency=2
 525 sequential_access=false
 526 size=32768
 527
 528 [system.cpu3.dtb]
 529 type=SparcTLB
 530 eventq_index=0
 531 size=64
 532
 533 [system.cpu3.icache]
 534 type=Cache
 535 children=tags
 536 addr_ranges=0:18446744073709551615
 537 assoc=1
 538 clk_domain=system.cpu_clk_domain
 539 clusivity=mostly_incl
 540 demand_mshr_reserve=1
 541 eventq_index=0
 542 forward_snoops=true
 543 hit_latency=2
 544 is_read_only=true
 545 max_miss_count=0
 546 mshrs=4
 547 prefetch_on_access=false
 548 prefetcher=Null
 549 response_latency=2
 550 sequential_access=false
 551 size=32768
 552 system=system
 553 tags=system.cpu3.icache.tags
 554 tgts_per_mshr=20
 555 write_buffers=8
 556 writeback_clean=true
 557 cpu_side=system.cpu3.icache_port
 558 mem_side=system.toL2Bus.slave[6]
 559
 560 [system.cpu3.icache.tags]
 561 type=LRU
 562 assoc=1
 563 block_size=64
 564 clk_domain=system.cpu_clk_domain
 565 eventq_index=0
 566 hit_latency=2
 567 sequential_access=false
 568 size=32768
 569
 570 [system.cpu3.interrupts]
 571 type=SparcInterrupts
 572 eventq_index=0
 573
 574 [system.cpu3.isa]
 575 type=SparcISA
 576 eventq_index=0
 577
 578 [system.cpu3.itb]
 579 type=SparcTLB
 580 eventq_index=0
 581 size=64
 582
 583 [system.cpu3.tracer]
 584 type=ExeTracer
 585 eventq_index=0
 586
 587 [system.cpu_clk_domain]
 588 type=SrcClockDomain
 589 clock=500
 590 domain_id=-1
 591 eventq_index=0
 592 init_perf_level=0
 593 voltage_domain=system.voltage_domain
 594
 595 [system.dvfs_handler]
 596 type=DVFSHandler
 597 domains=
 598 enable=false
 599 eventq_index=0
 600 sys_clk_domain=system.clk_domain
 601 transition_latency=100000000
 602
 603 [system.l2c]
 604 type=Cache
 605 children=tags
 606 addr_ranges=0:18446744073709551615
 607 assoc=8
 608 clk_domain=system.cpu_clk_domain
 609 clusivity=mostly_incl
 610 demand_mshr_reserve=1
 611 eventq_index=0
 612 forward_snoops=true
 613 hit_latency=20
 614 is_read_only=false
 615 max_miss_count=0
 616 mshrs=20
 617 prefetch_on_access=false
 618 prefetcher=Null
 619 response_latency=20
 620 sequential_access=false
 621 size=4194304
 622 system=system
 623 tags=system.l2c.tags
 624 tgts_per_mshr=12
 625 write_buffers=8
 626 writeback_clean=false
 627 cpu_side=system.toL2Bus.master[0]
 628 mem_side=system.membus.slave[1]
 629
 630 [system.l2c.tags]
 631 type=LRU
 632 assoc=8
 633 block_size=64
 634 clk_domain=system.cpu_clk_domain
 635 eventq_index=0
 636 hit_latency=20
 637 sequential_access=false
 638 size=4194304
 639
 640 [system.membus]
 641 type=CoherentXBar
 642 clk_domain=system.clk_domain
 643 eventq_index=0
 644 forward_latency=4
 645 frontend_latency=3
 646 response_latency=2
 647 snoop_filter=Null
 648 snoop_response_latency=4
 649 system=system
 650 use_default_range=false
 651 width=16
 652 master=system.physmem.port
 653 slave=system.system_port system.l2c.mem_side
 654
 655 [system.physmem]
 656 type=SimpleMemory
 657 bandwidth=73.000000
 658 clk_domain=system.clk_domain
 659 conf_table_reported=true
 660 eventq_index=0
 661 in_addr_map=true
 662 latency=30000
 663 latency_var=0
 664 null=false
 665 range=0:134217727
 666 port=system.membus.master[0]
 667
 668 [system.toL2Bus]
 669 type=CoherentXBar
 670 children=snoop_filter
 671 clk_domain=system.cpu_clk_domain
 672 eventq_index=0
 673 forward_latency=0
 674 frontend_latency=1
 675 response_latency=1
 676 snoop_filter=system.toL2Bus.snoop_filter
 677 snoop_response_latency=1
 678 system=system
 679 use_default_range=false
 680 width=32
 681 master=system.l2c.cpu_side
 682 slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side
 683
 684 [system.toL2Bus.snoop_filter]
 685 type=SnoopFilter
 686 eventq_index=0
 687 lookup_latency=0
 688 max_capacity=8388608
 689 system=system
 690
 691 [system.voltage_domain]
 692 type=VoltageDomain
 693 eventq_index=0
 694 voltage=1.000000
 695