tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 eventq_index=0
   5 full_system=false
   6 sim_quantum=0
   7 time_sync_enable=false
   8 time_sync_period=100000000000
   9 time_sync_spin_threshold=100000000
  10
  11 [system]
  12 type=System
  13 children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu_clk_domain dvfs_handler l2c membus physmem toL2Bus voltage_domain
  14 boot_osflags=a
  15 cache_line_size=64
  16 clk_domain=system.clk_domain
  17 eventq_index=0
  18 init_param=0
  19 kernel=
  20 kernel_addr_check=true
  21 load_addr_mask=1099511627775
  22 load_offset=0
  23 mem_mode=timing
  24 mem_ranges=
  25 memories=system.physmem
  26 num_work_ids=16
  27 readfile=
  28 symbolfile=
  29 work_begin_ckpt_count=0
  30 work_begin_cpu_id_exit=-1
  31 work_begin_exit_count=0
  32 work_cpus_ckpt_count=0
  33 work_end_ckpt_count=0
  34 work_end_exit_count=0
  35 work_item_id=-1
  36 system_port=system.membus.slave[0]
  37
  38 [system.clk_domain]
  39 type=SrcClockDomain
  40 clock=1000
  41 domain_id=-1
  42 eventq_index=0
  43 init_perf_level=0
  44 voltage_domain=system.voltage_domain
  45
  46 [system.cpu0]
  47 type=TimingSimpleCPU
  48 children=dcache dtb icache interrupts isa itb tracer workload
  49 branchPred=Null
  50 checker=Null
  51 clk_domain=system.cpu_clk_domain
  52 cpu_id=0
  53 do_checkpoint_insts=true
  54 do_quiesce=true
  55 do_statistics_insts=true
  56 dtb=system.cpu0.dtb
  57 eventq_index=0
  58 function_trace=false
  59 function_trace_start=0
  60 interrupts=system.cpu0.interrupts
  61 isa=system.cpu0.isa
  62 itb=system.cpu0.itb
  63 max_insts_all_threads=0
  64 max_insts_any_thread=0
  65 max_loads_all_threads=0
  66 max_loads_any_thread=0
  67 numThreads=1
  68 profile=0
  69 progress_interval=0
  70 simpoint_start_insts=
  71 socket_id=0
  72 switched_out=false
  73 system=system
  74 tracer=system.cpu0.tracer
  75 workload=system.cpu0.workload
  76 dcache_port=system.cpu0.dcache.cpu_side
  77 icache_port=system.cpu0.icache.cpu_side
  78
  79 [system.cpu0.dcache]
  80 type=BaseCache
  81 children=tags
  82 addr_ranges=0:18446744073709551615
  83 assoc=4
  84 clk_domain=system.cpu_clk_domain
  85 eventq_index=0
  86 forward_snoops=true
  87 hit_latency=2
  88 is_top_level=true
  89 max_miss_count=0
  90 mshrs=4
  91 prefetch_on_access=false
  92 prefetcher=Null
  93 response_latency=2
  94 sequential_access=false
  95 size=32768
  96 system=system
  97 tags=system.cpu0.dcache.tags
  98 tgts_per_mshr=20
  99 two_queue=false
 100 write_buffers=8
 101 cpu_side=system.cpu0.dcache_port
 102 mem_side=system.toL2Bus.slave[1]
 103
 104 [system.cpu0.dcache.tags]
 105 type=LRU
 106 assoc=4
 107 block_size=64
 108 clk_domain=system.cpu_clk_domain
 109 eventq_index=0
 110 hit_latency=2
 111 sequential_access=false
 112 size=32768
 113
 114 [system.cpu0.dtb]
 115 type=SparcTLB
 116 eventq_index=0
 117 size=64
 118
 119 [system.cpu0.icache]
 120 type=BaseCache
 121 children=tags
 122 addr_ranges=0:18446744073709551615
 123 assoc=1
 124 clk_domain=system.cpu_clk_domain
 125 eventq_index=0
 126 forward_snoops=true
 127 hit_latency=2
 128 is_top_level=true
 129 max_miss_count=0
 130 mshrs=4
 131 prefetch_on_access=false
 132 prefetcher=Null
 133 response_latency=2
 134 sequential_access=false
 135 size=32768
 136 system=system
 137 tags=system.cpu0.icache.tags
 138 tgts_per_mshr=20
 139 two_queue=false
 140 write_buffers=8
 141 cpu_side=system.cpu0.icache_port
 142 mem_side=system.toL2Bus.slave[0]
 143
 144 [system.cpu0.icache.tags]
 145 type=LRU
 146 assoc=1
 147 block_size=64
 148 clk_domain=system.cpu_clk_domain
 149 eventq_index=0
 150 hit_latency=2
 151 sequential_access=false
 152 size=32768
 153
 154 [system.cpu0.interrupts]
 155 type=SparcInterrupts
 156 eventq_index=0
 157
 158 [system.cpu0.isa]
 159 type=SparcISA
 160 eventq_index=0
 161
 162 [system.cpu0.itb]
 163 type=SparcTLB
 164 eventq_index=0
 165 size=64
 166
 167 [system.cpu0.tracer]
 168 type=ExeTracer
 169 eventq_index=0
 170
 171 [system.cpu0.workload]
 172 type=LiveProcess
 173 cmd=test_atomic 4
 174 cwd=
 175 egid=100
 176 env=
 177 errout=cerr
 178 euid=100
 179 eventq_index=0
 180 executable=/scratch/nilay/GEM5/gem5/tests/test-progs/m5threads/bin/sparc/linux/test_atomic
 181 gid=100
 182 input=cin
 183 max_stack_size=67108864
 184 output=cout
 185 pid=100
 186 ppid=99
 187 simpoint=0
 188 system=system
 189 uid=100
 190
 191 [system.cpu1]
 192 type=TimingSimpleCPU
 193 children=dcache dtb icache interrupts isa itb tracer
 194 branchPred=Null
 195 checker=Null
 196 clk_domain=system.cpu_clk_domain
 197 cpu_id=1
 198 do_checkpoint_insts=true
 199 do_quiesce=true
 200 do_statistics_insts=true
 201 dtb=system.cpu1.dtb
 202 eventq_index=0
 203 function_trace=false
 204 function_trace_start=0
 205 interrupts=system.cpu1.interrupts
 206 isa=system.cpu1.isa
 207 itb=system.cpu1.itb
 208 max_insts_all_threads=0
 209 max_insts_any_thread=0
 210 max_loads_all_threads=0
 211 max_loads_any_thread=0
 212 numThreads=1
 213 profile=0
 214 progress_interval=0
 215 simpoint_start_insts=
 216 socket_id=0
 217 switched_out=false
 218 system=system
 219 tracer=system.cpu1.tracer
 220 workload=system.cpu0.workload
 221 dcache_port=system.cpu1.dcache.cpu_side
 222 icache_port=system.cpu1.icache.cpu_side
 223
 224 [system.cpu1.dcache]
 225 type=BaseCache
 226 children=tags
 227 addr_ranges=0:18446744073709551615
 228 assoc=4
 229 clk_domain=system.cpu_clk_domain
 230 eventq_index=0
 231 forward_snoops=true
 232 hit_latency=2
 233 is_top_level=true
 234 max_miss_count=0
 235 mshrs=4
 236 prefetch_on_access=false
 237 prefetcher=Null
 238 response_latency=2
 239 sequential_access=false
 240 size=32768
 241 system=system
 242 tags=system.cpu1.dcache.tags
 243 tgts_per_mshr=20
 244 two_queue=false
 245 write_buffers=8
 246 cpu_side=system.cpu1.dcache_port
 247 mem_side=system.toL2Bus.slave[3]
 248
 249 [system.cpu1.dcache.tags]
 250 type=LRU
 251 assoc=4
 252 block_size=64
 253 clk_domain=system.cpu_clk_domain
 254 eventq_index=0
 255 hit_latency=2
 256 sequential_access=false
 257 size=32768
 258
 259 [system.cpu1.dtb]
 260 type=SparcTLB
 261 eventq_index=0
 262 size=64
 263
 264 [system.cpu1.icache]
 265 type=BaseCache
 266 children=tags
 267 addr_ranges=0:18446744073709551615
 268 assoc=1
 269 clk_domain=system.cpu_clk_domain
 270 eventq_index=0
 271 forward_snoops=true
 272 hit_latency=2
 273 is_top_level=true
 274 max_miss_count=0
 275 mshrs=4
 276 prefetch_on_access=false
 277 prefetcher=Null
 278 response_latency=2
 279 sequential_access=false
 280 size=32768
 281 system=system
 282 tags=system.cpu1.icache.tags
 283 tgts_per_mshr=20
 284 two_queue=false
 285 write_buffers=8
 286 cpu_side=system.cpu1.icache_port
 287 mem_side=system.toL2Bus.slave[2]
 288
 289 [system.cpu1.icache.tags]
 290 type=LRU
 291 assoc=1
 292 block_size=64
 293 clk_domain=system.cpu_clk_domain
 294 eventq_index=0
 295 hit_latency=2
 296 sequential_access=false
 297 size=32768
 298
 299 [system.cpu1.interrupts]
 300 type=SparcInterrupts
 301 eventq_index=0
 302
 303 [system.cpu1.isa]
 304 type=SparcISA
 305 eventq_index=0
 306
 307 [system.cpu1.itb]
 308 type=SparcTLB
 309 eventq_index=0
 310 size=64
 311
 312 [system.cpu1.tracer]
 313 type=ExeTracer
 314 eventq_index=0
 315
 316 [system.cpu2]
 317 type=TimingSimpleCPU
 318 children=dcache dtb icache interrupts isa itb tracer
 319 branchPred=Null
 320 checker=Null
 321 clk_domain=system.cpu_clk_domain
 322 cpu_id=2
 323 do_checkpoint_insts=true
 324 do_quiesce=true
 325 do_statistics_insts=true
 326 dtb=system.cpu2.dtb
 327 eventq_index=0
 328 function_trace=false
 329 function_trace_start=0
 330 interrupts=system.cpu2.interrupts
 331 isa=system.cpu2.isa
 332 itb=system.cpu2.itb
 333 max_insts_all_threads=0
 334 max_insts_any_thread=0
 335 max_loads_all_threads=0
 336 max_loads_any_thread=0
 337 numThreads=1
 338 profile=0
 339 progress_interval=0
 340 simpoint_start_insts=
 341 socket_id=0
 342 switched_out=false
 343 system=system
 344 tracer=system.cpu2.tracer
 345 workload=system.cpu0.workload
 346 dcache_port=system.cpu2.dcache.cpu_side
 347 icache_port=system.cpu2.icache.cpu_side
 348
 349 [system.cpu2.dcache]
 350 type=BaseCache
 351 children=tags
 352 addr_ranges=0:18446744073709551615
 353 assoc=4
 354 clk_domain=system.cpu_clk_domain
 355 eventq_index=0
 356 forward_snoops=true
 357 hit_latency=2
 358 is_top_level=true
 359 max_miss_count=0
 360 mshrs=4
 361 prefetch_on_access=false
 362 prefetcher=Null
 363 response_latency=2
 364 sequential_access=false
 365 size=32768
 366 system=system
 367 tags=system.cpu2.dcache.tags
 368 tgts_per_mshr=20
 369 two_queue=false
 370 write_buffers=8
 371 cpu_side=system.cpu2.dcache_port
 372 mem_side=system.toL2Bus.slave[5]
 373
 374 [system.cpu2.dcache.tags]
 375 type=LRU
 376 assoc=4
 377 block_size=64
 378 clk_domain=system.cpu_clk_domain
 379 eventq_index=0
 380 hit_latency=2
 381 sequential_access=false
 382 size=32768
 383
 384 [system.cpu2.dtb]
 385 type=SparcTLB
 386 eventq_index=0
 387 size=64
 388
 389 [system.cpu2.icache]
 390 type=BaseCache
 391 children=tags
 392 addr_ranges=0:18446744073709551615
 393 assoc=1
 394 clk_domain=system.cpu_clk_domain
 395 eventq_index=0
 396 forward_snoops=true
 397 hit_latency=2
 398 is_top_level=true
 399 max_miss_count=0
 400 mshrs=4
 401 prefetch_on_access=false
 402 prefetcher=Null
 403 response_latency=2
 404 sequential_access=false
 405 size=32768
 406 system=system
 407 tags=system.cpu2.icache.tags
 408 tgts_per_mshr=20
 409 two_queue=false
 410 write_buffers=8
 411 cpu_side=system.cpu2.icache_port
 412 mem_side=system.toL2Bus.slave[4]
 413
 414 [system.cpu2.icache.tags]
 415 type=LRU
 416 assoc=1
 417 block_size=64
 418 clk_domain=system.cpu_clk_domain
 419 eventq_index=0
 420 hit_latency=2
 421 sequential_access=false
 422 size=32768
 423
 424 [system.cpu2.interrupts]
 425 type=SparcInterrupts
 426 eventq_index=0
 427
 428 [system.cpu2.isa]
 429 type=SparcISA
 430 eventq_index=0
 431
 432 [system.cpu2.itb]
 433 type=SparcTLB
 434 eventq_index=0
 435 size=64
 436
 437 [system.cpu2.tracer]
 438 type=ExeTracer
 439 eventq_index=0
 440
 441 [system.cpu3]
 442 type=TimingSimpleCPU
 443 children=dcache dtb icache interrupts isa itb tracer
 444 branchPred=Null
 445 checker=Null
 446 clk_domain=system.cpu_clk_domain
 447 cpu_id=3
 448 do_checkpoint_insts=true
 449 do_quiesce=true
 450 do_statistics_insts=true
 451 dtb=system.cpu3.dtb
 452 eventq_index=0
 453 function_trace=false
 454 function_trace_start=0
 455 interrupts=system.cpu3.interrupts
 456 isa=system.cpu3.isa
 457 itb=system.cpu3.itb
 458 max_insts_all_threads=0
 459 max_insts_any_thread=0
 460 max_loads_all_threads=0
 461 max_loads_any_thread=0
 462 numThreads=1
 463 profile=0
 464 progress_interval=0
 465 simpoint_start_insts=
 466 socket_id=0
 467 switched_out=false
 468 system=system
 469 tracer=system.cpu3.tracer
 470 workload=system.cpu0.workload
 471 dcache_port=system.cpu3.dcache.cpu_side
 472 icache_port=system.cpu3.icache.cpu_side
 473
 474 [system.cpu3.dcache]
 475 type=BaseCache
 476 children=tags
 477 addr_ranges=0:18446744073709551615
 478 assoc=4
 479 clk_domain=system.cpu_clk_domain
 480 eventq_index=0
 481 forward_snoops=true
 482 hit_latency=2
 483 is_top_level=true
 484 max_miss_count=0
 485 mshrs=4
 486 prefetch_on_access=false
 487 prefetcher=Null
 488 response_latency=2
 489 sequential_access=false
 490 size=32768
 491 system=system
 492 tags=system.cpu3.dcache.tags
 493 tgts_per_mshr=20
 494 two_queue=false
 495 write_buffers=8
 496 cpu_side=system.cpu3.dcache_port
 497 mem_side=system.toL2Bus.slave[7]
 498
 499 [system.cpu3.dcache.tags]
 500 type=LRU
 501 assoc=4
 502 block_size=64
 503 clk_domain=system.cpu_clk_domain
 504 eventq_index=0
 505 hit_latency=2
 506 sequential_access=false
 507 size=32768
 508
 509 [system.cpu3.dtb]
 510 type=SparcTLB
 511 eventq_index=0
 512 size=64
 513
 514 [system.cpu3.icache]
 515 type=BaseCache
 516 children=tags
 517 addr_ranges=0:18446744073709551615
 518 assoc=1
 519 clk_domain=system.cpu_clk_domain
 520 eventq_index=0
 521 forward_snoops=true
 522 hit_latency=2
 523 is_top_level=true
 524 max_miss_count=0
 525 mshrs=4
 526 prefetch_on_access=false
 527 prefetcher=Null
 528 response_latency=2
 529 sequential_access=false
 530 size=32768
 531 system=system
 532 tags=system.cpu3.icache.tags
 533 tgts_per_mshr=20
 534 two_queue=false
 535 write_buffers=8
 536 cpu_side=system.cpu3.icache_port
 537 mem_side=system.toL2Bus.slave[6]
 538
 539 [system.cpu3.icache.tags]
 540 type=LRU
 541 assoc=1
 542 block_size=64
 543 clk_domain=system.cpu_clk_domain
 544 eventq_index=0
 545 hit_latency=2
 546 sequential_access=false
 547 size=32768
 548
 549 [system.cpu3.interrupts]
 550 type=SparcInterrupts
 551 eventq_index=0
 552
 553 [system.cpu3.isa]
 554 type=SparcISA
 555 eventq_index=0
 556
 557 [system.cpu3.itb]
 558 type=SparcTLB
 559 eventq_index=0
 560 size=64
 561
 562 [system.cpu3.tracer]
 563 type=ExeTracer
 564 eventq_index=0
 565
 566 [system.cpu_clk_domain]
 567 type=SrcClockDomain
 568 clock=500
 569 domain_id=-1
 570 eventq_index=0
 571 init_perf_level=0
 572 voltage_domain=system.voltage_domain
 573
 574 [system.dvfs_handler]
 575 type=DVFSHandler
 576 domains=
 577 enable=false
 578 eventq_index=0
 579 sys_clk_domain=system.clk_domain
 580 transition_latency=100000000
 581
 582 [system.l2c]
 583 type=BaseCache
 584 children=tags
 585 addr_ranges=0:18446744073709551615
 586 assoc=8
 587 clk_domain=system.cpu_clk_domain
 588 eventq_index=0
 589 forward_snoops=true
 590 hit_latency=20
 591 is_top_level=false
 592 max_miss_count=0
 593 mshrs=20
 594 prefetch_on_access=false
 595 prefetcher=Null
 596 response_latency=20
 597 sequential_access=false
 598 size=4194304
 599 system=system
 600 tags=system.l2c.tags
 601 tgts_per_mshr=12
 602 two_queue=false
 603 write_buffers=8
 604 cpu_side=system.toL2Bus.master[0]
 605 mem_side=system.membus.slave[1]
 606
 607 [system.l2c.tags]
 608 type=LRU
 609 assoc=8
 610 block_size=64
 611 clk_domain=system.cpu_clk_domain
 612 eventq_index=0
 613 hit_latency=20
 614 sequential_access=false
 615 size=4194304
 616
 617 [system.membus]
 618 type=CoherentBus
 619 clk_domain=system.clk_domain
 620 eventq_index=0
 621 header_cycles=1
 622 system=system
 623 use_default_range=false
 624 width=8
 625 master=system.physmem.port
 626 slave=system.system_port system.l2c.mem_side
 627
 628 [system.physmem]
 629 type=SimpleMemory
 630 bandwidth=73.000000
 631 clk_domain=system.clk_domain
 632 conf_table_reported=true
 633 eventq_index=0
 634 in_addr_map=true
 635 latency=30000
 636 latency_var=0
 637 null=false
 638 range=0:134217727
 639 port=system.membus.master[0]
 640
 641 [system.toL2Bus]
 642 type=CoherentBus
 643 clk_domain=system.cpu_clk_domain
 644 eventq_index=0
 645 header_cycles=1
 646 system=system
 647 use_default_range=false
 648 width=8
 649 master=system.l2c.cpu_side
 650 slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side
 651
 652 [system.voltage_domain]
 653 type=VoltageDomain
 654 eventq_index=0
 655 voltage=1.000000
 656