2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.000263 # Number of seconds simulated
4 sim_ticks 262793500 # Number of ticks simulated
5 final_tick 262793500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 1021127 # Simulator instruction rate (inst/s)
8 host_op_rate 1021105 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 404381057 # Simulator tick rate (ticks/s)
10 host_mem_usage 299844 # Number of bytes of host memory used
11 host_seconds 0.65 # Real time elapsed on the host
12 sim_insts 663567 # Number of instructions simulated
13 sim_ops 663567 # Number of ops (including micro ops) simulated
14 system.voltage_domain.voltage 1 # Voltage in Volts
15 system.clk_domain.clock 1000 # Clock period in ticks
16 system.physmem.bytes_read::cpu0.inst 18240 # Number of bytes read from this memory
17 system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory
18 system.physmem.bytes_read::cpu1.inst 3776 # Number of bytes read from this memory
19 system.physmem.bytes_read::cpu1.data 1408 # Number of bytes read from this memory
20 system.physmem.bytes_read::cpu2.inst 128 # Number of bytes read from this memory
21 system.physmem.bytes_read::cpu2.data 960 # Number of bytes read from this memory
22 system.physmem.bytes_read::cpu3.inst 512 # Number of bytes read from this memory
23 system.physmem.bytes_read::cpu3.data 1024 # Number of bytes read from this memory
24 system.physmem.bytes_read::total 36608 # Number of bytes read from this memory
25 system.physmem.bytes_inst_read::cpu0.inst 18240 # Number of instructions bytes read from this memory
26 system.physmem.bytes_inst_read::cpu1.inst 3776 # Number of instructions bytes read from this memory
27 system.physmem.bytes_inst_read::cpu2.inst 128 # Number of instructions bytes read from this memory
28 system.physmem.bytes_inst_read::cpu3.inst 512 # Number of instructions bytes read from this memory
29 system.physmem.bytes_inst_read::total 22656 # Number of instructions bytes read from this memory
30 system.physmem.num_reads::cpu0.inst 285 # Number of read requests responded to by this memory
31 system.physmem.num_reads::cpu0.data 165 # Number of read requests responded to by this memory
32 system.physmem.num_reads::cpu1.inst 59 # Number of read requests responded to by this memory
33 system.physmem.num_reads::cpu1.data 22 # Number of read requests responded to by this memory
34 system.physmem.num_reads::cpu2.inst 2 # Number of read requests responded to by this memory
35 system.physmem.num_reads::cpu2.data 15 # Number of read requests responded to by this memory
36 system.physmem.num_reads::cpu3.inst 8 # Number of read requests responded to by this memory
37 system.physmem.num_reads::cpu3.data 16 # Number of read requests responded to by this memory
38 system.physmem.num_reads::total 572 # Number of read requests responded to by this memory
39 system.physmem.bw_read::cpu0.inst 69408109 # Total read bandwidth from this memory (bytes/s)
40 system.physmem.bw_read::cpu0.data 40183642 # Total read bandwidth from this memory (bytes/s)
41 system.physmem.bw_read::cpu1.inst 14368696 # Total read bandwidth from this memory (bytes/s)
42 system.physmem.bw_read::cpu1.data 5357819 # Total read bandwidth from this memory (bytes/s)
43 system.physmem.bw_read::cpu2.inst 487074 # Total read bandwidth from this memory (bytes/s)
44 system.physmem.bw_read::cpu2.data 3653058 # Total read bandwidth from this memory (bytes/s)
45 system.physmem.bw_read::cpu3.inst 1948298 # Total read bandwidth from this memory (bytes/s)
46 system.physmem.bw_read::cpu3.data 3896596 # Total read bandwidth from this memory (bytes/s)
47 system.physmem.bw_read::total 139303293 # Total read bandwidth from this memory (bytes/s)
48 system.physmem.bw_inst_read::cpu0.inst 69408109 # Instruction read bandwidth from this memory (bytes/s)
49 system.physmem.bw_inst_read::cpu1.inst 14368696 # Instruction read bandwidth from this memory (bytes/s)
50 system.physmem.bw_inst_read::cpu2.inst 487074 # Instruction read bandwidth from this memory (bytes/s)
51 system.physmem.bw_inst_read::cpu3.inst 1948298 # Instruction read bandwidth from this memory (bytes/s)
52 system.physmem.bw_inst_read::total 86212178 # Instruction read bandwidth from this memory (bytes/s)
53 system.physmem.bw_total::cpu0.inst 69408109 # Total bandwidth to/from this memory (bytes/s)
54 system.physmem.bw_total::cpu0.data 40183642 # Total bandwidth to/from this memory (bytes/s)
55 system.physmem.bw_total::cpu1.inst 14368696 # Total bandwidth to/from this memory (bytes/s)
56 system.physmem.bw_total::cpu1.data 5357819 # Total bandwidth to/from this memory (bytes/s)
57 system.physmem.bw_total::cpu2.inst 487074 # Total bandwidth to/from this memory (bytes/s)
58 system.physmem.bw_total::cpu2.data 3653058 # Total bandwidth to/from this memory (bytes/s)
59 system.physmem.bw_total::cpu3.inst 1948298 # Total bandwidth to/from this memory (bytes/s)
60 system.physmem.bw_total::cpu3.data 3896596 # Total bandwidth to/from this memory (bytes/s)
61 system.physmem.bw_total::total 139303293 # Total bandwidth to/from this memory (bytes/s)
62 system.membus.trans_dist::ReadReq 430 # Transaction distribution
63 system.membus.trans_dist::ReadResp 430 # Transaction distribution
64 system.membus.trans_dist::UpgradeReq 272 # Transaction distribution
65 system.membus.trans_dist::UpgradeResp 77 # Transaction distribution
66 system.membus.trans_dist::ReadExReq 208 # Transaction distribution
67 system.membus.trans_dist::ReadExResp 142 # Transaction distribution
68 system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1559 # Packet count per connected master and slave (bytes)
69 system.membus.pkt_count::total 1559 # Packet count per connected master and slave (bytes)
70 system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 36608 # Cumulative packet size per connected master and slave (bytes)
71 system.membus.pkt_size::total 36608 # Cumulative packet size per connected master and slave (bytes)
72 system.membus.snoops 261 # Total snoops (count)
73 system.membus.snoop_fanout::samples 915 # Request fanout histogram
74 system.membus.snoop_fanout::mean 0 # Request fanout histogram
75 system.membus.snoop_fanout::stdev 0 # Request fanout histogram
76 system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
77 system.membus.snoop_fanout::0 915 100.00% 100.00% # Request fanout histogram
78 system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
79 system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
80 system.membus.snoop_fanout::min_value 0 # Request fanout histogram
81 system.membus.snoop_fanout::max_value 0 # Request fanout histogram
82 system.membus.snoop_fanout::total 915 # Request fanout histogram
83 system.membus.reqLayer0.occupancy 852796 # Layer occupancy (ticks)
84 system.membus.reqLayer0.utilization 0.3 # Layer utilization (%)
85 system.membus.respLayer1.occupancy 5420500 # Layer occupancy (ticks)
86 system.membus.respLayer1.utilization 2.1 # Layer utilization (%)
87 system.cpu_clk_domain.clock 500 # Clock period in ticks
88 system.l2c.tags.replacements 0 # number of replacements
89 system.l2c.tags.tagsinuse 349.046261 # Cycle average of tags in use
90 system.l2c.tags.total_refs 1220 # Total number of references to valid blocks.
91 system.l2c.tags.sampled_refs 429 # Sample count of references to valid blocks.
92 system.l2c.tags.avg_refs 2.843823 # Average number of references to valid blocks.
93 system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
94 system.l2c.tags.occ_blocks::writebacks 0.889004 # Average occupied blocks per requestor
95 system.l2c.tags.occ_blocks::cpu0.inst 231.790402 # Average occupied blocks per requestor
96 system.l2c.tags.occ_blocks::cpu0.data 54.207937 # Average occupied blocks per requestor
97 system.l2c.tags.occ_blocks::cpu1.inst 51.556867 # Average occupied blocks per requestor
98 system.l2c.tags.occ_blocks::cpu1.data 6.123938 # Average occupied blocks per requestor
99 system.l2c.tags.occ_blocks::cpu2.inst 1.773027 # Average occupied blocks per requestor
100 system.l2c.tags.occ_blocks::cpu2.data 0.843763 # Average occupied blocks per requestor
101 system.l2c.tags.occ_blocks::cpu3.inst 1.030296 # Average occupied blocks per requestor
102 system.l2c.tags.occ_blocks::cpu3.data 0.831027 # Average occupied blocks per requestor
103 system.l2c.tags.occ_percent::writebacks 0.000014 # Average percentage of cache occupancy
104 system.l2c.tags.occ_percent::cpu0.inst 0.003537 # Average percentage of cache occupancy
105 system.l2c.tags.occ_percent::cpu0.data 0.000827 # Average percentage of cache occupancy
106 system.l2c.tags.occ_percent::cpu1.inst 0.000787 # Average percentage of cache occupancy
107 system.l2c.tags.occ_percent::cpu1.data 0.000093 # Average percentage of cache occupancy
108 system.l2c.tags.occ_percent::cpu2.inst 0.000027 # Average percentage of cache occupancy
109 system.l2c.tags.occ_percent::cpu2.data 0.000013 # Average percentage of cache occupancy
110 system.l2c.tags.occ_percent::cpu3.inst 0.000016 # Average percentage of cache occupancy
111 system.l2c.tags.occ_percent::cpu3.data 0.000013 # Average percentage of cache occupancy
112 system.l2c.tags.occ_percent::total 0.005326 # Average percentage of cache occupancy
113 system.l2c.tags.occ_task_id_blocks::1024 429 # Occupied blocks per task id
114 system.l2c.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id
115 system.l2c.tags.age_task_id_blocks_1024::2 374 # Occupied blocks per task id
116 system.l2c.tags.occ_task_id_percent::1024 0.006546 # Percentage of cache occupancy per task id
117 system.l2c.tags.tag_accesses 15709 # Number of tag accesses
118 system.l2c.tags.data_accesses 15709 # Number of data accesses
119 system.l2c.ReadReq_hits::cpu0.inst 182 # number of ReadReq hits
120 system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits
121 system.l2c.ReadReq_hits::cpu1.inst 300 # number of ReadReq hits
122 system.l2c.ReadReq_hits::cpu1.data 3 # number of ReadReq hits
123 system.l2c.ReadReq_hits::cpu2.inst 354 # number of ReadReq hits
124 system.l2c.ReadReq_hits::cpu2.data 9 # number of ReadReq hits
125 system.l2c.ReadReq_hits::cpu3.inst 358 # number of ReadReq hits
126 system.l2c.ReadReq_hits::cpu3.data 9 # number of ReadReq hits
127 system.l2c.ReadReq_hits::total 1220 # number of ReadReq hits
128 system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits
129 system.l2c.Writeback_hits::total 1 # number of Writeback hits
130 system.l2c.UpgradeReq_hits::cpu0.data 2 # number of UpgradeReq hits
131 system.l2c.UpgradeReq_hits::total 2 # number of UpgradeReq hits
132 system.l2c.demand_hits::cpu0.inst 182 # number of demand (read+write) hits
133 system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits
134 system.l2c.demand_hits::cpu1.inst 300 # number of demand (read+write) hits
135 system.l2c.demand_hits::cpu1.data 3 # number of demand (read+write) hits
136 system.l2c.demand_hits::cpu2.inst 354 # number of demand (read+write) hits
137 system.l2c.demand_hits::cpu2.data 9 # number of demand (read+write) hits
138 system.l2c.demand_hits::cpu3.inst 358 # number of demand (read+write) hits
139 system.l2c.demand_hits::cpu3.data 9 # number of demand (read+write) hits
140 system.l2c.demand_hits::total 1220 # number of demand (read+write) hits
141 system.l2c.overall_hits::cpu0.inst 182 # number of overall hits
142 system.l2c.overall_hits::cpu0.data 5 # number of overall hits
143 system.l2c.overall_hits::cpu1.inst 300 # number of overall hits
144 system.l2c.overall_hits::cpu1.data 3 # number of overall hits
145 system.l2c.overall_hits::cpu2.inst 354 # number of overall hits
146 system.l2c.overall_hits::cpu2.data 9 # number of overall hits
147 system.l2c.overall_hits::cpu3.inst 358 # number of overall hits
148 system.l2c.overall_hits::cpu3.data 9 # number of overall hits
149 system.l2c.overall_hits::total 1220 # number of overall hits
150 system.l2c.ReadReq_misses::cpu0.inst 285 # number of ReadReq misses
151 system.l2c.ReadReq_misses::cpu0.data 66 # number of ReadReq misses
152 system.l2c.ReadReq_misses::cpu1.inst 66 # number of ReadReq misses
153 system.l2c.ReadReq_misses::cpu1.data 8 # number of ReadReq misses
154 system.l2c.ReadReq_misses::cpu2.inst 12 # number of ReadReq misses
155 system.l2c.ReadReq_misses::cpu2.data 2 # number of ReadReq misses
156 system.l2c.ReadReq_misses::cpu3.inst 9 # number of ReadReq misses
157 system.l2c.ReadReq_misses::cpu3.data 2 # number of ReadReq misses
158 system.l2c.ReadReq_misses::total 450 # number of ReadReq misses
159 system.l2c.UpgradeReq_misses::cpu0.data 28 # number of UpgradeReq misses
160 system.l2c.UpgradeReq_misses::cpu1.data 15 # number of UpgradeReq misses
161 system.l2c.UpgradeReq_misses::cpu2.data 15 # number of UpgradeReq misses
162 system.l2c.UpgradeReq_misses::cpu3.data 19 # number of UpgradeReq misses
163 system.l2c.UpgradeReq_misses::total 77 # number of UpgradeReq misses
164 system.l2c.ReadExReq_misses::cpu0.data 99 # number of ReadExReq misses
165 system.l2c.ReadExReq_misses::cpu1.data 15 # number of ReadExReq misses
166 system.l2c.ReadExReq_misses::cpu2.data 14 # number of ReadExReq misses
167 system.l2c.ReadExReq_misses::cpu3.data 14 # number of ReadExReq misses
168 system.l2c.ReadExReq_misses::total 142 # number of ReadExReq misses
169 system.l2c.demand_misses::cpu0.inst 285 # number of demand (read+write) misses
170 system.l2c.demand_misses::cpu0.data 165 # number of demand (read+write) misses
171 system.l2c.demand_misses::cpu1.inst 66 # number of demand (read+write) misses
172 system.l2c.demand_misses::cpu1.data 23 # number of demand (read+write) misses
173 system.l2c.demand_misses::cpu2.inst 12 # number of demand (read+write) misses
174 system.l2c.demand_misses::cpu2.data 16 # number of demand (read+write) misses
175 system.l2c.demand_misses::cpu3.inst 9 # number of demand (read+write) misses
176 system.l2c.demand_misses::cpu3.data 16 # number of demand (read+write) misses
177 system.l2c.demand_misses::total 592 # number of demand (read+write) misses
178 system.l2c.overall_misses::cpu0.inst 285 # number of overall misses
179 system.l2c.overall_misses::cpu0.data 165 # number of overall misses
180 system.l2c.overall_misses::cpu1.inst 66 # number of overall misses
181 system.l2c.overall_misses::cpu1.data 23 # number of overall misses
182 system.l2c.overall_misses::cpu2.inst 12 # number of overall misses
183 system.l2c.overall_misses::cpu2.data 16 # number of overall misses
184 system.l2c.overall_misses::cpu3.inst 9 # number of overall misses
185 system.l2c.overall_misses::cpu3.data 16 # number of overall misses
186 system.l2c.overall_misses::total 592 # number of overall misses
187 system.l2c.ReadReq_miss_latency::cpu0.inst 14927000 # number of ReadReq miss cycles
188 system.l2c.ReadReq_miss_latency::cpu0.data 3451500 # number of ReadReq miss cycles
189 system.l2c.ReadReq_miss_latency::cpu1.inst 3434000 # number of ReadReq miss cycles
190 system.l2c.ReadReq_miss_latency::cpu1.data 418000 # number of ReadReq miss cycles
191 system.l2c.ReadReq_miss_latency::cpu2.inst 595000 # number of ReadReq miss cycles
192 system.l2c.ReadReq_miss_latency::cpu2.data 103000 # number of ReadReq miss cycles
193 system.l2c.ReadReq_miss_latency::cpu3.inst 465000 # number of ReadReq miss cycles
194 system.l2c.ReadReq_miss_latency::cpu3.data 104500 # number of ReadReq miss cycles
195 system.l2c.ReadReq_miss_latency::total 23498000 # number of ReadReq miss cycles
196 system.l2c.ReadExReq_miss_latency::cpu0.data 5172500 # number of ReadExReq miss cycles
197 system.l2c.ReadExReq_miss_latency::cpu1.data 800500 # number of ReadExReq miss cycles
198 system.l2c.ReadExReq_miss_latency::cpu2.data 746000 # number of ReadExReq miss cycles
199 system.l2c.ReadExReq_miss_latency::cpu3.data 730500 # number of ReadExReq miss cycles
200 system.l2c.ReadExReq_miss_latency::total 7449500 # number of ReadExReq miss cycles
201 system.l2c.demand_miss_latency::cpu0.inst 14927000 # number of demand (read+write) miss cycles
202 system.l2c.demand_miss_latency::cpu0.data 8624000 # number of demand (read+write) miss cycles
203 system.l2c.demand_miss_latency::cpu1.inst 3434000 # number of demand (read+write) miss cycles
204 system.l2c.demand_miss_latency::cpu1.data 1218500 # number of demand (read+write) miss cycles
205 system.l2c.demand_miss_latency::cpu2.inst 595000 # number of demand (read+write) miss cycles
206 system.l2c.demand_miss_latency::cpu2.data 849000 # number of demand (read+write) miss cycles
207 system.l2c.demand_miss_latency::cpu3.inst 465000 # number of demand (read+write) miss cycles
208 system.l2c.demand_miss_latency::cpu3.data 835000 # number of demand (read+write) miss cycles
209 system.l2c.demand_miss_latency::total 30947500 # number of demand (read+write) miss cycles
210 system.l2c.overall_miss_latency::cpu0.inst 14927000 # number of overall miss cycles
211 system.l2c.overall_miss_latency::cpu0.data 8624000 # number of overall miss cycles
212 system.l2c.overall_miss_latency::cpu1.inst 3434000 # number of overall miss cycles
213 system.l2c.overall_miss_latency::cpu1.data 1218500 # number of overall miss cycles
214 system.l2c.overall_miss_latency::cpu2.inst 595000 # number of overall miss cycles
215 system.l2c.overall_miss_latency::cpu2.data 849000 # number of overall miss cycles
216 system.l2c.overall_miss_latency::cpu3.inst 465000 # number of overall miss cycles
217 system.l2c.overall_miss_latency::cpu3.data 835000 # number of overall miss cycles
218 system.l2c.overall_miss_latency::total 30947500 # number of overall miss cycles
219 system.l2c.ReadReq_accesses::cpu0.inst 467 # number of ReadReq accesses(hits+misses)
220 system.l2c.ReadReq_accesses::cpu0.data 71 # number of ReadReq accesses(hits+misses)
221 system.l2c.ReadReq_accesses::cpu1.inst 366 # number of ReadReq accesses(hits+misses)
222 system.l2c.ReadReq_accesses::cpu1.data 11 # number of ReadReq accesses(hits+misses)
223 system.l2c.ReadReq_accesses::cpu2.inst 366 # number of ReadReq accesses(hits+misses)
224 system.l2c.ReadReq_accesses::cpu2.data 11 # number of ReadReq accesses(hits+misses)
225 system.l2c.ReadReq_accesses::cpu3.inst 367 # number of ReadReq accesses(hits+misses)
226 system.l2c.ReadReq_accesses::cpu3.data 11 # number of ReadReq accesses(hits+misses)
227 system.l2c.ReadReq_accesses::total 1670 # number of ReadReq accesses(hits+misses)
228 system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses)
229 system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses)
230 system.l2c.UpgradeReq_accesses::cpu0.data 30 # number of UpgradeReq accesses(hits+misses)
231 system.l2c.UpgradeReq_accesses::cpu1.data 15 # number of UpgradeReq accesses(hits+misses)
232 system.l2c.UpgradeReq_accesses::cpu2.data 15 # number of UpgradeReq accesses(hits+misses)
233 system.l2c.UpgradeReq_accesses::cpu3.data 19 # number of UpgradeReq accesses(hits+misses)
234 system.l2c.UpgradeReq_accesses::total 79 # number of UpgradeReq accesses(hits+misses)
235 system.l2c.ReadExReq_accesses::cpu0.data 99 # number of ReadExReq accesses(hits+misses)
236 system.l2c.ReadExReq_accesses::cpu1.data 15 # number of ReadExReq accesses(hits+misses)
237 system.l2c.ReadExReq_accesses::cpu2.data 14 # number of ReadExReq accesses(hits+misses)
238 system.l2c.ReadExReq_accesses::cpu3.data 14 # number of ReadExReq accesses(hits+misses)
239 system.l2c.ReadExReq_accesses::total 142 # number of ReadExReq accesses(hits+misses)
240 system.l2c.demand_accesses::cpu0.inst 467 # number of demand (read+write) accesses
241 system.l2c.demand_accesses::cpu0.data 170 # number of demand (read+write) accesses
242 system.l2c.demand_accesses::cpu1.inst 366 # number of demand (read+write) accesses
243 system.l2c.demand_accesses::cpu1.data 26 # number of demand (read+write) accesses
244 system.l2c.demand_accesses::cpu2.inst 366 # number of demand (read+write) accesses
245 system.l2c.demand_accesses::cpu2.data 25 # number of demand (read+write) accesses
246 system.l2c.demand_accesses::cpu3.inst 367 # number of demand (read+write) accesses
247 system.l2c.demand_accesses::cpu3.data 25 # number of demand (read+write) accesses
248 system.l2c.demand_accesses::total 1812 # number of demand (read+write) accesses
249 system.l2c.overall_accesses::cpu0.inst 467 # number of overall (read+write) accesses
250 system.l2c.overall_accesses::cpu0.data 170 # number of overall (read+write) accesses
251 system.l2c.overall_accesses::cpu1.inst 366 # number of overall (read+write) accesses
252 system.l2c.overall_accesses::cpu1.data 26 # number of overall (read+write) accesses
253 system.l2c.overall_accesses::cpu2.inst 366 # number of overall (read+write) accesses
254 system.l2c.overall_accesses::cpu2.data 25 # number of overall (read+write) accesses
255 system.l2c.overall_accesses::cpu3.inst 367 # number of overall (read+write) accesses
256 system.l2c.overall_accesses::cpu3.data 25 # number of overall (read+write) accesses
257 system.l2c.overall_accesses::total 1812 # number of overall (read+write) accesses
258 system.l2c.ReadReq_miss_rate::cpu0.inst 0.610278 # miss rate for ReadReq accesses
259 system.l2c.ReadReq_miss_rate::cpu0.data 0.929577 # miss rate for ReadReq accesses
260 system.l2c.ReadReq_miss_rate::cpu1.inst 0.180328 # miss rate for ReadReq accesses
261 system.l2c.ReadReq_miss_rate::cpu1.data 0.727273 # miss rate for ReadReq accesses
262 system.l2c.ReadReq_miss_rate::cpu2.inst 0.032787 # miss rate for ReadReq accesses
263 system.l2c.ReadReq_miss_rate::cpu2.data 0.181818 # miss rate for ReadReq accesses
264 system.l2c.ReadReq_miss_rate::cpu3.inst 0.024523 # miss rate for ReadReq accesses
265 system.l2c.ReadReq_miss_rate::cpu3.data 0.181818 # miss rate for ReadReq accesses
266 system.l2c.ReadReq_miss_rate::total 0.269461 # miss rate for ReadReq accesses
267 system.l2c.UpgradeReq_miss_rate::cpu0.data 0.933333 # miss rate for UpgradeReq accesses
268 system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses
269 system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses
270 system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses
271 system.l2c.UpgradeReq_miss_rate::total 0.974684 # miss rate for UpgradeReq accesses
272 system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses
273 system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses
274 system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses
275 system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses
276 system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
277 system.l2c.demand_miss_rate::cpu0.inst 0.610278 # miss rate for demand accesses
278 system.l2c.demand_miss_rate::cpu0.data 0.970588 # miss rate for demand accesses
279 system.l2c.demand_miss_rate::cpu1.inst 0.180328 # miss rate for demand accesses
280 system.l2c.demand_miss_rate::cpu1.data 0.884615 # miss rate for demand accesses
281 system.l2c.demand_miss_rate::cpu2.inst 0.032787 # miss rate for demand accesses
282 system.l2c.demand_miss_rate::cpu2.data 0.640000 # miss rate for demand accesses
283 system.l2c.demand_miss_rate::cpu3.inst 0.024523 # miss rate for demand accesses
284 system.l2c.demand_miss_rate::cpu3.data 0.640000 # miss rate for demand accesses
285 system.l2c.demand_miss_rate::total 0.326711 # miss rate for demand accesses
286 system.l2c.overall_miss_rate::cpu0.inst 0.610278 # miss rate for overall accesses
287 system.l2c.overall_miss_rate::cpu0.data 0.970588 # miss rate for overall accesses
288 system.l2c.overall_miss_rate::cpu1.inst 0.180328 # miss rate for overall accesses
289 system.l2c.overall_miss_rate::cpu1.data 0.884615 # miss rate for overall accesses
290 system.l2c.overall_miss_rate::cpu2.inst 0.032787 # miss rate for overall accesses
291 system.l2c.overall_miss_rate::cpu2.data 0.640000 # miss rate for overall accesses
292 system.l2c.overall_miss_rate::cpu3.inst 0.024523 # miss rate for overall accesses
293 system.l2c.overall_miss_rate::cpu3.data 0.640000 # miss rate for overall accesses
294 system.l2c.overall_miss_rate::total 0.326711 # miss rate for overall accesses
295 system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52375.438596 # average ReadReq miss latency
296 system.l2c.ReadReq_avg_miss_latency::cpu0.data 52295.454545 # average ReadReq miss latency
297 system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52030.303030 # average ReadReq miss latency
298 system.l2c.ReadReq_avg_miss_latency::cpu1.data 52250 # average ReadReq miss latency
299 system.l2c.ReadReq_avg_miss_latency::cpu2.inst 49583.333333 # average ReadReq miss latency
300 system.l2c.ReadReq_avg_miss_latency::cpu2.data 51500 # average ReadReq miss latency
301 system.l2c.ReadReq_avg_miss_latency::cpu3.inst 51666.666667 # average ReadReq miss latency
302 system.l2c.ReadReq_avg_miss_latency::cpu3.data 52250 # average ReadReq miss latency
303 system.l2c.ReadReq_avg_miss_latency::total 52217.777778 # average ReadReq miss latency
304 system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52247.474747 # average ReadExReq miss latency
305 system.l2c.ReadExReq_avg_miss_latency::cpu1.data 53366.666667 # average ReadExReq miss latency
306 system.l2c.ReadExReq_avg_miss_latency::cpu2.data 53285.714286 # average ReadExReq miss latency
307 system.l2c.ReadExReq_avg_miss_latency::cpu3.data 52178.571429 # average ReadExReq miss latency
308 system.l2c.ReadExReq_avg_miss_latency::total 52461.267606 # average ReadExReq miss latency
309 system.l2c.demand_avg_miss_latency::cpu0.inst 52375.438596 # average overall miss latency
310 system.l2c.demand_avg_miss_latency::cpu0.data 52266.666667 # average overall miss latency
311 system.l2c.demand_avg_miss_latency::cpu1.inst 52030.303030 # average overall miss latency
312 system.l2c.demand_avg_miss_latency::cpu1.data 52978.260870 # average overall miss latency
313 system.l2c.demand_avg_miss_latency::cpu2.inst 49583.333333 # average overall miss latency
314 system.l2c.demand_avg_miss_latency::cpu2.data 53062.500000 # average overall miss latency
315 system.l2c.demand_avg_miss_latency::cpu3.inst 51666.666667 # average overall miss latency
316 system.l2c.demand_avg_miss_latency::cpu3.data 52187.500000 # average overall miss latency
317 system.l2c.demand_avg_miss_latency::total 52276.182432 # average overall miss latency
318 system.l2c.overall_avg_miss_latency::cpu0.inst 52375.438596 # average overall miss latency
319 system.l2c.overall_avg_miss_latency::cpu0.data 52266.666667 # average overall miss latency
320 system.l2c.overall_avg_miss_latency::cpu1.inst 52030.303030 # average overall miss latency
321 system.l2c.overall_avg_miss_latency::cpu1.data 52978.260870 # average overall miss latency
322 system.l2c.overall_avg_miss_latency::cpu2.inst 49583.333333 # average overall miss latency
323 system.l2c.overall_avg_miss_latency::cpu2.data 53062.500000 # average overall miss latency
324 system.l2c.overall_avg_miss_latency::cpu3.inst 51666.666667 # average overall miss latency
325 system.l2c.overall_avg_miss_latency::cpu3.data 52187.500000 # average overall miss latency
326 system.l2c.overall_avg_miss_latency::total 52276.182432 # average overall miss latency
327 system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
328 system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
329 system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
330 system.l2c.blocked::no_targets 0 # number of cycles access was blocked
331 system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
332 system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
333 system.l2c.fast_writes 0 # number of fast writes performed
334 system.l2c.cache_copies 0 # number of cache copies performed
335 system.l2c.ReadReq_mshr_hits::cpu1.inst 7 # number of ReadReq MSHR hits
336 system.l2c.ReadReq_mshr_hits::cpu1.data 1 # number of ReadReq MSHR hits
337 system.l2c.ReadReq_mshr_hits::cpu2.inst 10 # number of ReadReq MSHR hits
338 system.l2c.ReadReq_mshr_hits::cpu2.data 1 # number of ReadReq MSHR hits
339 system.l2c.ReadReq_mshr_hits::cpu3.inst 1 # number of ReadReq MSHR hits
340 system.l2c.ReadReq_mshr_hits::total 20 # number of ReadReq MSHR hits
341 system.l2c.demand_mshr_hits::cpu1.inst 7 # number of demand (read+write) MSHR hits
342 system.l2c.demand_mshr_hits::cpu1.data 1 # number of demand (read+write) MSHR hits
343 system.l2c.demand_mshr_hits::cpu2.inst 10 # number of demand (read+write) MSHR hits
344 system.l2c.demand_mshr_hits::cpu2.data 1 # number of demand (read+write) MSHR hits
345 system.l2c.demand_mshr_hits::cpu3.inst 1 # number of demand (read+write) MSHR hits
346 system.l2c.demand_mshr_hits::total 20 # number of demand (read+write) MSHR hits
347 system.l2c.overall_mshr_hits::cpu1.inst 7 # number of overall MSHR hits
348 system.l2c.overall_mshr_hits::cpu1.data 1 # number of overall MSHR hits
349 system.l2c.overall_mshr_hits::cpu2.inst 10 # number of overall MSHR hits
350 system.l2c.overall_mshr_hits::cpu2.data 1 # number of overall MSHR hits
351 system.l2c.overall_mshr_hits::cpu3.inst 1 # number of overall MSHR hits
352 system.l2c.overall_mshr_hits::total 20 # number of overall MSHR hits
353 system.l2c.ReadReq_mshr_misses::cpu0.inst 285 # number of ReadReq MSHR misses
354 system.l2c.ReadReq_mshr_misses::cpu0.data 66 # number of ReadReq MSHR misses
355 system.l2c.ReadReq_mshr_misses::cpu1.inst 59 # number of ReadReq MSHR misses
356 system.l2c.ReadReq_mshr_misses::cpu1.data 7 # number of ReadReq MSHR misses
357 system.l2c.ReadReq_mshr_misses::cpu2.inst 2 # number of ReadReq MSHR misses
358 system.l2c.ReadReq_mshr_misses::cpu2.data 1 # number of ReadReq MSHR misses
359 system.l2c.ReadReq_mshr_misses::cpu3.inst 8 # number of ReadReq MSHR misses
360 system.l2c.ReadReq_mshr_misses::cpu3.data 2 # number of ReadReq MSHR misses
361 system.l2c.ReadReq_mshr_misses::total 430 # number of ReadReq MSHR misses
362 system.l2c.UpgradeReq_mshr_misses::cpu0.data 28 # number of UpgradeReq MSHR misses
363 system.l2c.UpgradeReq_mshr_misses::cpu1.data 15 # number of UpgradeReq MSHR misses
364 system.l2c.UpgradeReq_mshr_misses::cpu2.data 15 # number of UpgradeReq MSHR misses
365 system.l2c.UpgradeReq_mshr_misses::cpu3.data 19 # number of UpgradeReq MSHR misses
366 system.l2c.UpgradeReq_mshr_misses::total 77 # number of UpgradeReq MSHR misses
367 system.l2c.ReadExReq_mshr_misses::cpu0.data 99 # number of ReadExReq MSHR misses
368 system.l2c.ReadExReq_mshr_misses::cpu1.data 15 # number of ReadExReq MSHR misses
369 system.l2c.ReadExReq_mshr_misses::cpu2.data 14 # number of ReadExReq MSHR misses
370 system.l2c.ReadExReq_mshr_misses::cpu3.data 14 # number of ReadExReq MSHR misses
371 system.l2c.ReadExReq_mshr_misses::total 142 # number of ReadExReq MSHR misses
372 system.l2c.demand_mshr_misses::cpu0.inst 285 # number of demand (read+write) MSHR misses
373 system.l2c.demand_mshr_misses::cpu0.data 165 # number of demand (read+write) MSHR misses
374 system.l2c.demand_mshr_misses::cpu1.inst 59 # number of demand (read+write) MSHR misses
375 system.l2c.demand_mshr_misses::cpu1.data 22 # number of demand (read+write) MSHR misses
376 system.l2c.demand_mshr_misses::cpu2.inst 2 # number of demand (read+write) MSHR misses
377 system.l2c.demand_mshr_misses::cpu2.data 15 # number of demand (read+write) MSHR misses
378 system.l2c.demand_mshr_misses::cpu3.inst 8 # number of demand (read+write) MSHR misses
379 system.l2c.demand_mshr_misses::cpu3.data 16 # number of demand (read+write) MSHR misses
380 system.l2c.demand_mshr_misses::total 572 # number of demand (read+write) MSHR misses
381 system.l2c.overall_mshr_misses::cpu0.inst 285 # number of overall MSHR misses
382 system.l2c.overall_mshr_misses::cpu0.data 165 # number of overall MSHR misses
383 system.l2c.overall_mshr_misses::cpu1.inst 59 # number of overall MSHR misses
384 system.l2c.overall_mshr_misses::cpu1.data 22 # number of overall MSHR misses
385 system.l2c.overall_mshr_misses::cpu2.inst 2 # number of overall MSHR misses
386 system.l2c.overall_mshr_misses::cpu2.data 15 # number of overall MSHR misses
387 system.l2c.overall_mshr_misses::cpu3.inst 8 # number of overall MSHR misses
388 system.l2c.overall_mshr_misses::cpu3.data 16 # number of overall MSHR misses
389 system.l2c.overall_mshr_misses::total 572 # number of overall MSHR misses
390 system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 11414500 # number of ReadReq MSHR miss cycles
391 system.l2c.ReadReq_mshr_miss_latency::cpu0.data 2640000 # number of ReadReq MSHR miss cycles
392 system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 2368500 # number of ReadReq MSHR miss cycles
393 system.l2c.ReadReq_mshr_miss_latency::cpu1.data 280000 # number of ReadReq MSHR miss cycles
394 system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 80000 # number of ReadReq MSHR miss cycles
395 system.l2c.ReadReq_mshr_miss_latency::cpu2.data 40000 # number of ReadReq MSHR miss cycles
396 system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 320000 # number of ReadReq MSHR miss cycles
397 system.l2c.ReadReq_mshr_miss_latency::cpu3.data 80000 # number of ReadReq MSHR miss cycles
398 system.l2c.ReadReq_mshr_miss_latency::total 17223000 # number of ReadReq MSHR miss cycles
399 system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 1120000 # number of UpgradeReq MSHR miss cycles
400 system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 600499 # number of UpgradeReq MSHR miss cycles
401 system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 600000 # number of UpgradeReq MSHR miss cycles
402 system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 763992 # number of UpgradeReq MSHR miss cycles
403 system.l2c.UpgradeReq_mshr_miss_latency::total 3084491 # number of UpgradeReq MSHR miss cycles
404 system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3962500 # number of ReadExReq MSHR miss cycles
405 system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 617000 # number of ReadExReq MSHR miss cycles
406 system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 576500 # number of ReadExReq MSHR miss cycles
407 system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 560000 # number of ReadExReq MSHR miss cycles
408 system.l2c.ReadExReq_mshr_miss_latency::total 5716000 # number of ReadExReq MSHR miss cycles
409 system.l2c.demand_mshr_miss_latency::cpu0.inst 11414500 # number of demand (read+write) MSHR miss cycles
410 system.l2c.demand_mshr_miss_latency::cpu0.data 6602500 # number of demand (read+write) MSHR miss cycles
411 system.l2c.demand_mshr_miss_latency::cpu1.inst 2368500 # number of demand (read+write) MSHR miss cycles
412 system.l2c.demand_mshr_miss_latency::cpu1.data 897000 # number of demand (read+write) MSHR miss cycles
413 system.l2c.demand_mshr_miss_latency::cpu2.inst 80000 # number of demand (read+write) MSHR miss cycles
414 system.l2c.demand_mshr_miss_latency::cpu2.data 616500 # number of demand (read+write) MSHR miss cycles
415 system.l2c.demand_mshr_miss_latency::cpu3.inst 320000 # number of demand (read+write) MSHR miss cycles
416 system.l2c.demand_mshr_miss_latency::cpu3.data 640000 # number of demand (read+write) MSHR miss cycles
417 system.l2c.demand_mshr_miss_latency::total 22939000 # number of demand (read+write) MSHR miss cycles
418 system.l2c.overall_mshr_miss_latency::cpu0.inst 11414500 # number of overall MSHR miss cycles
419 system.l2c.overall_mshr_miss_latency::cpu0.data 6602500 # number of overall MSHR miss cycles
420 system.l2c.overall_mshr_miss_latency::cpu1.inst 2368500 # number of overall MSHR miss cycles
421 system.l2c.overall_mshr_miss_latency::cpu1.data 897000 # number of overall MSHR miss cycles
422 system.l2c.overall_mshr_miss_latency::cpu2.inst 80000 # number of overall MSHR miss cycles
423 system.l2c.overall_mshr_miss_latency::cpu2.data 616500 # number of overall MSHR miss cycles
424 system.l2c.overall_mshr_miss_latency::cpu3.inst 320000 # number of overall MSHR miss cycles
425 system.l2c.overall_mshr_miss_latency::cpu3.data 640000 # number of overall MSHR miss cycles
426 system.l2c.overall_mshr_miss_latency::total 22939000 # number of overall MSHR miss cycles
427 system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for ReadReq accesses
428 system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.929577 # mshr miss rate for ReadReq accesses
429 system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.161202 # mshr miss rate for ReadReq accesses
430 system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.636364 # mshr miss rate for ReadReq accesses
431 system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.005464 # mshr miss rate for ReadReq accesses
432 system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.090909 # mshr miss rate for ReadReq accesses
433 system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.021798 # mshr miss rate for ReadReq accesses
434 system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.181818 # mshr miss rate for ReadReq accesses
435 system.l2c.ReadReq_mshr_miss_rate::total 0.257485 # mshr miss rate for ReadReq accesses
436 system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.933333 # mshr miss rate for UpgradeReq accesses
437 system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses
438 system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses
439 system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses
440 system.l2c.UpgradeReq_mshr_miss_rate::total 0.974684 # mshr miss rate for UpgradeReq accesses
441 system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses
442 system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses
443 system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses
444 system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses
445 system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
446 system.l2c.demand_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for demand accesses
447 system.l2c.demand_mshr_miss_rate::cpu0.data 0.970588 # mshr miss rate for demand accesses
448 system.l2c.demand_mshr_miss_rate::cpu1.inst 0.161202 # mshr miss rate for demand accesses
449 system.l2c.demand_mshr_miss_rate::cpu1.data 0.846154 # mshr miss rate for demand accesses
450 system.l2c.demand_mshr_miss_rate::cpu2.inst 0.005464 # mshr miss rate for demand accesses
451 system.l2c.demand_mshr_miss_rate::cpu2.data 0.600000 # mshr miss rate for demand accesses
452 system.l2c.demand_mshr_miss_rate::cpu3.inst 0.021798 # mshr miss rate for demand accesses
453 system.l2c.demand_mshr_miss_rate::cpu3.data 0.640000 # mshr miss rate for demand accesses
454 system.l2c.demand_mshr_miss_rate::total 0.315673 # mshr miss rate for demand accesses
455 system.l2c.overall_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for overall accesses
456 system.l2c.overall_mshr_miss_rate::cpu0.data 0.970588 # mshr miss rate for overall accesses
457 system.l2c.overall_mshr_miss_rate::cpu1.inst 0.161202 # mshr miss rate for overall accesses
458 system.l2c.overall_mshr_miss_rate::cpu1.data 0.846154 # mshr miss rate for overall accesses
459 system.l2c.overall_mshr_miss_rate::cpu2.inst 0.005464 # mshr miss rate for overall accesses
460 system.l2c.overall_mshr_miss_rate::cpu2.data 0.600000 # mshr miss rate for overall accesses
461 system.l2c.overall_mshr_miss_rate::cpu3.inst 0.021798 # mshr miss rate for overall accesses
462 system.l2c.overall_mshr_miss_rate::cpu3.data 0.640000 # mshr miss rate for overall accesses
463 system.l2c.overall_mshr_miss_rate::total 0.315673 # mshr miss rate for overall accesses
464 system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40050.877193 # average ReadReq mshr miss latency
465 system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40000 # average ReadReq mshr miss latency
466 system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40144.067797 # average ReadReq mshr miss latency
467 system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40000 # average ReadReq mshr miss latency
468 system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 40000 # average ReadReq mshr miss latency
469 system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 40000 # average ReadReq mshr miss latency
470 system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 40000 # average ReadReq mshr miss latency
471 system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 40000 # average ReadReq mshr miss latency
472 system.l2c.ReadReq_avg_mshr_miss_latency::total 40053.488372 # average ReadReq mshr miss latency
473 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40000 # average UpgradeReq mshr miss latency
474 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40033.266667 # average UpgradeReq mshr miss latency
475 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 40000 # average UpgradeReq mshr miss latency
476 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 40210.105263 # average UpgradeReq mshr miss latency
477 system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40058.324675 # average UpgradeReq mshr miss latency
478 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40025.252525 # average ReadExReq mshr miss latency
479 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 41133.333333 # average ReadExReq mshr miss latency
480 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 41178.571429 # average ReadExReq mshr miss latency
481 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 40000 # average ReadExReq mshr miss latency
482 system.l2c.ReadExReq_avg_mshr_miss_latency::total 40253.521127 # average ReadExReq mshr miss latency
483 system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40050.877193 # average overall mshr miss latency
484 system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40015.151515 # average overall mshr miss latency
485 system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40144.067797 # average overall mshr miss latency
486 system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40772.727273 # average overall mshr miss latency
487 system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency
488 system.l2c.demand_avg_mshr_miss_latency::cpu2.data 41100 # average overall mshr miss latency
489 system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency
490 system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40000 # average overall mshr miss latency
491 system.l2c.demand_avg_mshr_miss_latency::total 40103.146853 # average overall mshr miss latency
492 system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40050.877193 # average overall mshr miss latency
493 system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40015.151515 # average overall mshr miss latency
494 system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40144.067797 # average overall mshr miss latency
495 system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40772.727273 # average overall mshr miss latency
496 system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency
497 system.l2c.overall_avg_mshr_miss_latency::cpu2.data 41100 # average overall mshr miss latency
498 system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency
499 system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40000 # average overall mshr miss latency
500 system.l2c.overall_avg_mshr_miss_latency::total 40103.146853 # average overall mshr miss latency
501 system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
502 system.toL2Bus.trans_dist::ReadReq 2225 # Transaction distribution
503 system.toL2Bus.trans_dist::ReadResp 2225 # Transaction distribution
504 system.toL2Bus.trans_dist::Writeback 1 # Transaction distribution
505 system.toL2Bus.trans_dist::UpgradeReq 274 # Transaction distribution
506 system.toL2Bus.trans_dist::UpgradeResp 274 # Transaction distribution
507 system.toL2Bus.trans_dist::ReadExReq 429 # Transaction distribution
508 system.toL2Bus.trans_dist::ReadExResp 429 # Transaction distribution
509 system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 934 # Packet count per connected master and slave (bytes)
510 system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 580 # Packet count per connected master and slave (bytes)
511 system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 732 # Packet count per connected master and slave (bytes)
512 system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 355 # Packet count per connected master and slave (bytes)
513 system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 732 # Packet count per connected master and slave (bytes)
514 system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 352 # Packet count per connected master and slave (bytes)
515 system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 734 # Packet count per connected master and slave (bytes)
516 system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 401 # Packet count per connected master and slave (bytes)
517 system.toL2Bus.pkt_count::total 4820 # Packet count per connected master and slave (bytes)
518 system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 29888 # Cumulative packet size per connected master and slave (bytes)
519 system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 10944 # Cumulative packet size per connected master and slave (bytes)
520 system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 23424 # Cumulative packet size per connected master and slave (bytes)
521 system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1664 # Cumulative packet size per connected master and slave (bytes)
522 system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 23424 # Cumulative packet size per connected master and slave (bytes)
523 system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes)
524 system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 23488 # Cumulative packet size per connected master and slave (bytes)
525 system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes)
526 system.toL2Bus.pkt_size::total 116032 # Cumulative packet size per connected master and slave (bytes)
527 system.toL2Bus.snoops 1037 # Total snoops (count)
528 system.toL2Bus.snoop_fanout::samples 2929 # Request fanout histogram
529 system.toL2Bus.snoop_fanout::mean 7 # Request fanout histogram
530 system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
531 system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
532 system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
533 system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
534 system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
535 system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
536 system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
537 system.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram
538 system.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram
539 system.toL2Bus.snoop_fanout::7 2929 100.00% 100.00% # Request fanout histogram
540 system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram
541 system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
542 system.toL2Bus.snoop_fanout::min_value 7 # Request fanout histogram
543 system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram
544 system.toL2Bus.snoop_fanout::total 2929 # Request fanout histogram
545 system.toL2Bus.reqLayer0.occupancy 1473490 # Layer occupancy (ticks)
546 system.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%)
547 system.toL2Bus.respLayer0.occupancy 2101500 # Layer occupancy (ticks)
548 system.toL2Bus.respLayer0.utilization 0.8 # Layer utilization (%)
549 system.toL2Bus.respLayer1.occupancy 1430481 # Layer occupancy (ticks)
550 system.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%)
551 system.toL2Bus.respLayer2.occupancy 1650488 # Layer occupancy (ticks)
552 system.toL2Bus.respLayer2.utilization 0.6 # Layer utilization (%)
553 system.toL2Bus.respLayer3.occupancy 1157483 # Layer occupancy (ticks)
554 system.toL2Bus.respLayer3.utilization 0.4 # Layer utilization (%)
555 system.toL2Bus.respLayer4.occupancy 1651988 # Layer occupancy (ticks)
556 system.toL2Bus.respLayer4.utilization 0.6 # Layer utilization (%)
557 system.toL2Bus.respLayer5.occupancy 1147981 # Layer occupancy (ticks)
558 system.toL2Bus.respLayer5.utilization 0.4 # Layer utilization (%)
559 system.toL2Bus.respLayer6.occupancy 1651999 # Layer occupancy (ticks)
560 system.toL2Bus.respLayer6.utilization 0.6 # Layer utilization (%)
561 system.toL2Bus.respLayer7.occupancy 1327473 # Layer occupancy (ticks)
562 system.toL2Bus.respLayer7.utilization 0.5 # Layer utilization (%)
563 system.cpu0.workload.num_syscalls 89 # Number of system calls
564 system.cpu0.numCycles 525587 # number of cpu cycles simulated
565 system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
566 system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
567 system.cpu0.committedInsts 158574 # Number of instructions committed
568 system.cpu0.committedOps 158574 # Number of ops (including micro ops) committed
569 system.cpu0.num_int_alu_accesses 109208 # Number of integer alu accesses
570 system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses
571 system.cpu0.num_func_calls 390 # number of times a function call or return occured
572 system.cpu0.num_conditional_control_insts 26032 # number of instructions that are conditional controls
573 system.cpu0.num_int_insts 109208 # number of integer instructions
574 system.cpu0.num_fp_insts 0 # number of float instructions
575 system.cpu0.num_int_register_reads 315782 # number of times the integer registers were read
576 system.cpu0.num_int_register_writes 110814 # number of times the integer registers were written
577 system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read
578 system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written
579 system.cpu0.num_mem_refs 74021 # number of memory refs
580 system.cpu0.num_load_insts 49007 # Number of load instructions
581 system.cpu0.num_store_insts 25014 # Number of store instructions
582 system.cpu0.num_idle_cycles 0 # Number of idle cycles
583 system.cpu0.num_busy_cycles 525587 # Number of busy cycles
584 system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles
585 system.cpu0.idle_fraction 0 # Percentage of idle cycles
586 system.cpu0.Branches 26897 # Number of branches fetched
587 system.cpu0.op_class::No_OpClass 23624 14.89% 14.89% # Class of executed instruction
588 system.cpu0.op_class::IntAlu 60907 38.39% 53.29% # Class of executed instruction
589 system.cpu0.op_class::IntMult 0 0.00% 53.29% # Class of executed instruction
590 system.cpu0.op_class::IntDiv 0 0.00% 53.29% # Class of executed instruction
591 system.cpu0.op_class::FloatAdd 0 0.00% 53.29% # Class of executed instruction
592 system.cpu0.op_class::FloatCmp 0 0.00% 53.29% # Class of executed instruction
593 system.cpu0.op_class::FloatCvt 0 0.00% 53.29% # Class of executed instruction
594 system.cpu0.op_class::FloatMult 0 0.00% 53.29% # Class of executed instruction
595 system.cpu0.op_class::FloatDiv 0 0.00% 53.29% # Class of executed instruction
596 system.cpu0.op_class::FloatSqrt 0 0.00% 53.29% # Class of executed instruction
597 system.cpu0.op_class::SimdAdd 0 0.00% 53.29% # Class of executed instruction
598 system.cpu0.op_class::SimdAddAcc 0 0.00% 53.29% # Class of executed instruction
599 system.cpu0.op_class::SimdAlu 0 0.00% 53.29% # Class of executed instruction
600 system.cpu0.op_class::SimdCmp 0 0.00% 53.29% # Class of executed instruction
601 system.cpu0.op_class::SimdCvt 0 0.00% 53.29% # Class of executed instruction
602 system.cpu0.op_class::SimdMisc 0 0.00% 53.29% # Class of executed instruction
603 system.cpu0.op_class::SimdMult 0 0.00% 53.29% # Class of executed instruction
604 system.cpu0.op_class::SimdMultAcc 0 0.00% 53.29% # Class of executed instruction
605 system.cpu0.op_class::SimdShift 0 0.00% 53.29% # Class of executed instruction
606 system.cpu0.op_class::SimdShiftAcc 0 0.00% 53.29% # Class of executed instruction
607 system.cpu0.op_class::SimdSqrt 0 0.00% 53.29% # Class of executed instruction
608 system.cpu0.op_class::SimdFloatAdd 0 0.00% 53.29% # Class of executed instruction
609 system.cpu0.op_class::SimdFloatAlu 0 0.00% 53.29% # Class of executed instruction
610 system.cpu0.op_class::SimdFloatCmp 0 0.00% 53.29% # Class of executed instruction
611 system.cpu0.op_class::SimdFloatCvt 0 0.00% 53.29% # Class of executed instruction
612 system.cpu0.op_class::SimdFloatDiv 0 0.00% 53.29% # Class of executed instruction
613 system.cpu0.op_class::SimdFloatMisc 0 0.00% 53.29% # Class of executed instruction
614 system.cpu0.op_class::SimdFloatMult 0 0.00% 53.29% # Class of executed instruction
615 system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 53.29% # Class of executed instruction
616 system.cpu0.op_class::SimdFloatSqrt 0 0.00% 53.29% # Class of executed instruction
617 system.cpu0.op_class::MemRead 49091 30.95% 84.23% # Class of executed instruction
618 system.cpu0.op_class::MemWrite 25014 15.77% 100.00% # Class of executed instruction
619 system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
620 system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
621 system.cpu0.op_class::total 158636 # Class of executed instruction
622 system.cpu0.icache.tags.replacements 215 # number of replacements
623 system.cpu0.icache.tags.tagsinuse 212.401858 # Cycle average of tags in use
624 system.cpu0.icache.tags.total_refs 158170 # Total number of references to valid blocks.
625 system.cpu0.icache.tags.sampled_refs 467 # Sample count of references to valid blocks.
626 system.cpu0.icache.tags.avg_refs 338.693790 # Average number of references to valid blocks.
627 system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
628 system.cpu0.icache.tags.occ_blocks::cpu0.inst 212.401858 # Average occupied blocks per requestor
629 system.cpu0.icache.tags.occ_percent::cpu0.inst 0.414847 # Average percentage of cache occupancy
630 system.cpu0.icache.tags.occ_percent::total 0.414847 # Average percentage of cache occupancy
631 system.cpu0.icache.tags.occ_task_id_blocks::1024 252 # Occupied blocks per task id
632 system.cpu0.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id
633 system.cpu0.icache.tags.age_task_id_blocks_1024::2 199 # Occupied blocks per task id
634 system.cpu0.icache.tags.occ_task_id_percent::1024 0.492188 # Percentage of cache occupancy per task id
635 system.cpu0.icache.tags.tag_accesses 159104 # Number of tag accesses
636 system.cpu0.icache.tags.data_accesses 159104 # Number of data accesses
637 system.cpu0.icache.ReadReq_hits::cpu0.inst 158170 # number of ReadReq hits
638 system.cpu0.icache.ReadReq_hits::total 158170 # number of ReadReq hits
639 system.cpu0.icache.demand_hits::cpu0.inst 158170 # number of demand (read+write) hits
640 system.cpu0.icache.demand_hits::total 158170 # number of demand (read+write) hits
641 system.cpu0.icache.overall_hits::cpu0.inst 158170 # number of overall hits
642 system.cpu0.icache.overall_hits::total 158170 # number of overall hits
643 system.cpu0.icache.ReadReq_misses::cpu0.inst 467 # number of ReadReq misses
644 system.cpu0.icache.ReadReq_misses::total 467 # number of ReadReq misses
645 system.cpu0.icache.demand_misses::cpu0.inst 467 # number of demand (read+write) misses
646 system.cpu0.icache.demand_misses::total 467 # number of demand (read+write) misses
647 system.cpu0.icache.overall_misses::cpu0.inst 467 # number of overall misses
648 system.cpu0.icache.overall_misses::total 467 # number of overall misses
649 system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 18148000 # number of ReadReq miss cycles
650 system.cpu0.icache.ReadReq_miss_latency::total 18148000 # number of ReadReq miss cycles
651 system.cpu0.icache.demand_miss_latency::cpu0.inst 18148000 # number of demand (read+write) miss cycles
652 system.cpu0.icache.demand_miss_latency::total 18148000 # number of demand (read+write) miss cycles
653 system.cpu0.icache.overall_miss_latency::cpu0.inst 18148000 # number of overall miss cycles
654 system.cpu0.icache.overall_miss_latency::total 18148000 # number of overall miss cycles
655 system.cpu0.icache.ReadReq_accesses::cpu0.inst 158637 # number of ReadReq accesses(hits+misses)
656 system.cpu0.icache.ReadReq_accesses::total 158637 # number of ReadReq accesses(hits+misses)
657 system.cpu0.icache.demand_accesses::cpu0.inst 158637 # number of demand (read+write) accesses
658 system.cpu0.icache.demand_accesses::total 158637 # number of demand (read+write) accesses
659 system.cpu0.icache.overall_accesses::cpu0.inst 158637 # number of overall (read+write) accesses
660 system.cpu0.icache.overall_accesses::total 158637 # number of overall (read+write) accesses
661 system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002944 # miss rate for ReadReq accesses
662 system.cpu0.icache.ReadReq_miss_rate::total 0.002944 # miss rate for ReadReq accesses
663 system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002944 # miss rate for demand accesses
664 system.cpu0.icache.demand_miss_rate::total 0.002944 # miss rate for demand accesses
665 system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002944 # miss rate for overall accesses
666 system.cpu0.icache.overall_miss_rate::total 0.002944 # miss rate for overall accesses
667 system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 38860.813704 # average ReadReq miss latency
668 system.cpu0.icache.ReadReq_avg_miss_latency::total 38860.813704 # average ReadReq miss latency
669 system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 38860.813704 # average overall miss latency
670 system.cpu0.icache.demand_avg_miss_latency::total 38860.813704 # average overall miss latency
671 system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 38860.813704 # average overall miss latency
672 system.cpu0.icache.overall_avg_miss_latency::total 38860.813704 # average overall miss latency
673 system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
674 system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
675 system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
676 system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
677 system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
678 system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
679 system.cpu0.icache.fast_writes 0 # number of fast writes performed
680 system.cpu0.icache.cache_copies 0 # number of cache copies performed
681 system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 467 # number of ReadReq MSHR misses
682 system.cpu0.icache.ReadReq_mshr_misses::total 467 # number of ReadReq MSHR misses
683 system.cpu0.icache.demand_mshr_misses::cpu0.inst 467 # number of demand (read+write) MSHR misses
684 system.cpu0.icache.demand_mshr_misses::total 467 # number of demand (read+write) MSHR misses
685 system.cpu0.icache.overall_mshr_misses::cpu0.inst 467 # number of overall MSHR misses
686 system.cpu0.icache.overall_mshr_misses::total 467 # number of overall MSHR misses
687 system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 17214000 # number of ReadReq MSHR miss cycles
688 system.cpu0.icache.ReadReq_mshr_miss_latency::total 17214000 # number of ReadReq MSHR miss cycles
689 system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 17214000 # number of demand (read+write) MSHR miss cycles
690 system.cpu0.icache.demand_mshr_miss_latency::total 17214000 # number of demand (read+write) MSHR miss cycles
691 system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 17214000 # number of overall MSHR miss cycles
692 system.cpu0.icache.overall_mshr_miss_latency::total 17214000 # number of overall MSHR miss cycles
693 system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.002944 # mshr miss rate for ReadReq accesses
694 system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.002944 # mshr miss rate for ReadReq accesses
695 system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.002944 # mshr miss rate for demand accesses
696 system.cpu0.icache.demand_mshr_miss_rate::total 0.002944 # mshr miss rate for demand accesses
697 system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.002944 # mshr miss rate for overall accesses
698 system.cpu0.icache.overall_mshr_miss_rate::total 0.002944 # mshr miss rate for overall accesses
699 system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36860.813704 # average ReadReq mshr miss latency
700 system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 36860.813704 # average ReadReq mshr miss latency
701 system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 36860.813704 # average overall mshr miss latency
702 system.cpu0.icache.demand_avg_mshr_miss_latency::total 36860.813704 # average overall mshr miss latency
703 system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 36860.813704 # average overall mshr miss latency
704 system.cpu0.icache.overall_avg_mshr_miss_latency::total 36860.813704 # average overall mshr miss latency
705 system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
706 system.cpu0.dcache.tags.replacements 2 # number of replacements
707 system.cpu0.dcache.tags.tagsinuse 145.571907 # Cycle average of tags in use
708 system.cpu0.dcache.tags.total_refs 73489 # Total number of references to valid blocks.
709 system.cpu0.dcache.tags.sampled_refs 167 # Sample count of references to valid blocks.
710 system.cpu0.dcache.tags.avg_refs 440.053892 # Average number of references to valid blocks.
711 system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
712 system.cpu0.dcache.tags.occ_blocks::cpu0.data 145.571907 # Average occupied blocks per requestor
713 system.cpu0.dcache.tags.occ_percent::cpu0.data 0.284320 # Average percentage of cache occupancy
714 system.cpu0.dcache.tags.occ_percent::total 0.284320 # Average percentage of cache occupancy
715 system.cpu0.dcache.tags.occ_task_id_blocks::1024 165 # Occupied blocks per task id
716 system.cpu0.dcache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id
717 system.cpu0.dcache.tags.age_task_id_blocks_1024::2 149 # Occupied blocks per task id
718 system.cpu0.dcache.tags.occ_task_id_percent::1024 0.322266 # Percentage of cache occupancy per task id
719 system.cpu0.dcache.tags.tag_accesses 296317 # Number of tag accesses
720 system.cpu0.dcache.tags.data_accesses 296317 # Number of data accesses
721 system.cpu0.dcache.ReadReq_hits::cpu0.data 48827 # number of ReadReq hits
722 system.cpu0.dcache.ReadReq_hits::total 48827 # number of ReadReq hits
723 system.cpu0.dcache.WriteReq_hits::cpu0.data 24780 # number of WriteReq hits
724 system.cpu0.dcache.WriteReq_hits::total 24780 # number of WriteReq hits
725 system.cpu0.dcache.SwapReq_hits::cpu0.data 16 # number of SwapReq hits
726 system.cpu0.dcache.SwapReq_hits::total 16 # number of SwapReq hits
727 system.cpu0.dcache.demand_hits::cpu0.data 73607 # number of demand (read+write) hits
728 system.cpu0.dcache.demand_hits::total 73607 # number of demand (read+write) hits
729 system.cpu0.dcache.overall_hits::cpu0.data 73607 # number of overall hits
730 system.cpu0.dcache.overall_hits::total 73607 # number of overall hits
731 system.cpu0.dcache.ReadReq_misses::cpu0.data 170 # number of ReadReq misses
732 system.cpu0.dcache.ReadReq_misses::total 170 # number of ReadReq misses
733 system.cpu0.dcache.WriteReq_misses::cpu0.data 183 # number of WriteReq misses
734 system.cpu0.dcache.WriteReq_misses::total 183 # number of WriteReq misses
735 system.cpu0.dcache.SwapReq_misses::cpu0.data 26 # number of SwapReq misses
736 system.cpu0.dcache.SwapReq_misses::total 26 # number of SwapReq misses
737 system.cpu0.dcache.demand_misses::cpu0.data 353 # number of demand (read+write) misses
738 system.cpu0.dcache.demand_misses::total 353 # number of demand (read+write) misses
739 system.cpu0.dcache.overall_misses::cpu0.data 353 # number of overall misses
740 system.cpu0.dcache.overall_misses::total 353 # number of overall misses
741 system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4586981 # number of ReadReq miss cycles
742 system.cpu0.dcache.ReadReq_miss_latency::total 4586981 # number of ReadReq miss cycles
743 system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 6973000 # number of WriteReq miss cycles
744 system.cpu0.dcache.WriteReq_miss_latency::total 6973000 # number of WriteReq miss cycles
745 system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 360500 # number of SwapReq miss cycles
746 system.cpu0.dcache.SwapReq_miss_latency::total 360500 # number of SwapReq miss cycles
747 system.cpu0.dcache.demand_miss_latency::cpu0.data 11559981 # number of demand (read+write) miss cycles
748 system.cpu0.dcache.demand_miss_latency::total 11559981 # number of demand (read+write) miss cycles
749 system.cpu0.dcache.overall_miss_latency::cpu0.data 11559981 # number of overall miss cycles
750 system.cpu0.dcache.overall_miss_latency::total 11559981 # number of overall miss cycles
751 system.cpu0.dcache.ReadReq_accesses::cpu0.data 48997 # number of ReadReq accesses(hits+misses)
752 system.cpu0.dcache.ReadReq_accesses::total 48997 # number of ReadReq accesses(hits+misses)
753 system.cpu0.dcache.WriteReq_accesses::cpu0.data 24963 # number of WriteReq accesses(hits+misses)
754 system.cpu0.dcache.WriteReq_accesses::total 24963 # number of WriteReq accesses(hits+misses)
755 system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses)
756 system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses)
757 system.cpu0.dcache.demand_accesses::cpu0.data 73960 # number of demand (read+write) accesses
758 system.cpu0.dcache.demand_accesses::total 73960 # number of demand (read+write) accesses
759 system.cpu0.dcache.overall_accesses::cpu0.data 73960 # number of overall (read+write) accesses
760 system.cpu0.dcache.overall_accesses::total 73960 # number of overall (read+write) accesses
761 system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.003470 # miss rate for ReadReq accesses
762 system.cpu0.dcache.ReadReq_miss_rate::total 0.003470 # miss rate for ReadReq accesses
763 system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007331 # miss rate for WriteReq accesses
764 system.cpu0.dcache.WriteReq_miss_rate::total 0.007331 # miss rate for WriteReq accesses
765 system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.619048 # miss rate for SwapReq accesses
766 system.cpu0.dcache.SwapReq_miss_rate::total 0.619048 # miss rate for SwapReq accesses
767 system.cpu0.dcache.demand_miss_rate::cpu0.data 0.004773 # miss rate for demand accesses
768 system.cpu0.dcache.demand_miss_rate::total 0.004773 # miss rate for demand accesses
769 system.cpu0.dcache.overall_miss_rate::cpu0.data 0.004773 # miss rate for overall accesses
770 system.cpu0.dcache.overall_miss_rate::total 0.004773 # miss rate for overall accesses
771 system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 26982.241176 # average ReadReq miss latency
772 system.cpu0.dcache.ReadReq_avg_miss_latency::total 26982.241176 # average ReadReq miss latency
773 system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38103.825137 # average WriteReq miss latency
774 system.cpu0.dcache.WriteReq_avg_miss_latency::total 38103.825137 # average WriteReq miss latency
775 system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 13865.384615 # average SwapReq miss latency
776 system.cpu0.dcache.SwapReq_avg_miss_latency::total 13865.384615 # average SwapReq miss latency
777 system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 32747.821530 # average overall miss latency
778 system.cpu0.dcache.demand_avg_miss_latency::total 32747.821530 # average overall miss latency
779 system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 32747.821530 # average overall miss latency
780 system.cpu0.dcache.overall_avg_miss_latency::total 32747.821530 # average overall miss latency
781 system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
782 system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
783 system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
784 system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
785 system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
786 system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
787 system.cpu0.dcache.fast_writes 0 # number of fast writes performed
788 system.cpu0.dcache.cache_copies 0 # number of cache copies performed
789 system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks
790 system.cpu0.dcache.writebacks::total 1 # number of writebacks
791 system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 170 # number of ReadReq MSHR misses
792 system.cpu0.dcache.ReadReq_mshr_misses::total 170 # number of ReadReq MSHR misses
793 system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 183 # number of WriteReq MSHR misses
794 system.cpu0.dcache.WriteReq_mshr_misses::total 183 # number of WriteReq MSHR misses
795 system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 26 # number of SwapReq MSHR misses
796 system.cpu0.dcache.SwapReq_mshr_misses::total 26 # number of SwapReq MSHR misses
797 system.cpu0.dcache.demand_mshr_misses::cpu0.data 353 # number of demand (read+write) MSHR misses
798 system.cpu0.dcache.demand_mshr_misses::total 353 # number of demand (read+write) MSHR misses
799 system.cpu0.dcache.overall_mshr_misses::cpu0.data 353 # number of overall MSHR misses
800 system.cpu0.dcache.overall_mshr_misses::total 353 # number of overall MSHR misses
801 system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4237019 # number of ReadReq MSHR miss cycles
802 system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4237019 # number of ReadReq MSHR miss cycles
803 system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6607000 # number of WriteReq MSHR miss cycles
804 system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6607000 # number of WriteReq MSHR miss cycles
805 system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 308500 # number of SwapReq MSHR miss cycles
806 system.cpu0.dcache.SwapReq_mshr_miss_latency::total 308500 # number of SwapReq MSHR miss cycles
807 system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10844019 # number of demand (read+write) MSHR miss cycles
808 system.cpu0.dcache.demand_mshr_miss_latency::total 10844019 # number of demand (read+write) MSHR miss cycles
809 system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10844019 # number of overall MSHR miss cycles
810 system.cpu0.dcache.overall_mshr_miss_latency::total 10844019 # number of overall MSHR miss cycles
811 system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.003470 # mshr miss rate for ReadReq accesses
812 system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.003470 # mshr miss rate for ReadReq accesses
813 system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.007331 # mshr miss rate for WriteReq accesses
814 system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007331 # mshr miss rate for WriteReq accesses
815 system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.619048 # mshr miss rate for SwapReq accesses
816 system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.619048 # mshr miss rate for SwapReq accesses
817 system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.004773 # mshr miss rate for demand accesses
818 system.cpu0.dcache.demand_mshr_miss_rate::total 0.004773 # mshr miss rate for demand accesses
819 system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.004773 # mshr miss rate for overall accesses
820 system.cpu0.dcache.overall_mshr_miss_rate::total 0.004773 # mshr miss rate for overall accesses
821 system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 24923.641176 # average ReadReq mshr miss latency
822 system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 24923.641176 # average ReadReq mshr miss latency
823 system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36103.825137 # average WriteReq mshr miss latency
824 system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36103.825137 # average WriteReq mshr miss latency
825 system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 11865.384615 # average SwapReq mshr miss latency
826 system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 11865.384615 # average SwapReq mshr miss latency
827 system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 30719.600567 # average overall mshr miss latency
828 system.cpu0.dcache.demand_avg_mshr_miss_latency::total 30719.600567 # average overall mshr miss latency
829 system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 30719.600567 # average overall mshr miss latency
830 system.cpu0.dcache.overall_avg_mshr_miss_latency::total 30719.600567 # average overall mshr miss latency
831 system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
832 system.cpu1.numCycles 525586 # number of cpu cycles simulated
833 system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
834 system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
835 system.cpu1.committedInsts 163471 # Number of instructions committed
836 system.cpu1.committedOps 163471 # Number of ops (including micro ops) committed
837 system.cpu1.num_int_alu_accesses 111731 # Number of integer alu accesses
838 system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses
839 system.cpu1.num_func_calls 637 # number of times a function call or return occured
840 system.cpu1.num_conditional_control_insts 29880 # number of instructions that are conditional controls
841 system.cpu1.num_int_insts 111731 # number of integer instructions
842 system.cpu1.num_fp_insts 0 # number of float instructions
843 system.cpu1.num_int_register_reads 289610 # number of times the integer registers were read
844 system.cpu1.num_int_register_writes 111151 # number of times the integer registers were written
845 system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read
846 system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written
847 system.cpu1.num_mem_refs 58020 # number of memory refs
848 system.cpu1.num_load_insts 41540 # Number of load instructions
849 system.cpu1.num_store_insts 16480 # Number of store instructions
850 system.cpu1.num_idle_cycles 69346.869794 # Number of idle cycles
851 system.cpu1.num_busy_cycles 456239.130206 # Number of busy cycles
852 system.cpu1.not_idle_fraction 0.868058 # Percentage of non-idle cycles
853 system.cpu1.idle_fraction 0.131942 # Percentage of idle cycles
854 system.cpu1.Branches 31528 # Number of branches fetched
855 system.cpu1.op_class::No_OpClass 22316 13.65% 13.65% # Class of executed instruction
856 system.cpu1.op_class::IntAlu 75095 45.93% 59.58% # Class of executed instruction
857 system.cpu1.op_class::IntMult 0 0.00% 59.58% # Class of executed instruction
858 system.cpu1.op_class::IntDiv 0 0.00% 59.58% # Class of executed instruction
859 system.cpu1.op_class::FloatAdd 0 0.00% 59.58% # Class of executed instruction
860 system.cpu1.op_class::FloatCmp 0 0.00% 59.58% # Class of executed instruction
861 system.cpu1.op_class::FloatCvt 0 0.00% 59.58% # Class of executed instruction
862 system.cpu1.op_class::FloatMult 0 0.00% 59.58% # Class of executed instruction
863 system.cpu1.op_class::FloatDiv 0 0.00% 59.58% # Class of executed instruction
864 system.cpu1.op_class::FloatSqrt 0 0.00% 59.58% # Class of executed instruction
865 system.cpu1.op_class::SimdAdd 0 0.00% 59.58% # Class of executed instruction
866 system.cpu1.op_class::SimdAddAcc 0 0.00% 59.58% # Class of executed instruction
867 system.cpu1.op_class::SimdAlu 0 0.00% 59.58% # Class of executed instruction
868 system.cpu1.op_class::SimdCmp 0 0.00% 59.58% # Class of executed instruction
869 system.cpu1.op_class::SimdCvt 0 0.00% 59.58% # Class of executed instruction
870 system.cpu1.op_class::SimdMisc 0 0.00% 59.58% # Class of executed instruction
871 system.cpu1.op_class::SimdMult 0 0.00% 59.58% # Class of executed instruction
872 system.cpu1.op_class::SimdMultAcc 0 0.00% 59.58% # Class of executed instruction
873 system.cpu1.op_class::SimdShift 0 0.00% 59.58% # Class of executed instruction
874 system.cpu1.op_class::SimdShiftAcc 0 0.00% 59.58% # Class of executed instruction
875 system.cpu1.op_class::SimdSqrt 0 0.00% 59.58% # Class of executed instruction
876 system.cpu1.op_class::SimdFloatAdd 0 0.00% 59.58% # Class of executed instruction
877 system.cpu1.op_class::SimdFloatAlu 0 0.00% 59.58% # Class of executed instruction
878 system.cpu1.op_class::SimdFloatCmp 0 0.00% 59.58% # Class of executed instruction
879 system.cpu1.op_class::SimdFloatCvt 0 0.00% 59.58% # Class of executed instruction
880 system.cpu1.op_class::SimdFloatDiv 0 0.00% 59.58% # Class of executed instruction
881 system.cpu1.op_class::SimdFloatMisc 0 0.00% 59.58% # Class of executed instruction
882 system.cpu1.op_class::SimdFloatMult 0 0.00% 59.58% # Class of executed instruction
883 system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 59.58% # Class of executed instruction
884 system.cpu1.op_class::SimdFloatSqrt 0 0.00% 59.58% # Class of executed instruction
885 system.cpu1.op_class::MemRead 49612 30.34% 89.92% # Class of executed instruction
886 system.cpu1.op_class::MemWrite 16480 10.08% 100.00% # Class of executed instruction
887 system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
888 system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
889 system.cpu1.op_class::total 163503 # Class of executed instruction
890 system.cpu1.icache.tags.replacements 280 # number of replacements
891 system.cpu1.icache.tags.tagsinuse 70.017769 # Cycle average of tags in use
892 system.cpu1.icache.tags.total_refs 163138 # Total number of references to valid blocks.
893 system.cpu1.icache.tags.sampled_refs 366 # Sample count of references to valid blocks.
894 system.cpu1.icache.tags.avg_refs 445.732240 # Average number of references to valid blocks.
895 system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
896 system.cpu1.icache.tags.occ_blocks::cpu1.inst 70.017769 # Average occupied blocks per requestor
897 system.cpu1.icache.tags.occ_percent::cpu1.inst 0.136753 # Average percentage of cache occupancy
898 system.cpu1.icache.tags.occ_percent::total 0.136753 # Average percentage of cache occupancy
899 system.cpu1.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id
900 system.cpu1.icache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id
901 system.cpu1.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id
902 system.cpu1.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id
903 system.cpu1.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id
904 system.cpu1.icache.tags.tag_accesses 163870 # Number of tag accesses
905 system.cpu1.icache.tags.data_accesses 163870 # Number of data accesses
906 system.cpu1.icache.ReadReq_hits::cpu1.inst 163138 # number of ReadReq hits
907 system.cpu1.icache.ReadReq_hits::total 163138 # number of ReadReq hits
908 system.cpu1.icache.demand_hits::cpu1.inst 163138 # number of demand (read+write) hits
909 system.cpu1.icache.demand_hits::total 163138 # number of demand (read+write) hits
910 system.cpu1.icache.overall_hits::cpu1.inst 163138 # number of overall hits
911 system.cpu1.icache.overall_hits::total 163138 # number of overall hits
912 system.cpu1.icache.ReadReq_misses::cpu1.inst 366 # number of ReadReq misses
913 system.cpu1.icache.ReadReq_misses::total 366 # number of ReadReq misses
914 system.cpu1.icache.demand_misses::cpu1.inst 366 # number of demand (read+write) misses
915 system.cpu1.icache.demand_misses::total 366 # number of demand (read+write) misses
916 system.cpu1.icache.overall_misses::cpu1.inst 366 # number of overall misses
917 system.cpu1.icache.overall_misses::total 366 # number of overall misses
918 system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7544488 # number of ReadReq miss cycles
919 system.cpu1.icache.ReadReq_miss_latency::total 7544488 # number of ReadReq miss cycles
920 system.cpu1.icache.demand_miss_latency::cpu1.inst 7544488 # number of demand (read+write) miss cycles
921 system.cpu1.icache.demand_miss_latency::total 7544488 # number of demand (read+write) miss cycles
922 system.cpu1.icache.overall_miss_latency::cpu1.inst 7544488 # number of overall miss cycles
923 system.cpu1.icache.overall_miss_latency::total 7544488 # number of overall miss cycles
924 system.cpu1.icache.ReadReq_accesses::cpu1.inst 163504 # number of ReadReq accesses(hits+misses)
925 system.cpu1.icache.ReadReq_accesses::total 163504 # number of ReadReq accesses(hits+misses)
926 system.cpu1.icache.demand_accesses::cpu1.inst 163504 # number of demand (read+write) accesses
927 system.cpu1.icache.demand_accesses::total 163504 # number of demand (read+write) accesses
928 system.cpu1.icache.overall_accesses::cpu1.inst 163504 # number of overall (read+write) accesses
929 system.cpu1.icache.overall_accesses::total 163504 # number of overall (read+write) accesses
930 system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002238 # miss rate for ReadReq accesses
931 system.cpu1.icache.ReadReq_miss_rate::total 0.002238 # miss rate for ReadReq accesses
932 system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002238 # miss rate for demand accesses
933 system.cpu1.icache.demand_miss_rate::total 0.002238 # miss rate for demand accesses
934 system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002238 # miss rate for overall accesses
935 system.cpu1.icache.overall_miss_rate::total 0.002238 # miss rate for overall accesses
936 system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 20613.355191 # average ReadReq miss latency
937 system.cpu1.icache.ReadReq_avg_miss_latency::total 20613.355191 # average ReadReq miss latency
938 system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 20613.355191 # average overall miss latency
939 system.cpu1.icache.demand_avg_miss_latency::total 20613.355191 # average overall miss latency
940 system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 20613.355191 # average overall miss latency
941 system.cpu1.icache.overall_avg_miss_latency::total 20613.355191 # average overall miss latency
942 system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
943 system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
944 system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
945 system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
946 system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
947 system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
948 system.cpu1.icache.fast_writes 0 # number of fast writes performed
949 system.cpu1.icache.cache_copies 0 # number of cache copies performed
950 system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 366 # number of ReadReq MSHR misses
951 system.cpu1.icache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses
952 system.cpu1.icache.demand_mshr_misses::cpu1.inst 366 # number of demand (read+write) MSHR misses
953 system.cpu1.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses
954 system.cpu1.icache.overall_mshr_misses::cpu1.inst 366 # number of overall MSHR misses
955 system.cpu1.icache.overall_mshr_misses::total 366 # number of overall MSHR misses
956 system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6805512 # number of ReadReq MSHR miss cycles
957 system.cpu1.icache.ReadReq_mshr_miss_latency::total 6805512 # number of ReadReq MSHR miss cycles
958 system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6805512 # number of demand (read+write) MSHR miss cycles
959 system.cpu1.icache.demand_mshr_miss_latency::total 6805512 # number of demand (read+write) MSHR miss cycles
960 system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6805512 # number of overall MSHR miss cycles
961 system.cpu1.icache.overall_mshr_miss_latency::total 6805512 # number of overall MSHR miss cycles
962 system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.002238 # mshr miss rate for ReadReq accesses
963 system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.002238 # mshr miss rate for ReadReq accesses
964 system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.002238 # mshr miss rate for demand accesses
965 system.cpu1.icache.demand_mshr_miss_rate::total 0.002238 # mshr miss rate for demand accesses
966 system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.002238 # mshr miss rate for overall accesses
967 system.cpu1.icache.overall_mshr_miss_rate::total 0.002238 # mshr miss rate for overall accesses
968 system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 18594.295082 # average ReadReq mshr miss latency
969 system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 18594.295082 # average ReadReq mshr miss latency
970 system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 18594.295082 # average overall mshr miss latency
971 system.cpu1.icache.demand_avg_mshr_miss_latency::total 18594.295082 # average overall mshr miss latency
972 system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 18594.295082 # average overall mshr miss latency
973 system.cpu1.icache.overall_avg_mshr_miss_latency::total 18594.295082 # average overall mshr miss latency
974 system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
975 system.cpu1.dcache.tags.replacements 0 # number of replacements
976 system.cpu1.dcache.tags.tagsinuse 27.720301 # Cycle average of tags in use
977 system.cpu1.dcache.tags.total_refs 35348 # Total number of references to valid blocks.
978 system.cpu1.dcache.tags.sampled_refs 30 # Sample count of references to valid blocks.
979 system.cpu1.dcache.tags.avg_refs 1178.266667 # Average number of references to valid blocks.
980 system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
981 system.cpu1.dcache.tags.occ_blocks::cpu1.data 27.720301 # Average occupied blocks per requestor
982 system.cpu1.dcache.tags.occ_percent::cpu1.data 0.054141 # Average percentage of cache occupancy
983 system.cpu1.dcache.tags.occ_percent::total 0.054141 # Average percentage of cache occupancy
984 system.cpu1.dcache.tags.occ_task_id_blocks::1024 30 # Occupied blocks per task id
985 system.cpu1.dcache.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id
986 system.cpu1.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id
987 system.cpu1.dcache.tags.occ_task_id_percent::1024 0.058594 # Percentage of cache occupancy per task id
988 system.cpu1.dcache.tags.tag_accesses 232288 # Number of tag accesses
989 system.cpu1.dcache.tags.data_accesses 232288 # Number of data accesses
990 system.cpu1.dcache.ReadReq_hits::cpu1.data 41378 # number of ReadReq hits
991 system.cpu1.dcache.ReadReq_hits::total 41378 # number of ReadReq hits
992 system.cpu1.dcache.WriteReq_hits::cpu1.data 16307 # number of WriteReq hits
993 system.cpu1.dcache.WriteReq_hits::total 16307 # number of WriteReq hits
994 system.cpu1.dcache.SwapReq_hits::cpu1.data 11 # number of SwapReq hits
995 system.cpu1.dcache.SwapReq_hits::total 11 # number of SwapReq hits
996 system.cpu1.dcache.demand_hits::cpu1.data 57685 # number of demand (read+write) hits
997 system.cpu1.dcache.demand_hits::total 57685 # number of demand (read+write) hits
998 system.cpu1.dcache.overall_hits::cpu1.data 57685 # number of overall hits
999 system.cpu1.dcache.overall_hits::total 57685 # number of overall hits
1000 system.cpu1.dcache.ReadReq_misses::cpu1.data 154 # number of ReadReq misses
1001 system.cpu1.dcache.ReadReq_misses::total 154 # number of ReadReq misses
1002 system.cpu1.dcache.WriteReq_misses::cpu1.data 109 # number of WriteReq misses
1003 system.cpu1.dcache.WriteReq_misses::total 109 # number of WriteReq misses
1004 system.cpu1.dcache.SwapReq_misses::cpu1.data 51 # number of SwapReq misses
1005 system.cpu1.dcache.SwapReq_misses::total 51 # number of SwapReq misses
1006 system.cpu1.dcache.demand_misses::cpu1.data 263 # number of demand (read+write) misses
1007 system.cpu1.dcache.demand_misses::total 263 # number of demand (read+write) misses
1008 system.cpu1.dcache.overall_misses::cpu1.data 263 # number of overall misses
1009 system.cpu1.dcache.overall_misses::total 263 # number of overall misses
1010 system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2494983 # number of ReadReq miss cycles
1011 system.cpu1.dcache.ReadReq_miss_latency::total 2494983 # number of ReadReq miss cycles
1012 system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1979500 # number of WriteReq miss cycles
1013 system.cpu1.dcache.WriteReq_miss_latency::total 1979500 # number of WriteReq miss cycles
1014 system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 209500 # number of SwapReq miss cycles
1015 system.cpu1.dcache.SwapReq_miss_latency::total 209500 # number of SwapReq miss cycles
1016 system.cpu1.dcache.demand_miss_latency::cpu1.data 4474483 # number of demand (read+write) miss cycles
1017 system.cpu1.dcache.demand_miss_latency::total 4474483 # number of demand (read+write) miss cycles
1018 system.cpu1.dcache.overall_miss_latency::cpu1.data 4474483 # number of overall miss cycles
1019 system.cpu1.dcache.overall_miss_latency::total 4474483 # number of overall miss cycles
1020 system.cpu1.dcache.ReadReq_accesses::cpu1.data 41532 # number of ReadReq accesses(hits+misses)
1021 system.cpu1.dcache.ReadReq_accesses::total 41532 # number of ReadReq accesses(hits+misses)
1022 system.cpu1.dcache.WriteReq_accesses::cpu1.data 16416 # number of WriteReq accesses(hits+misses)
1023 system.cpu1.dcache.WriteReq_accesses::total 16416 # number of WriteReq accesses(hits+misses)
1024 system.cpu1.dcache.SwapReq_accesses::cpu1.data 62 # number of SwapReq accesses(hits+misses)
1025 system.cpu1.dcache.SwapReq_accesses::total 62 # number of SwapReq accesses(hits+misses)
1026 system.cpu1.dcache.demand_accesses::cpu1.data 57948 # number of demand (read+write) accesses
1027 system.cpu1.dcache.demand_accesses::total 57948 # number of demand (read+write) accesses
1028 system.cpu1.dcache.overall_accesses::cpu1.data 57948 # number of overall (read+write) accesses
1029 system.cpu1.dcache.overall_accesses::total 57948 # number of overall (read+write) accesses
1030 system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.003708 # miss rate for ReadReq accesses
1031 system.cpu1.dcache.ReadReq_miss_rate::total 0.003708 # miss rate for ReadReq accesses
1032 system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.006640 # miss rate for WriteReq accesses
1033 system.cpu1.dcache.WriteReq_miss_rate::total 0.006640 # miss rate for WriteReq accesses
1034 system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.822581 # miss rate for SwapReq accesses
1035 system.cpu1.dcache.SwapReq_miss_rate::total 0.822581 # miss rate for SwapReq accesses
1036 system.cpu1.dcache.demand_miss_rate::cpu1.data 0.004539 # miss rate for demand accesses
1037 system.cpu1.dcache.demand_miss_rate::total 0.004539 # miss rate for demand accesses
1038 system.cpu1.dcache.overall_miss_rate::cpu1.data 0.004539 # miss rate for overall accesses
1039 system.cpu1.dcache.overall_miss_rate::total 0.004539 # miss rate for overall accesses
1040 system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16201.188312 # average ReadReq miss latency
1041 system.cpu1.dcache.ReadReq_avg_miss_latency::total 16201.188312 # average ReadReq miss latency
1042 system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18160.550459 # average WriteReq miss latency
1043 system.cpu1.dcache.WriteReq_avg_miss_latency::total 18160.550459 # average WriteReq miss latency
1044 system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 4107.843137 # average SwapReq miss latency
1045 system.cpu1.dcache.SwapReq_avg_miss_latency::total 4107.843137 # average SwapReq miss latency
1046 system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17013.243346 # average overall miss latency
1047 system.cpu1.dcache.demand_avg_miss_latency::total 17013.243346 # average overall miss latency
1048 system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17013.243346 # average overall miss latency
1049 system.cpu1.dcache.overall_avg_miss_latency::total 17013.243346 # average overall miss latency
1050 system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1051 system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1052 system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
1053 system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
1054 system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1055 system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1056 system.cpu1.dcache.fast_writes 0 # number of fast writes performed
1057 system.cpu1.dcache.cache_copies 0 # number of cache copies performed
1058 system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 154 # number of ReadReq MSHR misses
1059 system.cpu1.dcache.ReadReq_mshr_misses::total 154 # number of ReadReq MSHR misses
1060 system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 109 # number of WriteReq MSHR misses
1061 system.cpu1.dcache.WriteReq_mshr_misses::total 109 # number of WriteReq MSHR misses
1062 system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 51 # number of SwapReq MSHR misses
1063 system.cpu1.dcache.SwapReq_mshr_misses::total 51 # number of SwapReq MSHR misses
1064 system.cpu1.dcache.demand_mshr_misses::cpu1.data 263 # number of demand (read+write) MSHR misses
1065 system.cpu1.dcache.demand_mshr_misses::total 263 # number of demand (read+write) MSHR misses
1066 system.cpu1.dcache.overall_mshr_misses::cpu1.data 263 # number of overall MSHR misses
1067 system.cpu1.dcache.overall_mshr_misses::total 263 # number of overall MSHR misses
1068 system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2170017 # number of ReadReq MSHR miss cycles
1069 system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2170017 # number of ReadReq MSHR miss cycles
1070 system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1761500 # number of WriteReq MSHR miss cycles
1071 system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1761500 # number of WriteReq MSHR miss cycles
1072 system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 107500 # number of SwapReq MSHR miss cycles
1073 system.cpu1.dcache.SwapReq_mshr_miss_latency::total 107500 # number of SwapReq MSHR miss cycles
1074 system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3931517 # number of demand (read+write) MSHR miss cycles
1075 system.cpu1.dcache.demand_mshr_miss_latency::total 3931517 # number of demand (read+write) MSHR miss cycles
1076 system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3931517 # number of overall MSHR miss cycles
1077 system.cpu1.dcache.overall_mshr_miss_latency::total 3931517 # number of overall MSHR miss cycles
1078 system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003708 # mshr miss rate for ReadReq accesses
1079 system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003708 # mshr miss rate for ReadReq accesses
1080 system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.006640 # mshr miss rate for WriteReq accesses
1081 system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.006640 # mshr miss rate for WriteReq accesses
1082 system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.822581 # mshr miss rate for SwapReq accesses
1083 system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.822581 # mshr miss rate for SwapReq accesses
1084 system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.004539 # mshr miss rate for demand accesses
1085 system.cpu1.dcache.demand_mshr_miss_rate::total 0.004539 # mshr miss rate for demand accesses
1086 system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.004539 # mshr miss rate for overall accesses
1087 system.cpu1.dcache.overall_mshr_miss_rate::total 0.004539 # mshr miss rate for overall accesses
1088 system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14091.019481 # average ReadReq mshr miss latency
1089 system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14091.019481 # average ReadReq mshr miss latency
1090 system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16160.550459 # average WriteReq mshr miss latency
1091 system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16160.550459 # average WriteReq mshr miss latency
1092 system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 2107.843137 # average SwapReq mshr miss latency
1093 system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 2107.843137 # average SwapReq mshr miss latency
1094 system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14948.733840 # average overall mshr miss latency
1095 system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14948.733840 # average overall mshr miss latency
1096 system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14948.733840 # average overall mshr miss latency
1097 system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14948.733840 # average overall mshr miss latency
1098 system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1099 system.cpu2.numCycles 525586 # number of cpu cycles simulated
1100 system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
1101 system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
1102 system.cpu2.committedInsts 164866 # Number of instructions committed
1103 system.cpu2.committedOps 164866 # Number of ops (including micro ops) committed
1104 system.cpu2.num_int_alu_accesses 112988 # Number of integer alu accesses
1105 system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses
1106 system.cpu2.num_func_calls 637 # number of times a function call or return occured
1107 system.cpu2.num_conditional_control_insts 29949 # number of instructions that are conditional controls
1108 system.cpu2.num_int_insts 112988 # number of integer instructions
1109 system.cpu2.num_fp_insts 0 # number of float instructions
1110 system.cpu2.num_int_register_reads 294363 # number of times the integer registers were read
1111 system.cpu2.num_int_register_writes 112900 # number of times the integer registers were written
1112 system.cpu2.num_fp_register_reads 0 # number of times the floating registers were read
1113 system.cpu2.num_fp_register_writes 0 # number of times the floating registers were written
1114 system.cpu2.num_mem_refs 59208 # number of memory refs
1115 system.cpu2.num_load_insts 42171 # Number of load instructions
1116 system.cpu2.num_store_insts 17037 # Number of store instructions
1117 system.cpu2.num_idle_cycles 69603.869304 # Number of idle cycles
1118 system.cpu2.num_busy_cycles 455982.130696 # Number of busy cycles
1119 system.cpu2.not_idle_fraction 0.867569 # Percentage of non-idle cycles
1120 system.cpu2.idle_fraction 0.132431 # Percentage of idle cycles
1121 system.cpu2.Branches 31596 # Number of branches fetched
1122 system.cpu2.op_class::No_OpClass 22386 13.58% 13.58% # Class of executed instruction
1123 system.cpu2.op_class::IntAlu 75723 45.92% 59.50% # Class of executed instruction
1124 system.cpu2.op_class::IntMult 0 0.00% 59.50% # Class of executed instruction
1125 system.cpu2.op_class::IntDiv 0 0.00% 59.50% # Class of executed instruction
1126 system.cpu2.op_class::FloatAdd 0 0.00% 59.50% # Class of executed instruction
1127 system.cpu2.op_class::FloatCmp 0 0.00% 59.50% # Class of executed instruction
1128 system.cpu2.op_class::FloatCvt 0 0.00% 59.50% # Class of executed instruction
1129 system.cpu2.op_class::FloatMult 0 0.00% 59.50% # Class of executed instruction
1130 system.cpu2.op_class::FloatDiv 0 0.00% 59.50% # Class of executed instruction
1131 system.cpu2.op_class::FloatSqrt 0 0.00% 59.50% # Class of executed instruction
1132 system.cpu2.op_class::SimdAdd 0 0.00% 59.50% # Class of executed instruction
1133 system.cpu2.op_class::SimdAddAcc 0 0.00% 59.50% # Class of executed instruction
1134 system.cpu2.op_class::SimdAlu 0 0.00% 59.50% # Class of executed instruction
1135 system.cpu2.op_class::SimdCmp 0 0.00% 59.50% # Class of executed instruction
1136 system.cpu2.op_class::SimdCvt 0 0.00% 59.50% # Class of executed instruction
1137 system.cpu2.op_class::SimdMisc 0 0.00% 59.50% # Class of executed instruction
1138 system.cpu2.op_class::SimdMult 0 0.00% 59.50% # Class of executed instruction
1139 system.cpu2.op_class::SimdMultAcc 0 0.00% 59.50% # Class of executed instruction
1140 system.cpu2.op_class::SimdShift 0 0.00% 59.50% # Class of executed instruction
1141 system.cpu2.op_class::SimdShiftAcc 0 0.00% 59.50% # Class of executed instruction
1142 system.cpu2.op_class::SimdSqrt 0 0.00% 59.50% # Class of executed instruction
1143 system.cpu2.op_class::SimdFloatAdd 0 0.00% 59.50% # Class of executed instruction
1144 system.cpu2.op_class::SimdFloatAlu 0 0.00% 59.50% # Class of executed instruction
1145 system.cpu2.op_class::SimdFloatCmp 0 0.00% 59.50% # Class of executed instruction
1146 system.cpu2.op_class::SimdFloatCvt 0 0.00% 59.50% # Class of executed instruction
1147 system.cpu2.op_class::SimdFloatDiv 0 0.00% 59.50% # Class of executed instruction
1148 system.cpu2.op_class::SimdFloatMisc 0 0.00% 59.50% # Class of executed instruction
1149 system.cpu2.op_class::SimdFloatMult 0 0.00% 59.50% # Class of executed instruction
1150 system.cpu2.op_class::SimdFloatMultAcc 0 0.00% 59.50% # Class of executed instruction
1151 system.cpu2.op_class::SimdFloatSqrt 0 0.00% 59.50% # Class of executed instruction
1152 system.cpu2.op_class::MemRead 49752 30.17% 89.67% # Class of executed instruction
1153 system.cpu2.op_class::MemWrite 17037 10.33% 100.00% # Class of executed instruction
1154 system.cpu2.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
1155 system.cpu2.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
1156 system.cpu2.op_class::total 164898 # Class of executed instruction
1157 system.cpu2.icache.tags.replacements 280 # number of replacements
1158 system.cpu2.icache.tags.tagsinuse 67.625211 # Cycle average of tags in use
1159 system.cpu2.icache.tags.total_refs 164533 # Total number of references to valid blocks.
1160 system.cpu2.icache.tags.sampled_refs 366 # Sample count of references to valid blocks.
1161 system.cpu2.icache.tags.avg_refs 449.543716 # Average number of references to valid blocks.
1162 system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1163 system.cpu2.icache.tags.occ_blocks::cpu2.inst 67.625211 # Average occupied blocks per requestor
1164 system.cpu2.icache.tags.occ_percent::cpu2.inst 0.132080 # Average percentage of cache occupancy
1165 system.cpu2.icache.tags.occ_percent::total 0.132080 # Average percentage of cache occupancy
1166 system.cpu2.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id
1167 system.cpu2.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id
1168 system.cpu2.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id
1169 system.cpu2.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id
1170 system.cpu2.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id
1171 system.cpu2.icache.tags.tag_accesses 165265 # Number of tag accesses
1172 system.cpu2.icache.tags.data_accesses 165265 # Number of data accesses
1173 system.cpu2.icache.ReadReq_hits::cpu2.inst 164533 # number of ReadReq hits
1174 system.cpu2.icache.ReadReq_hits::total 164533 # number of ReadReq hits
1175 system.cpu2.icache.demand_hits::cpu2.inst 164533 # number of demand (read+write) hits
1176 system.cpu2.icache.demand_hits::total 164533 # number of demand (read+write) hits
1177 system.cpu2.icache.overall_hits::cpu2.inst 164533 # number of overall hits
1178 system.cpu2.icache.overall_hits::total 164533 # number of overall hits
1179 system.cpu2.icache.ReadReq_misses::cpu2.inst 366 # number of ReadReq misses
1180 system.cpu2.icache.ReadReq_misses::total 366 # number of ReadReq misses
1181 system.cpu2.icache.demand_misses::cpu2.inst 366 # number of demand (read+write) misses
1182 system.cpu2.icache.demand_misses::total 366 # number of demand (read+write) misses
1183 system.cpu2.icache.overall_misses::cpu2.inst 366 # number of overall misses
1184 system.cpu2.icache.overall_misses::total 366 # number of overall misses
1185 system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 5251988 # number of ReadReq miss cycles
1186 system.cpu2.icache.ReadReq_miss_latency::total 5251988 # number of ReadReq miss cycles
1187 system.cpu2.icache.demand_miss_latency::cpu2.inst 5251988 # number of demand (read+write) miss cycles
1188 system.cpu2.icache.demand_miss_latency::total 5251988 # number of demand (read+write) miss cycles
1189 system.cpu2.icache.overall_miss_latency::cpu2.inst 5251988 # number of overall miss cycles
1190 system.cpu2.icache.overall_miss_latency::total 5251988 # number of overall miss cycles
1191 system.cpu2.icache.ReadReq_accesses::cpu2.inst 164899 # number of ReadReq accesses(hits+misses)
1192 system.cpu2.icache.ReadReq_accesses::total 164899 # number of ReadReq accesses(hits+misses)
1193 system.cpu2.icache.demand_accesses::cpu2.inst 164899 # number of demand (read+write) accesses
1194 system.cpu2.icache.demand_accesses::total 164899 # number of demand (read+write) accesses
1195 system.cpu2.icache.overall_accesses::cpu2.inst 164899 # number of overall (read+write) accesses
1196 system.cpu2.icache.overall_accesses::total 164899 # number of overall (read+write) accesses
1197 system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002220 # miss rate for ReadReq accesses
1198 system.cpu2.icache.ReadReq_miss_rate::total 0.002220 # miss rate for ReadReq accesses
1199 system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002220 # miss rate for demand accesses
1200 system.cpu2.icache.demand_miss_rate::total 0.002220 # miss rate for demand accesses
1201 system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002220 # miss rate for overall accesses
1202 system.cpu2.icache.overall_miss_rate::total 0.002220 # miss rate for overall accesses
1203 system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 14349.693989 # average ReadReq miss latency
1204 system.cpu2.icache.ReadReq_avg_miss_latency::total 14349.693989 # average ReadReq miss latency
1205 system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 14349.693989 # average overall miss latency
1206 system.cpu2.icache.demand_avg_miss_latency::total 14349.693989 # average overall miss latency
1207 system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 14349.693989 # average overall miss latency
1208 system.cpu2.icache.overall_avg_miss_latency::total 14349.693989 # average overall miss latency
1209 system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1210 system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1211 system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked
1212 system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked
1213 system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1214 system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1215 system.cpu2.icache.fast_writes 0 # number of fast writes performed
1216 system.cpu2.icache.cache_copies 0 # number of cache copies performed
1217 system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 366 # number of ReadReq MSHR misses
1218 system.cpu2.icache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses
1219 system.cpu2.icache.demand_mshr_misses::cpu2.inst 366 # number of demand (read+write) MSHR misses
1220 system.cpu2.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses
1221 system.cpu2.icache.overall_mshr_misses::cpu2.inst 366 # number of overall MSHR misses
1222 system.cpu2.icache.overall_mshr_misses::total 366 # number of overall MSHR misses
1223 system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 4510012 # number of ReadReq MSHR miss cycles
1224 system.cpu2.icache.ReadReq_mshr_miss_latency::total 4510012 # number of ReadReq MSHR miss cycles
1225 system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 4510012 # number of demand (read+write) MSHR miss cycles
1226 system.cpu2.icache.demand_mshr_miss_latency::total 4510012 # number of demand (read+write) MSHR miss cycles
1227 system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 4510012 # number of overall MSHR miss cycles
1228 system.cpu2.icache.overall_mshr_miss_latency::total 4510012 # number of overall MSHR miss cycles
1229 system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.002220 # mshr miss rate for ReadReq accesses
1230 system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.002220 # mshr miss rate for ReadReq accesses
1231 system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.002220 # mshr miss rate for demand accesses
1232 system.cpu2.icache.demand_mshr_miss_rate::total 0.002220 # mshr miss rate for demand accesses
1233 system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.002220 # mshr miss rate for overall accesses
1234 system.cpu2.icache.overall_mshr_miss_rate::total 0.002220 # mshr miss rate for overall accesses
1235 system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12322.437158 # average ReadReq mshr miss latency
1236 system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 12322.437158 # average ReadReq mshr miss latency
1237 system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 12322.437158 # average overall mshr miss latency
1238 system.cpu2.icache.demand_avg_mshr_miss_latency::total 12322.437158 # average overall mshr miss latency
1239 system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 12322.437158 # average overall mshr miss latency
1240 system.cpu2.icache.overall_avg_mshr_miss_latency::total 12322.437158 # average overall mshr miss latency
1241 system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1242 system.cpu2.dcache.tags.replacements 0 # number of replacements
1243 system.cpu2.dcache.tags.tagsinuse 26.763988 # Cycle average of tags in use
1244 system.cpu2.dcache.tags.total_refs 36347 # Total number of references to valid blocks.
1245 system.cpu2.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks.
1246 system.cpu2.dcache.tags.avg_refs 1253.344828 # Average number of references to valid blocks.
1247 system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1248 system.cpu2.dcache.tags.occ_blocks::cpu2.data 26.763988 # Average occupied blocks per requestor
1249 system.cpu2.dcache.tags.occ_percent::cpu2.data 0.052273 # Average percentage of cache occupancy
1250 system.cpu2.dcache.tags.occ_percent::total 0.052273 # Average percentage of cache occupancy
1251 system.cpu2.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id
1252 system.cpu2.dcache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id
1253 system.cpu2.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id
1254 system.cpu2.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id
1255 system.cpu2.dcache.tags.tag_accesses 237038 # Number of tag accesses
1256 system.cpu2.dcache.tags.data_accesses 237038 # Number of data accesses
1257 system.cpu2.dcache.ReadReq_hits::cpu2.data 42011 # number of ReadReq hits
1258 system.cpu2.dcache.ReadReq_hits::total 42011 # number of ReadReq hits
1259 system.cpu2.dcache.WriteReq_hits::cpu2.data 16865 # number of WriteReq hits
1260 system.cpu2.dcache.WriteReq_hits::total 16865 # number of WriteReq hits
1261 system.cpu2.dcache.SwapReq_hits::cpu2.data 10 # number of SwapReq hits
1262 system.cpu2.dcache.SwapReq_hits::total 10 # number of SwapReq hits
1263 system.cpu2.dcache.demand_hits::cpu2.data 58876 # number of demand (read+write) hits
1264 system.cpu2.dcache.demand_hits::total 58876 # number of demand (read+write) hits
1265 system.cpu2.dcache.overall_hits::cpu2.data 58876 # number of overall hits
1266 system.cpu2.dcache.overall_hits::total 58876 # number of overall hits
1267 system.cpu2.dcache.ReadReq_misses::cpu2.data 152 # number of ReadReq misses
1268 system.cpu2.dcache.ReadReq_misses::total 152 # number of ReadReq misses
1269 system.cpu2.dcache.WriteReq_misses::cpu2.data 110 # number of WriteReq misses
1270 system.cpu2.dcache.WriteReq_misses::total 110 # number of WriteReq misses
1271 system.cpu2.dcache.SwapReq_misses::cpu2.data 50 # number of SwapReq misses
1272 system.cpu2.dcache.SwapReq_misses::total 50 # number of SwapReq misses
1273 system.cpu2.dcache.demand_misses::cpu2.data 262 # number of demand (read+write) misses
1274 system.cpu2.dcache.demand_misses::total 262 # number of demand (read+write) misses
1275 system.cpu2.dcache.overall_misses::cpu2.data 262 # number of overall misses
1276 system.cpu2.dcache.overall_misses::total 262 # number of overall misses
1277 system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 2128981 # number of ReadReq miss cycles
1278 system.cpu2.dcache.ReadReq_miss_latency::total 2128981 # number of ReadReq miss cycles
1279 system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 1929500 # number of WriteReq miss cycles
1280 system.cpu2.dcache.WriteReq_miss_latency::total 1929500 # number of WriteReq miss cycles
1281 system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 204500 # number of SwapReq miss cycles
1282 system.cpu2.dcache.SwapReq_miss_latency::total 204500 # number of SwapReq miss cycles
1283 system.cpu2.dcache.demand_miss_latency::cpu2.data 4058481 # number of demand (read+write) miss cycles
1284 system.cpu2.dcache.demand_miss_latency::total 4058481 # number of demand (read+write) miss cycles
1285 system.cpu2.dcache.overall_miss_latency::cpu2.data 4058481 # number of overall miss cycles
1286 system.cpu2.dcache.overall_miss_latency::total 4058481 # number of overall miss cycles
1287 system.cpu2.dcache.ReadReq_accesses::cpu2.data 42163 # number of ReadReq accesses(hits+misses)
1288 system.cpu2.dcache.ReadReq_accesses::total 42163 # number of ReadReq accesses(hits+misses)
1289 system.cpu2.dcache.WriteReq_accesses::cpu2.data 16975 # number of WriteReq accesses(hits+misses)
1290 system.cpu2.dcache.WriteReq_accesses::total 16975 # number of WriteReq accesses(hits+misses)
1291 system.cpu2.dcache.SwapReq_accesses::cpu2.data 60 # number of SwapReq accesses(hits+misses)
1292 system.cpu2.dcache.SwapReq_accesses::total 60 # number of SwapReq accesses(hits+misses)
1293 system.cpu2.dcache.demand_accesses::cpu2.data 59138 # number of demand (read+write) accesses
1294 system.cpu2.dcache.demand_accesses::total 59138 # number of demand (read+write) accesses
1295 system.cpu2.dcache.overall_accesses::cpu2.data 59138 # number of overall (read+write) accesses
1296 system.cpu2.dcache.overall_accesses::total 59138 # number of overall (read+write) accesses
1297 system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003605 # miss rate for ReadReq accesses
1298 system.cpu2.dcache.ReadReq_miss_rate::total 0.003605 # miss rate for ReadReq accesses
1299 system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.006480 # miss rate for WriteReq accesses
1300 system.cpu2.dcache.WriteReq_miss_rate::total 0.006480 # miss rate for WriteReq accesses
1301 system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.833333 # miss rate for SwapReq accesses
1302 system.cpu2.dcache.SwapReq_miss_rate::total 0.833333 # miss rate for SwapReq accesses
1303 system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004430 # miss rate for demand accesses
1304 system.cpu2.dcache.demand_miss_rate::total 0.004430 # miss rate for demand accesses
1305 system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004430 # miss rate for overall accesses
1306 system.cpu2.dcache.overall_miss_rate::total 0.004430 # miss rate for overall accesses
1307 system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 14006.453947 # average ReadReq miss latency
1308 system.cpu2.dcache.ReadReq_avg_miss_latency::total 14006.453947 # average ReadReq miss latency
1309 system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 17540.909091 # average WriteReq miss latency
1310 system.cpu2.dcache.WriteReq_avg_miss_latency::total 17540.909091 # average WriteReq miss latency
1311 system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 4090 # average SwapReq miss latency
1312 system.cpu2.dcache.SwapReq_avg_miss_latency::total 4090 # average SwapReq miss latency
1313 system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 15490.385496 # average overall miss latency
1314 system.cpu2.dcache.demand_avg_miss_latency::total 15490.385496 # average overall miss latency
1315 system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 15490.385496 # average overall miss latency
1316 system.cpu2.dcache.overall_avg_miss_latency::total 15490.385496 # average overall miss latency
1317 system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1318 system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1319 system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
1320 system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked
1321 system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1322 system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1323 system.cpu2.dcache.fast_writes 0 # number of fast writes performed
1324 system.cpu2.dcache.cache_copies 0 # number of cache copies performed
1325 system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 152 # number of ReadReq MSHR misses
1326 system.cpu2.dcache.ReadReq_mshr_misses::total 152 # number of ReadReq MSHR misses
1327 system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 110 # number of WriteReq MSHR misses
1328 system.cpu2.dcache.WriteReq_mshr_misses::total 110 # number of WriteReq MSHR misses
1329 system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 50 # number of SwapReq MSHR misses
1330 system.cpu2.dcache.SwapReq_mshr_misses::total 50 # number of SwapReq MSHR misses
1331 system.cpu2.dcache.demand_mshr_misses::cpu2.data 262 # number of demand (read+write) MSHR misses
1332 system.cpu2.dcache.demand_mshr_misses::total 262 # number of demand (read+write) MSHR misses
1333 system.cpu2.dcache.overall_mshr_misses::cpu2.data 262 # number of overall MSHR misses
1334 system.cpu2.dcache.overall_mshr_misses::total 262 # number of overall MSHR misses
1335 system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1809019 # number of ReadReq MSHR miss cycles
1336 system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1809019 # number of ReadReq MSHR miss cycles
1337 system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1709500 # number of WriteReq MSHR miss cycles
1338 system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1709500 # number of WriteReq MSHR miss cycles
1339 system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 104500 # number of SwapReq MSHR miss cycles
1340 system.cpu2.dcache.SwapReq_mshr_miss_latency::total 104500 # number of SwapReq MSHR miss cycles
1341 system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3518519 # number of demand (read+write) MSHR miss cycles
1342 system.cpu2.dcache.demand_mshr_miss_latency::total 3518519 # number of demand (read+write) MSHR miss cycles
1343 system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3518519 # number of overall MSHR miss cycles
1344 system.cpu2.dcache.overall_mshr_miss_latency::total 3518519 # number of overall MSHR miss cycles
1345 system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003605 # mshr miss rate for ReadReq accesses
1346 system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003605 # mshr miss rate for ReadReq accesses
1347 system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.006480 # mshr miss rate for WriteReq accesses
1348 system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.006480 # mshr miss rate for WriteReq accesses
1349 system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.833333 # mshr miss rate for SwapReq accesses
1350 system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.833333 # mshr miss rate for SwapReq accesses
1351 system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004430 # mshr miss rate for demand accesses
1352 system.cpu2.dcache.demand_mshr_miss_rate::total 0.004430 # mshr miss rate for demand accesses
1353 system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004430 # mshr miss rate for overall accesses
1354 system.cpu2.dcache.overall_mshr_miss_rate::total 0.004430 # mshr miss rate for overall accesses
1355 system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 11901.440789 # average ReadReq mshr miss latency
1356 system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 11901.440789 # average ReadReq mshr miss latency
1357 system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 15540.909091 # average WriteReq mshr miss latency
1358 system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 15540.909091 # average WriteReq mshr miss latency
1359 system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 2090 # average SwapReq mshr miss latency
1360 system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 2090 # average SwapReq mshr miss latency
1361 system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 13429.461832 # average overall mshr miss latency
1362 system.cpu2.dcache.demand_avg_mshr_miss_latency::total 13429.461832 # average overall mshr miss latency
1363 system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 13429.461832 # average overall mshr miss latency
1364 system.cpu2.dcache.overall_avg_mshr_miss_latency::total 13429.461832 # average overall mshr miss latency
1365 system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1366 system.cpu3.numCycles 525586 # number of cpu cycles simulated
1367 system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
1368 system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed
1369 system.cpu3.committedInsts 176656 # Number of instructions committed
1370 system.cpu3.committedOps 176656 # Number of ops (including micro ops) committed
1371 system.cpu3.num_int_alu_accesses 108218 # Number of integer alu accesses
1372 system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses
1373 system.cpu3.num_func_calls 637 # number of times a function call or return occured
1374 system.cpu3.num_conditional_control_insts 38223 # number of instructions that are conditional controls
1375 system.cpu3.num_int_insts 108218 # number of integer instructions
1376 system.cpu3.num_fp_insts 0 # number of float instructions
1377 system.cpu3.num_int_register_reads 242179 # number of times the integer registers were read
1378 system.cpu3.num_int_register_writes 89182 # number of times the integer registers were written
1379 system.cpu3.num_fp_register_reads 0 # number of times the floating registers were read
1380 system.cpu3.num_fp_register_writes 0 # number of times the floating registers were written
1381 system.cpu3.num_mem_refs 46164 # number of memory refs
1382 system.cpu3.num_load_insts 39753 # Number of load instructions
1383 system.cpu3.num_store_insts 6411 # Number of store instructions
1384 system.cpu3.num_idle_cycles 69867.868801 # Number of idle cycles
1385 system.cpu3.num_busy_cycles 455718.131199 # Number of busy cycles
1386 system.cpu3.not_idle_fraction 0.867067 # Percentage of non-idle cycles
1387 system.cpu3.idle_fraction 0.132933 # Percentage of idle cycles
1388 system.cpu3.Branches 39890 # Number of branches fetched
1389 system.cpu3.op_class::No_OpClass 30652 17.35% 17.35% # Class of executed instruction
1390 system.cpu3.op_class::IntAlu 73353 41.52% 58.86% # Class of executed instruction
1391 system.cpu3.op_class::IntMult 0 0.00% 58.86% # Class of executed instruction
1392 system.cpu3.op_class::IntDiv 0 0.00% 58.86% # Class of executed instruction
1393 system.cpu3.op_class::FloatAdd 0 0.00% 58.86% # Class of executed instruction
1394 system.cpu3.op_class::FloatCmp 0 0.00% 58.86% # Class of executed instruction
1395 system.cpu3.op_class::FloatCvt 0 0.00% 58.86% # Class of executed instruction
1396 system.cpu3.op_class::FloatMult 0 0.00% 58.86% # Class of executed instruction
1397 system.cpu3.op_class::FloatDiv 0 0.00% 58.86% # Class of executed instruction
1398 system.cpu3.op_class::FloatSqrt 0 0.00% 58.86% # Class of executed instruction
1399 system.cpu3.op_class::SimdAdd 0 0.00% 58.86% # Class of executed instruction
1400 system.cpu3.op_class::SimdAddAcc 0 0.00% 58.86% # Class of executed instruction
1401 system.cpu3.op_class::SimdAlu 0 0.00% 58.86% # Class of executed instruction
1402 system.cpu3.op_class::SimdCmp 0 0.00% 58.86% # Class of executed instruction
1403 system.cpu3.op_class::SimdCvt 0 0.00% 58.86% # Class of executed instruction
1404 system.cpu3.op_class::SimdMisc 0 0.00% 58.86% # Class of executed instruction
1405 system.cpu3.op_class::SimdMult 0 0.00% 58.86% # Class of executed instruction
1406 system.cpu3.op_class::SimdMultAcc 0 0.00% 58.86% # Class of executed instruction
1407 system.cpu3.op_class::SimdShift 0 0.00% 58.86% # Class of executed instruction
1408 system.cpu3.op_class::SimdShiftAcc 0 0.00% 58.86% # Class of executed instruction
1409 system.cpu3.op_class::SimdSqrt 0 0.00% 58.86% # Class of executed instruction
1410 system.cpu3.op_class::SimdFloatAdd 0 0.00% 58.86% # Class of executed instruction
1411 system.cpu3.op_class::SimdFloatAlu 0 0.00% 58.86% # Class of executed instruction
1412 system.cpu3.op_class::SimdFloatCmp 0 0.00% 58.86% # Class of executed instruction
1413 system.cpu3.op_class::SimdFloatCvt 0 0.00% 58.86% # Class of executed instruction
1414 system.cpu3.op_class::SimdFloatDiv 0 0.00% 58.86% # Class of executed instruction
1415 system.cpu3.op_class::SimdFloatMisc 0 0.00% 58.86% # Class of executed instruction
1416 system.cpu3.op_class::SimdFloatMult 0 0.00% 58.86% # Class of executed instruction
1417 system.cpu3.op_class::SimdFloatMultAcc 0 0.00% 58.86% # Class of executed instruction
1418 system.cpu3.op_class::SimdFloatSqrt 0 0.00% 58.86% # Class of executed instruction
1419 system.cpu3.op_class::MemRead 66272 37.51% 96.37% # Class of executed instruction
1420 system.cpu3.op_class::MemWrite 6411 3.63% 100.00% # Class of executed instruction
1421 system.cpu3.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
1422 system.cpu3.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
1423 system.cpu3.op_class::total 176688 # Class of executed instruction
1424 system.cpu3.icache.tags.replacements 281 # number of replacements
1425 system.cpu3.icache.tags.tagsinuse 65.598702 # Cycle average of tags in use
1426 system.cpu3.icache.tags.total_refs 176322 # Total number of references to valid blocks.
1427 system.cpu3.icache.tags.sampled_refs 367 # Sample count of references to valid blocks.
1428 system.cpu3.icache.tags.avg_refs 480.441417 # Average number of references to valid blocks.
1429 system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1430 system.cpu3.icache.tags.occ_blocks::cpu3.inst 65.598702 # Average occupied blocks per requestor
1431 system.cpu3.icache.tags.occ_percent::cpu3.inst 0.128122 # Average percentage of cache occupancy
1432 system.cpu3.icache.tags.occ_percent::total 0.128122 # Average percentage of cache occupancy
1433 system.cpu3.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id
1434 system.cpu3.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id
1435 system.cpu3.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id
1436 system.cpu3.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id
1437 system.cpu3.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id
1438 system.cpu3.icache.tags.tag_accesses 177056 # Number of tag accesses
1439 system.cpu3.icache.tags.data_accesses 177056 # Number of data accesses
1440 system.cpu3.icache.ReadReq_hits::cpu3.inst 176322 # number of ReadReq hits
1441 system.cpu3.icache.ReadReq_hits::total 176322 # number of ReadReq hits
1442 system.cpu3.icache.demand_hits::cpu3.inst 176322 # number of demand (read+write) hits
1443 system.cpu3.icache.demand_hits::total 176322 # number of demand (read+write) hits
1444 system.cpu3.icache.overall_hits::cpu3.inst 176322 # number of overall hits
1445 system.cpu3.icache.overall_hits::total 176322 # number of overall hits
1446 system.cpu3.icache.ReadReq_misses::cpu3.inst 367 # number of ReadReq misses
1447 system.cpu3.icache.ReadReq_misses::total 367 # number of ReadReq misses
1448 system.cpu3.icache.demand_misses::cpu3.inst 367 # number of demand (read+write) misses
1449 system.cpu3.icache.demand_misses::total 367 # number of demand (read+write) misses
1450 system.cpu3.icache.overall_misses::cpu3.inst 367 # number of overall misses
1451 system.cpu3.icache.overall_misses::total 367 # number of overall misses
1452 system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 5147499 # number of ReadReq miss cycles
1453 system.cpu3.icache.ReadReq_miss_latency::total 5147499 # number of ReadReq miss cycles
1454 system.cpu3.icache.demand_miss_latency::cpu3.inst 5147499 # number of demand (read+write) miss cycles
1455 system.cpu3.icache.demand_miss_latency::total 5147499 # number of demand (read+write) miss cycles
1456 system.cpu3.icache.overall_miss_latency::cpu3.inst 5147499 # number of overall miss cycles
1457 system.cpu3.icache.overall_miss_latency::total 5147499 # number of overall miss cycles
1458 system.cpu3.icache.ReadReq_accesses::cpu3.inst 176689 # number of ReadReq accesses(hits+misses)
1459 system.cpu3.icache.ReadReq_accesses::total 176689 # number of ReadReq accesses(hits+misses)
1460 system.cpu3.icache.demand_accesses::cpu3.inst 176689 # number of demand (read+write) accesses
1461 system.cpu3.icache.demand_accesses::total 176689 # number of demand (read+write) accesses
1462 system.cpu3.icache.overall_accesses::cpu3.inst 176689 # number of overall (read+write) accesses
1463 system.cpu3.icache.overall_accesses::total 176689 # number of overall (read+write) accesses
1464 system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002077 # miss rate for ReadReq accesses
1465 system.cpu3.icache.ReadReq_miss_rate::total 0.002077 # miss rate for ReadReq accesses
1466 system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002077 # miss rate for demand accesses
1467 system.cpu3.icache.demand_miss_rate::total 0.002077 # miss rate for demand accesses
1468 system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002077 # miss rate for overall accesses
1469 system.cpu3.icache.overall_miss_rate::total 0.002077 # miss rate for overall accesses
1470 system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 14025.882834 # average ReadReq miss latency
1471 system.cpu3.icache.ReadReq_avg_miss_latency::total 14025.882834 # average ReadReq miss latency
1472 system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 14025.882834 # average overall miss latency
1473 system.cpu3.icache.demand_avg_miss_latency::total 14025.882834 # average overall miss latency
1474 system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 14025.882834 # average overall miss latency
1475 system.cpu3.icache.overall_avg_miss_latency::total 14025.882834 # average overall miss latency
1476 system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1477 system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1478 system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked
1479 system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked
1480 system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1481 system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1482 system.cpu3.icache.fast_writes 0 # number of fast writes performed
1483 system.cpu3.icache.cache_copies 0 # number of cache copies performed
1484 system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 367 # number of ReadReq MSHR misses
1485 system.cpu3.icache.ReadReq_mshr_misses::total 367 # number of ReadReq MSHR misses
1486 system.cpu3.icache.demand_mshr_misses::cpu3.inst 367 # number of demand (read+write) MSHR misses
1487 system.cpu3.icache.demand_mshr_misses::total 367 # number of demand (read+write) MSHR misses
1488 system.cpu3.icache.overall_mshr_misses::cpu3.inst 367 # number of overall MSHR misses
1489 system.cpu3.icache.overall_mshr_misses::total 367 # number of overall MSHR misses
1490 system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 4412501 # number of ReadReq MSHR miss cycles
1491 system.cpu3.icache.ReadReq_mshr_miss_latency::total 4412501 # number of ReadReq MSHR miss cycles
1492 system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 4412501 # number of demand (read+write) MSHR miss cycles
1493 system.cpu3.icache.demand_mshr_miss_latency::total 4412501 # number of demand (read+write) MSHR miss cycles
1494 system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 4412501 # number of overall MSHR miss cycles
1495 system.cpu3.icache.overall_mshr_miss_latency::total 4412501 # number of overall MSHR miss cycles
1496 system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.002077 # mshr miss rate for ReadReq accesses
1497 system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.002077 # mshr miss rate for ReadReq accesses
1498 system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.002077 # mshr miss rate for demand accesses
1499 system.cpu3.icache.demand_mshr_miss_rate::total 0.002077 # mshr miss rate for demand accesses
1500 system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.002077 # mshr miss rate for overall accesses
1501 system.cpu3.icache.overall_mshr_miss_rate::total 0.002077 # mshr miss rate for overall accesses
1502 system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12023.163488 # average ReadReq mshr miss latency
1503 system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12023.163488 # average ReadReq mshr miss latency
1504 system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12023.163488 # average overall mshr miss latency
1505 system.cpu3.icache.demand_avg_mshr_miss_latency::total 12023.163488 # average overall mshr miss latency
1506 system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12023.163488 # average overall mshr miss latency
1507 system.cpu3.icache.overall_avg_mshr_miss_latency::total 12023.163488 # average overall mshr miss latency
1508 system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1509 system.cpu3.dcache.tags.replacements 0 # number of replacements
1510 system.cpu3.dcache.tags.tagsinuse 25.915188 # Cycle average of tags in use
1511 system.cpu3.dcache.tags.total_refs 15020 # Total number of references to valid blocks.
1512 system.cpu3.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks.
1513 system.cpu3.dcache.tags.avg_refs 517.931034 # Average number of references to valid blocks.
1514 system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1515 system.cpu3.dcache.tags.occ_blocks::cpu3.data 25.915188 # Average occupied blocks per requestor
1516 system.cpu3.dcache.tags.occ_percent::cpu3.data 0.050616 # Average percentage of cache occupancy
1517 system.cpu3.dcache.tags.occ_percent::total 0.050616 # Average percentage of cache occupancy
1518 system.cpu3.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id
1519 system.cpu3.dcache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id
1520 system.cpu3.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id
1521 system.cpu3.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id
1522 system.cpu3.dcache.tags.tag_accesses 184905 # Number of tag accesses
1523 system.cpu3.dcache.tags.data_accesses 184905 # Number of data accesses
1524 system.cpu3.dcache.ReadReq_hits::cpu3.data 39563 # number of ReadReq hits
1525 system.cpu3.dcache.ReadReq_hits::total 39563 # number of ReadReq hits
1526 system.cpu3.dcache.WriteReq_hits::cpu3.data 6216 # number of WriteReq hits
1527 system.cpu3.dcache.WriteReq_hits::total 6216 # number of WriteReq hits
1528 system.cpu3.dcache.SwapReq_hits::cpu3.data 19 # number of SwapReq hits
1529 system.cpu3.dcache.SwapReq_hits::total 19 # number of SwapReq hits
1530 system.cpu3.dcache.demand_hits::cpu3.data 45779 # number of demand (read+write) hits
1531 system.cpu3.dcache.demand_hits::total 45779 # number of demand (read+write) hits
1532 system.cpu3.dcache.overall_hits::cpu3.data 45779 # number of overall hits
1533 system.cpu3.dcache.overall_hits::total 45779 # number of overall hits
1534 system.cpu3.dcache.ReadReq_misses::cpu3.data 183 # number of ReadReq misses
1535 system.cpu3.dcache.ReadReq_misses::total 183 # number of ReadReq misses
1536 system.cpu3.dcache.WriteReq_misses::cpu3.data 105 # number of WriteReq misses
1537 system.cpu3.dcache.WriteReq_misses::total 105 # number of WriteReq misses
1538 system.cpu3.dcache.SwapReq_misses::cpu3.data 69 # number of SwapReq misses
1539 system.cpu3.dcache.SwapReq_misses::total 69 # number of SwapReq misses
1540 system.cpu3.dcache.demand_misses::cpu3.data 288 # number of demand (read+write) misses
1541 system.cpu3.dcache.demand_misses::total 288 # number of demand (read+write) misses
1542 system.cpu3.dcache.overall_misses::cpu3.data 288 # number of overall misses
1543 system.cpu3.dcache.overall_misses::total 288 # number of overall misses
1544 system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 3156473 # number of ReadReq miss cycles
1545 system.cpu3.dcache.ReadReq_miss_latency::total 3156473 # number of ReadReq miss cycles
1546 system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 2099000 # number of WriteReq miss cycles
1547 system.cpu3.dcache.WriteReq_miss_latency::total 2099000 # number of WriteReq miss cycles
1548 system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 280000 # number of SwapReq miss cycles
1549 system.cpu3.dcache.SwapReq_miss_latency::total 280000 # number of SwapReq miss cycles
1550 system.cpu3.dcache.demand_miss_latency::cpu3.data 5255473 # number of demand (read+write) miss cycles
1551 system.cpu3.dcache.demand_miss_latency::total 5255473 # number of demand (read+write) miss cycles
1552 system.cpu3.dcache.overall_miss_latency::cpu3.data 5255473 # number of overall miss cycles
1553 system.cpu3.dcache.overall_miss_latency::total 5255473 # number of overall miss cycles
1554 system.cpu3.dcache.ReadReq_accesses::cpu3.data 39746 # number of ReadReq accesses(hits+misses)
1555 system.cpu3.dcache.ReadReq_accesses::total 39746 # number of ReadReq accesses(hits+misses)
1556 system.cpu3.dcache.WriteReq_accesses::cpu3.data 6321 # number of WriteReq accesses(hits+misses)
1557 system.cpu3.dcache.WriteReq_accesses::total 6321 # number of WriteReq accesses(hits+misses)
1558 system.cpu3.dcache.SwapReq_accesses::cpu3.data 88 # number of SwapReq accesses(hits+misses)
1559 system.cpu3.dcache.SwapReq_accesses::total 88 # number of SwapReq accesses(hits+misses)
1560 system.cpu3.dcache.demand_accesses::cpu3.data 46067 # number of demand (read+write) accesses
1561 system.cpu3.dcache.demand_accesses::total 46067 # number of demand (read+write) accesses
1562 system.cpu3.dcache.overall_accesses::cpu3.data 46067 # number of overall (read+write) accesses
1563 system.cpu3.dcache.overall_accesses::total 46067 # number of overall (read+write) accesses
1564 system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.004604 # miss rate for ReadReq accesses
1565 system.cpu3.dcache.ReadReq_miss_rate::total 0.004604 # miss rate for ReadReq accesses
1566 system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.016611 # miss rate for WriteReq accesses
1567 system.cpu3.dcache.WriteReq_miss_rate::total 0.016611 # miss rate for WriteReq accesses
1568 system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.784091 # miss rate for SwapReq accesses
1569 system.cpu3.dcache.SwapReq_miss_rate::total 0.784091 # miss rate for SwapReq accesses
1570 system.cpu3.dcache.demand_miss_rate::cpu3.data 0.006252 # miss rate for demand accesses
1571 system.cpu3.dcache.demand_miss_rate::total 0.006252 # miss rate for demand accesses
1572 system.cpu3.dcache.overall_miss_rate::cpu3.data 0.006252 # miss rate for overall accesses
1573 system.cpu3.dcache.overall_miss_rate::total 0.006252 # miss rate for overall accesses
1574 system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 17248.486339 # average ReadReq miss latency
1575 system.cpu3.dcache.ReadReq_avg_miss_latency::total 17248.486339 # average ReadReq miss latency
1576 system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 19990.476190 # average WriteReq miss latency
1577 system.cpu3.dcache.WriteReq_avg_miss_latency::total 19990.476190 # average WriteReq miss latency
1578 system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 4057.971014 # average SwapReq miss latency
1579 system.cpu3.dcache.SwapReq_avg_miss_latency::total 4057.971014 # average SwapReq miss latency
1580 system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 18248.170139 # average overall miss latency
1581 system.cpu3.dcache.demand_avg_miss_latency::total 18248.170139 # average overall miss latency
1582 system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 18248.170139 # average overall miss latency
1583 system.cpu3.dcache.overall_avg_miss_latency::total 18248.170139 # average overall miss latency
1584 system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1585 system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1586 system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
1587 system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked
1588 system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1589 system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1590 system.cpu3.dcache.fast_writes 0 # number of fast writes performed
1591 system.cpu3.dcache.cache_copies 0 # number of cache copies performed
1592 system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 183 # number of ReadReq MSHR misses
1593 system.cpu3.dcache.ReadReq_mshr_misses::total 183 # number of ReadReq MSHR misses
1594 system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 105 # number of WriteReq MSHR misses
1595 system.cpu3.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses
1596 system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 69 # number of SwapReq MSHR misses
1597 system.cpu3.dcache.SwapReq_mshr_misses::total 69 # number of SwapReq MSHR misses
1598 system.cpu3.dcache.demand_mshr_misses::cpu3.data 288 # number of demand (read+write) MSHR misses
1599 system.cpu3.dcache.demand_mshr_misses::total 288 # number of demand (read+write) MSHR misses
1600 system.cpu3.dcache.overall_mshr_misses::cpu3.data 288 # number of overall MSHR misses
1601 system.cpu3.dcache.overall_mshr_misses::total 288 # number of overall MSHR misses
1602 system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 2772527 # number of ReadReq MSHR miss cycles
1603 system.cpu3.dcache.ReadReq_mshr_miss_latency::total 2772527 # number of ReadReq MSHR miss cycles
1604 system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1889000 # number of WriteReq MSHR miss cycles
1605 system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1889000 # number of WriteReq MSHR miss cycles
1606 system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 142000 # number of SwapReq MSHR miss cycles
1607 system.cpu3.dcache.SwapReq_mshr_miss_latency::total 142000 # number of SwapReq MSHR miss cycles
1608 system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 4661527 # number of demand (read+write) MSHR miss cycles
1609 system.cpu3.dcache.demand_mshr_miss_latency::total 4661527 # number of demand (read+write) MSHR miss cycles
1610 system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 4661527 # number of overall MSHR miss cycles
1611 system.cpu3.dcache.overall_mshr_miss_latency::total 4661527 # number of overall MSHR miss cycles
1612 system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.004604 # mshr miss rate for ReadReq accesses
1613 system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.004604 # mshr miss rate for ReadReq accesses
1614 system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.016611 # mshr miss rate for WriteReq accesses
1615 system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.016611 # mshr miss rate for WriteReq accesses
1616 system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.784091 # mshr miss rate for SwapReq accesses
1617 system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.784091 # mshr miss rate for SwapReq accesses
1618 system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.006252 # mshr miss rate for demand accesses
1619 system.cpu3.dcache.demand_mshr_miss_rate::total 0.006252 # mshr miss rate for demand accesses
1620 system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.006252 # mshr miss rate for overall accesses
1621 system.cpu3.dcache.overall_mshr_miss_rate::total 0.006252 # mshr miss rate for overall accesses
1622 system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 15150.420765 # average ReadReq mshr miss latency
1623 system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 15150.420765 # average ReadReq mshr miss latency
1624 system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 17990.476190 # average WriteReq mshr miss latency
1625 system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 17990.476190 # average WriteReq mshr miss latency
1626 system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 2057.971014 # average SwapReq mshr miss latency
1627 system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 2057.971014 # average SwapReq mshr miss latency
1628 system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 16185.857639 # average overall mshr miss latency
1629 system.cpu3.dcache.demand_avg_mshr_miss_latency::total 16185.857639 # average overall mshr miss latency
1630 system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 16185.857639 # average overall mshr miss latency
1631 system.cpu3.dcache.overall_avg_mshr_miss_latency::total 16185.857639 # average overall mshr miss latency
1632 system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1634 ---------- End Simulation Statistics ----------
projects / gem5.git / blob