2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.000265 # Number of seconds simulated
4 sim_ticks 264840500 # Number of ticks simulated
5 final_tick 264840500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 127010 # Simulator instruction rate (inst/s)
8 host_op_rate 127009 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 50783237 # Simulator tick rate (ticks/s)
10 host_mem_usage 243272 # Number of bytes of host memory used
11 host_seconds 5.22 # Real time elapsed on the host
12 sim_insts 662366 # Number of instructions simulated
13 sim_ops 662366 # Number of ops (including micro ops) simulated
14 system.voltage_domain.voltage 1 # Voltage in Volts
15 system.clk_domain.clock 1000 # Clock period in ticks
16 system.physmem.bytes_read::cpu0.inst 18240 # Number of bytes read from this memory
17 system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory
18 system.physmem.bytes_read::cpu1.inst 448 # Number of bytes read from this memory
19 system.physmem.bytes_read::cpu1.data 960 # Number of bytes read from this memory
20 system.physmem.bytes_read::cpu2.inst 3712 # Number of bytes read from this memory
21 system.physmem.bytes_read::cpu2.data 1472 # Number of bytes read from this memory
22 system.physmem.bytes_read::cpu3.inst 256 # Number of bytes read from this memory
23 system.physmem.bytes_read::cpu3.data 960 # Number of bytes read from this memory
24 system.physmem.bytes_read::total 36608 # Number of bytes read from this memory
25 system.physmem.bytes_inst_read::cpu0.inst 18240 # Number of instructions bytes read from this memory
26 system.physmem.bytes_inst_read::cpu1.inst 448 # Number of instructions bytes read from this memory
27 system.physmem.bytes_inst_read::cpu2.inst 3712 # Number of instructions bytes read from this memory
28 system.physmem.bytes_inst_read::cpu3.inst 256 # Number of instructions bytes read from this memory
29 system.physmem.bytes_inst_read::total 22656 # Number of instructions bytes read from this memory
30 system.physmem.num_reads::cpu0.inst 285 # Number of read requests responded to by this memory
31 system.physmem.num_reads::cpu0.data 165 # Number of read requests responded to by this memory
32 system.physmem.num_reads::cpu1.inst 7 # Number of read requests responded to by this memory
33 system.physmem.num_reads::cpu1.data 15 # Number of read requests responded to by this memory
34 system.physmem.num_reads::cpu2.inst 58 # Number of read requests responded to by this memory
35 system.physmem.num_reads::cpu2.data 23 # Number of read requests responded to by this memory
36 system.physmem.num_reads::cpu3.inst 4 # Number of read requests responded to by this memory
37 system.physmem.num_reads::cpu3.data 15 # Number of read requests responded to by this memory
38 system.physmem.num_reads::total 572 # Number of read requests responded to by this memory
39 system.physmem.bw_read::cpu0.inst 68871642 # Total read bandwidth from this memory (bytes/s)
40 system.physmem.bw_read::cpu0.data 39873056 # Total read bandwidth from this memory (bytes/s)
41 system.physmem.bw_read::cpu1.inst 1691584 # Total read bandwidth from this memory (bytes/s)
42 system.physmem.bw_read::cpu1.data 3624823 # Total read bandwidth from this memory (bytes/s)
43 system.physmem.bw_read::cpu2.inst 14015983 # Total read bandwidth from this memory (bytes/s)
44 system.physmem.bw_read::cpu2.data 5558062 # Total read bandwidth from this memory (bytes/s)
45 system.physmem.bw_read::cpu3.inst 966620 # Total read bandwidth from this memory (bytes/s)
46 system.physmem.bw_read::cpu3.data 3624823 # Total read bandwidth from this memory (bytes/s)
47 system.physmem.bw_read::total 138226593 # Total read bandwidth from this memory (bytes/s)
48 system.physmem.bw_inst_read::cpu0.inst 68871642 # Instruction read bandwidth from this memory (bytes/s)
49 system.physmem.bw_inst_read::cpu1.inst 1691584 # Instruction read bandwidth from this memory (bytes/s)
50 system.physmem.bw_inst_read::cpu2.inst 14015983 # Instruction read bandwidth from this memory (bytes/s)
51 system.physmem.bw_inst_read::cpu3.inst 966620 # Instruction read bandwidth from this memory (bytes/s)
52 system.physmem.bw_inst_read::total 85545829 # Instruction read bandwidth from this memory (bytes/s)
53 system.physmem.bw_total::cpu0.inst 68871642 # Total bandwidth to/from this memory (bytes/s)
54 system.physmem.bw_total::cpu0.data 39873056 # Total bandwidth to/from this memory (bytes/s)
55 system.physmem.bw_total::cpu1.inst 1691584 # Total bandwidth to/from this memory (bytes/s)
56 system.physmem.bw_total::cpu1.data 3624823 # Total bandwidth to/from this memory (bytes/s)
57 system.physmem.bw_total::cpu2.inst 14015983 # Total bandwidth to/from this memory (bytes/s)
58 system.physmem.bw_total::cpu2.data 5558062 # Total bandwidth to/from this memory (bytes/s)
59 system.physmem.bw_total::cpu3.inst 966620 # Total bandwidth to/from this memory (bytes/s)
60 system.physmem.bw_total::cpu3.data 3624823 # Total bandwidth to/from this memory (bytes/s)
61 system.physmem.bw_total::total 138226593 # Total bandwidth to/from this memory (bytes/s)
62 system.cpu_clk_domain.clock 500 # Clock period in ticks
63 system.cpu0.workload.num_syscalls 89 # Number of system calls
64 system.cpu0.numCycles 529681 # number of cpu cycles simulated
65 system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
66 system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
67 system.cpu0.committedInsts 158238 # Number of instructions committed
68 system.cpu0.committedOps 158238 # Number of ops (including micro ops) committed
69 system.cpu0.num_int_alu_accesses 108984 # Number of integer alu accesses
70 system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses
71 system.cpu0.num_func_calls 390 # number of times a function call or return occured
72 system.cpu0.num_conditional_control_insts 25976 # number of instructions that are conditional controls
73 system.cpu0.num_int_insts 108984 # number of integer instructions
74 system.cpu0.num_fp_insts 0 # number of float instructions
75 system.cpu0.num_int_register_reads 315110 # number of times the integer registers were read
76 system.cpu0.num_int_register_writes 110590 # number of times the integer registers were written
77 system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read
78 system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written
79 system.cpu0.num_mem_refs 73853 # number of memory refs
80 system.cpu0.num_load_insts 48895 # Number of load instructions
81 system.cpu0.num_store_insts 24958 # Number of store instructions
82 system.cpu0.num_idle_cycles 0.002000 # Number of idle cycles
83 system.cpu0.num_busy_cycles 529680.998000 # Number of busy cycles
84 system.cpu0.not_idle_fraction 1.000000 # Percentage of non-idle cycles
85 system.cpu0.idle_fraction 0.000000 # Percentage of idle cycles
86 system.cpu0.Branches 26841 # Number of branches fetched
87 system.cpu0.op_class::No_OpClass 23568 14.89% 14.89% # Class of executed instruction
88 system.cpu0.op_class::IntAlu 60795 38.40% 53.29% # Class of executed instruction
89 system.cpu0.op_class::IntMult 0 0.00% 53.29% # Class of executed instruction
90 system.cpu0.op_class::IntDiv 0 0.00% 53.29% # Class of executed instruction
91 system.cpu0.op_class::FloatAdd 0 0.00% 53.29% # Class of executed instruction
92 system.cpu0.op_class::FloatCmp 0 0.00% 53.29% # Class of executed instruction
93 system.cpu0.op_class::FloatCvt 0 0.00% 53.29% # Class of executed instruction
94 system.cpu0.op_class::FloatMult 0 0.00% 53.29% # Class of executed instruction
95 system.cpu0.op_class::FloatDiv 0 0.00% 53.29% # Class of executed instruction
96 system.cpu0.op_class::FloatSqrt 0 0.00% 53.29% # Class of executed instruction
97 system.cpu0.op_class::SimdAdd 0 0.00% 53.29% # Class of executed instruction
98 system.cpu0.op_class::SimdAddAcc 0 0.00% 53.29% # Class of executed instruction
99 system.cpu0.op_class::SimdAlu 0 0.00% 53.29% # Class of executed instruction
100 system.cpu0.op_class::SimdCmp 0 0.00% 53.29% # Class of executed instruction
101 system.cpu0.op_class::SimdCvt 0 0.00% 53.29% # Class of executed instruction
102 system.cpu0.op_class::SimdMisc 0 0.00% 53.29% # Class of executed instruction
103 system.cpu0.op_class::SimdMult 0 0.00% 53.29% # Class of executed instruction
104 system.cpu0.op_class::SimdMultAcc 0 0.00% 53.29% # Class of executed instruction
105 system.cpu0.op_class::SimdShift 0 0.00% 53.29% # Class of executed instruction
106 system.cpu0.op_class::SimdShiftAcc 0 0.00% 53.29% # Class of executed instruction
107 system.cpu0.op_class::SimdSqrt 0 0.00% 53.29% # Class of executed instruction
108 system.cpu0.op_class::SimdFloatAdd 0 0.00% 53.29% # Class of executed instruction
109 system.cpu0.op_class::SimdFloatAlu 0 0.00% 53.29% # Class of executed instruction
110 system.cpu0.op_class::SimdFloatCmp 0 0.00% 53.29% # Class of executed instruction
111 system.cpu0.op_class::SimdFloatCvt 0 0.00% 53.29% # Class of executed instruction
112 system.cpu0.op_class::SimdFloatDiv 0 0.00% 53.29% # Class of executed instruction
113 system.cpu0.op_class::SimdFloatMisc 0 0.00% 53.29% # Class of executed instruction
114 system.cpu0.op_class::SimdFloatMult 0 0.00% 53.29% # Class of executed instruction
115 system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 53.29% # Class of executed instruction
116 system.cpu0.op_class::SimdFloatSqrt 0 0.00% 53.29% # Class of executed instruction
117 system.cpu0.op_class::MemRead 48979 30.94% 84.23% # Class of executed instruction
118 system.cpu0.op_class::MemWrite 24958 15.77% 100.00% # Class of executed instruction
119 system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
120 system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
121 system.cpu0.op_class::total 158300 # Class of executed instruction
122 system.cpu0.dcache.tags.replacements 2 # number of replacements
123 system.cpu0.dcache.tags.tagsinuse 145.090849 # Cycle average of tags in use
124 system.cpu0.dcache.tags.total_refs 73323 # Total number of references to valid blocks.
125 system.cpu0.dcache.tags.sampled_refs 167 # Sample count of references to valid blocks.
126 system.cpu0.dcache.tags.avg_refs 439.059880 # Average number of references to valid blocks.
127 system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
128 system.cpu0.dcache.tags.occ_blocks::cpu0.data 145.090849 # Average occupied blocks per requestor
129 system.cpu0.dcache.tags.occ_percent::cpu0.data 0.283381 # Average percentage of cache occupancy
130 system.cpu0.dcache.tags.occ_percent::total 0.283381 # Average percentage of cache occupancy
131 system.cpu0.dcache.tags.occ_task_id_blocks::1024 165 # Occupied blocks per task id
132 system.cpu0.dcache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id
133 system.cpu0.dcache.tags.age_task_id_blocks_1024::2 149 # Occupied blocks per task id
134 system.cpu0.dcache.tags.occ_task_id_percent::1024 0.322266 # Percentage of cache occupancy per task id
135 system.cpu0.dcache.tags.tag_accesses 295643 # Number of tag accesses
136 system.cpu0.dcache.tags.data_accesses 295643 # Number of data accesses
137 system.cpu0.dcache.ReadReq_hits::cpu0.data 48717 # number of ReadReq hits
138 system.cpu0.dcache.ReadReq_hits::total 48717 # number of ReadReq hits
139 system.cpu0.dcache.WriteReq_hits::cpu0.data 24724 # number of WriteReq hits
140 system.cpu0.dcache.WriteReq_hits::total 24724 # number of WriteReq hits
141 system.cpu0.dcache.SwapReq_hits::cpu0.data 16 # number of SwapReq hits
142 system.cpu0.dcache.SwapReq_hits::total 16 # number of SwapReq hits
143 system.cpu0.dcache.demand_hits::cpu0.data 73441 # number of demand (read+write) hits
144 system.cpu0.dcache.demand_hits::total 73441 # number of demand (read+write) hits
145 system.cpu0.dcache.overall_hits::cpu0.data 73441 # number of overall hits
146 system.cpu0.dcache.overall_hits::total 73441 # number of overall hits
147 system.cpu0.dcache.ReadReq_misses::cpu0.data 168 # number of ReadReq misses
148 system.cpu0.dcache.ReadReq_misses::total 168 # number of ReadReq misses
149 system.cpu0.dcache.WriteReq_misses::cpu0.data 183 # number of WriteReq misses
150 system.cpu0.dcache.WriteReq_misses::total 183 # number of WriteReq misses
151 system.cpu0.dcache.SwapReq_misses::cpu0.data 26 # number of SwapReq misses
152 system.cpu0.dcache.SwapReq_misses::total 26 # number of SwapReq misses
153 system.cpu0.dcache.demand_misses::cpu0.data 351 # number of demand (read+write) misses
154 system.cpu0.dcache.demand_misses::total 351 # number of demand (read+write) misses
155 system.cpu0.dcache.overall_misses::cpu0.data 351 # number of overall misses
156 system.cpu0.dcache.overall_misses::total 351 # number of overall misses
157 system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5149000 # number of ReadReq miss cycles
158 system.cpu0.dcache.ReadReq_miss_latency::total 5149000 # number of ReadReq miss cycles
159 system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7867000 # number of WriteReq miss cycles
160 system.cpu0.dcache.WriteReq_miss_latency::total 7867000 # number of WriteReq miss cycles
161 system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 395000 # number of SwapReq miss cycles
162 system.cpu0.dcache.SwapReq_miss_latency::total 395000 # number of SwapReq miss cycles
163 system.cpu0.dcache.demand_miss_latency::cpu0.data 13016000 # number of demand (read+write) miss cycles
164 system.cpu0.dcache.demand_miss_latency::total 13016000 # number of demand (read+write) miss cycles
165 system.cpu0.dcache.overall_miss_latency::cpu0.data 13016000 # number of overall miss cycles
166 system.cpu0.dcache.overall_miss_latency::total 13016000 # number of overall miss cycles
167 system.cpu0.dcache.ReadReq_accesses::cpu0.data 48885 # number of ReadReq accesses(hits+misses)
168 system.cpu0.dcache.ReadReq_accesses::total 48885 # number of ReadReq accesses(hits+misses)
169 system.cpu0.dcache.WriteReq_accesses::cpu0.data 24907 # number of WriteReq accesses(hits+misses)
170 system.cpu0.dcache.WriteReq_accesses::total 24907 # number of WriteReq accesses(hits+misses)
171 system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses)
172 system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses)
173 system.cpu0.dcache.demand_accesses::cpu0.data 73792 # number of demand (read+write) accesses
174 system.cpu0.dcache.demand_accesses::total 73792 # number of demand (read+write) accesses
175 system.cpu0.dcache.overall_accesses::cpu0.data 73792 # number of overall (read+write) accesses
176 system.cpu0.dcache.overall_accesses::total 73792 # number of overall (read+write) accesses
177 system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.003437 # miss rate for ReadReq accesses
178 system.cpu0.dcache.ReadReq_miss_rate::total 0.003437 # miss rate for ReadReq accesses
179 system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007347 # miss rate for WriteReq accesses
180 system.cpu0.dcache.WriteReq_miss_rate::total 0.007347 # miss rate for WriteReq accesses
181 system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.619048 # miss rate for SwapReq accesses
182 system.cpu0.dcache.SwapReq_miss_rate::total 0.619048 # miss rate for SwapReq accesses
183 system.cpu0.dcache.demand_miss_rate::cpu0.data 0.004757 # miss rate for demand accesses
184 system.cpu0.dcache.demand_miss_rate::total 0.004757 # miss rate for demand accesses
185 system.cpu0.dcache.overall_miss_rate::cpu0.data 0.004757 # miss rate for overall accesses
186 system.cpu0.dcache.overall_miss_rate::total 0.004757 # miss rate for overall accesses
187 system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 30648.809524 # average ReadReq miss latency
188 system.cpu0.dcache.ReadReq_avg_miss_latency::total 30648.809524 # average ReadReq miss latency
189 system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 42989.071038 # average WriteReq miss latency
190 system.cpu0.dcache.WriteReq_avg_miss_latency::total 42989.071038 # average WriteReq miss latency
191 system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 15192.307692 # average SwapReq miss latency
192 system.cpu0.dcache.SwapReq_avg_miss_latency::total 15192.307692 # average SwapReq miss latency
193 system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 37082.621083 # average overall miss latency
194 system.cpu0.dcache.demand_avg_miss_latency::total 37082.621083 # average overall miss latency
195 system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 37082.621083 # average overall miss latency
196 system.cpu0.dcache.overall_avg_miss_latency::total 37082.621083 # average overall miss latency
197 system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
198 system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
199 system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
200 system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
201 system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
202 system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
203 system.cpu0.dcache.fast_writes 0 # number of fast writes performed
204 system.cpu0.dcache.cache_copies 0 # number of cache copies performed
205 system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks
206 system.cpu0.dcache.writebacks::total 1 # number of writebacks
207 system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 168 # number of ReadReq MSHR misses
208 system.cpu0.dcache.ReadReq_mshr_misses::total 168 # number of ReadReq MSHR misses
209 system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 183 # number of WriteReq MSHR misses
210 system.cpu0.dcache.WriteReq_mshr_misses::total 183 # number of WriteReq MSHR misses
211 system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 26 # number of SwapReq MSHR misses
212 system.cpu0.dcache.SwapReq_mshr_misses::total 26 # number of SwapReq MSHR misses
213 system.cpu0.dcache.demand_mshr_misses::cpu0.data 351 # number of demand (read+write) MSHR misses
214 system.cpu0.dcache.demand_mshr_misses::total 351 # number of demand (read+write) MSHR misses
215 system.cpu0.dcache.overall_mshr_misses::cpu0.data 351 # number of overall MSHR misses
216 system.cpu0.dcache.overall_mshr_misses::total 351 # number of overall MSHR misses
217 system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4981000 # number of ReadReq MSHR miss cycles
218 system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4981000 # number of ReadReq MSHR miss cycles
219 system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7684000 # number of WriteReq MSHR miss cycles
220 system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7684000 # number of WriteReq MSHR miss cycles
221 system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 369000 # number of SwapReq MSHR miss cycles
222 system.cpu0.dcache.SwapReq_mshr_miss_latency::total 369000 # number of SwapReq MSHR miss cycles
223 system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 12665000 # number of demand (read+write) MSHR miss cycles
224 system.cpu0.dcache.demand_mshr_miss_latency::total 12665000 # number of demand (read+write) MSHR miss cycles
225 system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 12665000 # number of overall MSHR miss cycles
226 system.cpu0.dcache.overall_mshr_miss_latency::total 12665000 # number of overall MSHR miss cycles
227 system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.003437 # mshr miss rate for ReadReq accesses
228 system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.003437 # mshr miss rate for ReadReq accesses
229 system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.007347 # mshr miss rate for WriteReq accesses
230 system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007347 # mshr miss rate for WriteReq accesses
231 system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.619048 # mshr miss rate for SwapReq accesses
232 system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.619048 # mshr miss rate for SwapReq accesses
233 system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.004757 # mshr miss rate for demand accesses
234 system.cpu0.dcache.demand_mshr_miss_rate::total 0.004757 # mshr miss rate for demand accesses
235 system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.004757 # mshr miss rate for overall accesses
236 system.cpu0.dcache.overall_mshr_miss_rate::total 0.004757 # mshr miss rate for overall accesses
237 system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 29648.809524 # average ReadReq mshr miss latency
238 system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 29648.809524 # average ReadReq mshr miss latency
239 system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 41989.071038 # average WriteReq mshr miss latency
240 system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 41989.071038 # average WriteReq mshr miss latency
241 system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 14192.307692 # average SwapReq mshr miss latency
242 system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 14192.307692 # average SwapReq mshr miss latency
243 system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 36082.621083 # average overall mshr miss latency
244 system.cpu0.dcache.demand_avg_mshr_miss_latency::total 36082.621083 # average overall mshr miss latency
245 system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 36082.621083 # average overall mshr miss latency
246 system.cpu0.dcache.overall_avg_mshr_miss_latency::total 36082.621083 # average overall mshr miss latency
247 system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
248 system.cpu0.icache.tags.replacements 215 # number of replacements
249 system.cpu0.icache.tags.tagsinuse 211.456411 # Cycle average of tags in use
250 system.cpu0.icache.tags.total_refs 157834 # Total number of references to valid blocks.
251 system.cpu0.icache.tags.sampled_refs 467 # Sample count of references to valid blocks.
252 system.cpu0.icache.tags.avg_refs 337.974304 # Average number of references to valid blocks.
253 system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
254 system.cpu0.icache.tags.occ_blocks::cpu0.inst 211.456411 # Average occupied blocks per requestor
255 system.cpu0.icache.tags.occ_percent::cpu0.inst 0.413001 # Average percentage of cache occupancy
256 system.cpu0.icache.tags.occ_percent::total 0.413001 # Average percentage of cache occupancy
257 system.cpu0.icache.tags.occ_task_id_blocks::1024 252 # Occupied blocks per task id
258 system.cpu0.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id
259 system.cpu0.icache.tags.age_task_id_blocks_1024::2 199 # Occupied blocks per task id
260 system.cpu0.icache.tags.occ_task_id_percent::1024 0.492188 # Percentage of cache occupancy per task id
261 system.cpu0.icache.tags.tag_accesses 158768 # Number of tag accesses
262 system.cpu0.icache.tags.data_accesses 158768 # Number of data accesses
263 system.cpu0.icache.ReadReq_hits::cpu0.inst 157834 # number of ReadReq hits
264 system.cpu0.icache.ReadReq_hits::total 157834 # number of ReadReq hits
265 system.cpu0.icache.demand_hits::cpu0.inst 157834 # number of demand (read+write) hits
266 system.cpu0.icache.demand_hits::total 157834 # number of demand (read+write) hits
267 system.cpu0.icache.overall_hits::cpu0.inst 157834 # number of overall hits
268 system.cpu0.icache.overall_hits::total 157834 # number of overall hits
269 system.cpu0.icache.ReadReq_misses::cpu0.inst 467 # number of ReadReq misses
270 system.cpu0.icache.ReadReq_misses::total 467 # number of ReadReq misses
271 system.cpu0.icache.demand_misses::cpu0.inst 467 # number of demand (read+write) misses
272 system.cpu0.icache.demand_misses::total 467 # number of demand (read+write) misses
273 system.cpu0.icache.overall_misses::cpu0.inst 467 # number of overall misses
274 system.cpu0.icache.overall_misses::total 467 # number of overall misses
275 system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 20139500 # number of ReadReq miss cycles
276 system.cpu0.icache.ReadReq_miss_latency::total 20139500 # number of ReadReq miss cycles
277 system.cpu0.icache.demand_miss_latency::cpu0.inst 20139500 # number of demand (read+write) miss cycles
278 system.cpu0.icache.demand_miss_latency::total 20139500 # number of demand (read+write) miss cycles
279 system.cpu0.icache.overall_miss_latency::cpu0.inst 20139500 # number of overall miss cycles
280 system.cpu0.icache.overall_miss_latency::total 20139500 # number of overall miss cycles
281 system.cpu0.icache.ReadReq_accesses::cpu0.inst 158301 # number of ReadReq accesses(hits+misses)
282 system.cpu0.icache.ReadReq_accesses::total 158301 # number of ReadReq accesses(hits+misses)
283 system.cpu0.icache.demand_accesses::cpu0.inst 158301 # number of demand (read+write) accesses
284 system.cpu0.icache.demand_accesses::total 158301 # number of demand (read+write) accesses
285 system.cpu0.icache.overall_accesses::cpu0.inst 158301 # number of overall (read+write) accesses
286 system.cpu0.icache.overall_accesses::total 158301 # number of overall (read+write) accesses
287 system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002950 # miss rate for ReadReq accesses
288 system.cpu0.icache.ReadReq_miss_rate::total 0.002950 # miss rate for ReadReq accesses
289 system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002950 # miss rate for demand accesses
290 system.cpu0.icache.demand_miss_rate::total 0.002950 # miss rate for demand accesses
291 system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002950 # miss rate for overall accesses
292 system.cpu0.icache.overall_miss_rate::total 0.002950 # miss rate for overall accesses
293 system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 43125.267666 # average ReadReq miss latency
294 system.cpu0.icache.ReadReq_avg_miss_latency::total 43125.267666 # average ReadReq miss latency
295 system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 43125.267666 # average overall miss latency
296 system.cpu0.icache.demand_avg_miss_latency::total 43125.267666 # average overall miss latency
297 system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 43125.267666 # average overall miss latency
298 system.cpu0.icache.overall_avg_miss_latency::total 43125.267666 # average overall miss latency
299 system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
300 system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
301 system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
302 system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
303 system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
304 system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
305 system.cpu0.icache.fast_writes 0 # number of fast writes performed
306 system.cpu0.icache.cache_copies 0 # number of cache copies performed
307 system.cpu0.icache.writebacks::writebacks 215 # number of writebacks
308 system.cpu0.icache.writebacks::total 215 # number of writebacks
309 system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 467 # number of ReadReq MSHR misses
310 system.cpu0.icache.ReadReq_mshr_misses::total 467 # number of ReadReq MSHR misses
311 system.cpu0.icache.demand_mshr_misses::cpu0.inst 467 # number of demand (read+write) MSHR misses
312 system.cpu0.icache.demand_mshr_misses::total 467 # number of demand (read+write) MSHR misses
313 system.cpu0.icache.overall_mshr_misses::cpu0.inst 467 # number of overall MSHR misses
314 system.cpu0.icache.overall_mshr_misses::total 467 # number of overall MSHR misses
315 system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 19672500 # number of ReadReq MSHR miss cycles
316 system.cpu0.icache.ReadReq_mshr_miss_latency::total 19672500 # number of ReadReq MSHR miss cycles
317 system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 19672500 # number of demand (read+write) MSHR miss cycles
318 system.cpu0.icache.demand_mshr_miss_latency::total 19672500 # number of demand (read+write) MSHR miss cycles
319 system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 19672500 # number of overall MSHR miss cycles
320 system.cpu0.icache.overall_mshr_miss_latency::total 19672500 # number of overall MSHR miss cycles
321 system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.002950 # mshr miss rate for ReadReq accesses
322 system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.002950 # mshr miss rate for ReadReq accesses
323 system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.002950 # mshr miss rate for demand accesses
324 system.cpu0.icache.demand_mshr_miss_rate::total 0.002950 # mshr miss rate for demand accesses
325 system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.002950 # mshr miss rate for overall accesses
326 system.cpu0.icache.overall_mshr_miss_rate::total 0.002950 # mshr miss rate for overall accesses
327 system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 42125.267666 # average ReadReq mshr miss latency
328 system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 42125.267666 # average ReadReq mshr miss latency
329 system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 42125.267666 # average overall mshr miss latency
330 system.cpu0.icache.demand_avg_mshr_miss_latency::total 42125.267666 # average overall mshr miss latency
331 system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 42125.267666 # average overall mshr miss latency
332 system.cpu0.icache.overall_avg_mshr_miss_latency::total 42125.267666 # average overall mshr miss latency
333 system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
334 system.cpu1.numCycles 529680 # number of cpu cycles simulated
335 system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
336 system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
337 system.cpu1.committedInsts 168829 # Number of instructions committed
338 system.cpu1.committedOps 168829 # Number of ops (including micro ops) committed
339 system.cpu1.num_int_alu_accesses 111193 # Number of integer alu accesses
340 system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses
341 system.cpu1.num_func_calls 637 # number of times a function call or return occured
342 system.cpu1.num_conditional_control_insts 32827 # number of instructions that are conditional controls
343 system.cpu1.num_int_insts 111193 # number of integer instructions
344 system.cpu1.num_fp_insts 0 # number of float instructions
345 system.cpu1.num_int_register_reads 275699 # number of times the integer registers were read
346 system.cpu1.num_int_register_writes 104505 # number of times the integer registers were written
347 system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read
348 system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written
349 system.cpu1.num_mem_refs 54535 # number of memory refs
350 system.cpu1.num_load_insts 41264 # Number of load instructions
351 system.cpu1.num_store_insts 13271 # Number of store instructions
352 system.cpu1.num_idle_cycles 73879.862241 # Number of idle cycles
353 system.cpu1.num_busy_cycles 455800.137759 # Number of busy cycles
354 system.cpu1.not_idle_fraction 0.860520 # Percentage of non-idle cycles
355 system.cpu1.idle_fraction 0.139480 # Percentage of idle cycles
356 system.cpu1.Branches 34479 # Number of branches fetched
357 system.cpu1.op_class::No_OpClass 25261 14.96% 14.96% # Class of executed instruction
358 system.cpu1.op_class::IntAlu 74858 44.33% 59.29% # Class of executed instruction
359 system.cpu1.op_class::IntMult 0 0.00% 59.29% # Class of executed instruction
360 system.cpu1.op_class::IntDiv 0 0.00% 59.29% # Class of executed instruction
361 system.cpu1.op_class::FloatAdd 0 0.00% 59.29% # Class of executed instruction
362 system.cpu1.op_class::FloatCmp 0 0.00% 59.29% # Class of executed instruction
363 system.cpu1.op_class::FloatCvt 0 0.00% 59.29% # Class of executed instruction
364 system.cpu1.op_class::FloatMult 0 0.00% 59.29% # Class of executed instruction
365 system.cpu1.op_class::FloatDiv 0 0.00% 59.29% # Class of executed instruction
366 system.cpu1.op_class::FloatSqrt 0 0.00% 59.29% # Class of executed instruction
367 system.cpu1.op_class::SimdAdd 0 0.00% 59.29% # Class of executed instruction
368 system.cpu1.op_class::SimdAddAcc 0 0.00% 59.29% # Class of executed instruction
369 system.cpu1.op_class::SimdAlu 0 0.00% 59.29% # Class of executed instruction
370 system.cpu1.op_class::SimdCmp 0 0.00% 59.29% # Class of executed instruction
371 system.cpu1.op_class::SimdCvt 0 0.00% 59.29% # Class of executed instruction
372 system.cpu1.op_class::SimdMisc 0 0.00% 59.29% # Class of executed instruction
373 system.cpu1.op_class::SimdMult 0 0.00% 59.29% # Class of executed instruction
374 system.cpu1.op_class::SimdMultAcc 0 0.00% 59.29% # Class of executed instruction
375 system.cpu1.op_class::SimdShift 0 0.00% 59.29% # Class of executed instruction
376 system.cpu1.op_class::SimdShiftAcc 0 0.00% 59.29% # Class of executed instruction
377 system.cpu1.op_class::SimdSqrt 0 0.00% 59.29% # Class of executed instruction
378 system.cpu1.op_class::SimdFloatAdd 0 0.00% 59.29% # Class of executed instruction
379 system.cpu1.op_class::SimdFloatAlu 0 0.00% 59.29% # Class of executed instruction
380 system.cpu1.op_class::SimdFloatCmp 0 0.00% 59.29% # Class of executed instruction
381 system.cpu1.op_class::SimdFloatCvt 0 0.00% 59.29% # Class of executed instruction
382 system.cpu1.op_class::SimdFloatDiv 0 0.00% 59.29% # Class of executed instruction
383 system.cpu1.op_class::SimdFloatMisc 0 0.00% 59.29% # Class of executed instruction
384 system.cpu1.op_class::SimdFloatMult 0 0.00% 59.29% # Class of executed instruction
385 system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 59.29% # Class of executed instruction
386 system.cpu1.op_class::SimdFloatSqrt 0 0.00% 59.29% # Class of executed instruction
387 system.cpu1.op_class::MemRead 55471 32.85% 92.14% # Class of executed instruction
388 system.cpu1.op_class::MemWrite 13271 7.86% 100.00% # Class of executed instruction
389 system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
390 system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
391 system.cpu1.op_class::total 168861 # Class of executed instruction
392 system.cpu1.dcache.tags.replacements 0 # number of replacements
393 system.cpu1.dcache.tags.tagsinuse 26.495164 # Cycle average of tags in use
394 system.cpu1.dcache.tags.total_refs 28944 # Total number of references to valid blocks.
395 system.cpu1.dcache.tags.sampled_refs 30 # Sample count of references to valid blocks.
396 system.cpu1.dcache.tags.avg_refs 964.800000 # Average number of references to valid blocks.
397 system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
398 system.cpu1.dcache.tags.occ_blocks::cpu1.data 26.495164 # Average occupied blocks per requestor
399 system.cpu1.dcache.tags.occ_percent::cpu1.data 0.051748 # Average percentage of cache occupancy
400 system.cpu1.dcache.tags.occ_percent::total 0.051748 # Average percentage of cache occupancy
401 system.cpu1.dcache.tags.occ_task_id_blocks::1024 30 # Occupied blocks per task id
402 system.cpu1.dcache.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id
403 system.cpu1.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id
404 system.cpu1.dcache.tags.occ_task_id_percent::1024 0.058594 # Percentage of cache occupancy per task id
405 system.cpu1.dcache.tags.tag_accesses 218364 # Number of tag accesses
406 system.cpu1.dcache.tags.data_accesses 218364 # Number of data accesses
407 system.cpu1.dcache.ReadReq_hits::cpu1.data 41094 # number of ReadReq hits
408 system.cpu1.dcache.ReadReq_hits::total 41094 # number of ReadReq hits
409 system.cpu1.dcache.WriteReq_hits::cpu1.data 13094 # number of WriteReq hits
410 system.cpu1.dcache.WriteReq_hits::total 13094 # number of WriteReq hits
411 system.cpu1.dcache.SwapReq_hits::cpu1.data 13 # number of SwapReq hits
412 system.cpu1.dcache.SwapReq_hits::total 13 # number of SwapReq hits
413 system.cpu1.dcache.demand_hits::cpu1.data 54188 # number of demand (read+write) hits
414 system.cpu1.dcache.demand_hits::total 54188 # number of demand (read+write) hits
415 system.cpu1.dcache.overall_hits::cpu1.data 54188 # number of overall hits
416 system.cpu1.dcache.overall_hits::total 54188 # number of overall hits
417 system.cpu1.dcache.ReadReq_misses::cpu1.data 163 # number of ReadReq misses
418 system.cpu1.dcache.ReadReq_misses::total 163 # number of ReadReq misses
419 system.cpu1.dcache.WriteReq_misses::cpu1.data 107 # number of WriteReq misses
420 system.cpu1.dcache.WriteReq_misses::total 107 # number of WriteReq misses
421 system.cpu1.dcache.SwapReq_misses::cpu1.data 55 # number of SwapReq misses
422 system.cpu1.dcache.SwapReq_misses::total 55 # number of SwapReq misses
423 system.cpu1.dcache.demand_misses::cpu1.data 270 # number of demand (read+write) misses
424 system.cpu1.dcache.demand_misses::total 270 # number of demand (read+write) misses
425 system.cpu1.dcache.overall_misses::cpu1.data 270 # number of overall misses
426 system.cpu1.dcache.overall_misses::total 270 # number of overall misses
427 system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2920000 # number of ReadReq miss cycles
428 system.cpu1.dcache.ReadReq_miss_latency::total 2920000 # number of ReadReq miss cycles
429 system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2149500 # number of WriteReq miss cycles
430 system.cpu1.dcache.WriteReq_miss_latency::total 2149500 # number of WriteReq miss cycles
431 system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 245500 # number of SwapReq miss cycles
432 system.cpu1.dcache.SwapReq_miss_latency::total 245500 # number of SwapReq miss cycles
433 system.cpu1.dcache.demand_miss_latency::cpu1.data 5069500 # number of demand (read+write) miss cycles
434 system.cpu1.dcache.demand_miss_latency::total 5069500 # number of demand (read+write) miss cycles
435 system.cpu1.dcache.overall_miss_latency::cpu1.data 5069500 # number of overall miss cycles
436 system.cpu1.dcache.overall_miss_latency::total 5069500 # number of overall miss cycles
437 system.cpu1.dcache.ReadReq_accesses::cpu1.data 41257 # number of ReadReq accesses(hits+misses)
438 system.cpu1.dcache.ReadReq_accesses::total 41257 # number of ReadReq accesses(hits+misses)
439 system.cpu1.dcache.WriteReq_accesses::cpu1.data 13201 # number of WriteReq accesses(hits+misses)
440 system.cpu1.dcache.WriteReq_accesses::total 13201 # number of WriteReq accesses(hits+misses)
441 system.cpu1.dcache.SwapReq_accesses::cpu1.data 68 # number of SwapReq accesses(hits+misses)
442 system.cpu1.dcache.SwapReq_accesses::total 68 # number of SwapReq accesses(hits+misses)
443 system.cpu1.dcache.demand_accesses::cpu1.data 54458 # number of demand (read+write) accesses
444 system.cpu1.dcache.demand_accesses::total 54458 # number of demand (read+write) accesses
445 system.cpu1.dcache.overall_accesses::cpu1.data 54458 # number of overall (read+write) accesses
446 system.cpu1.dcache.overall_accesses::total 54458 # number of overall (read+write) accesses
447 system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.003951 # miss rate for ReadReq accesses
448 system.cpu1.dcache.ReadReq_miss_rate::total 0.003951 # miss rate for ReadReq accesses
449 system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.008105 # miss rate for WriteReq accesses
450 system.cpu1.dcache.WriteReq_miss_rate::total 0.008105 # miss rate for WriteReq accesses
451 system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.808824 # miss rate for SwapReq accesses
452 system.cpu1.dcache.SwapReq_miss_rate::total 0.808824 # miss rate for SwapReq accesses
453 system.cpu1.dcache.demand_miss_rate::cpu1.data 0.004958 # miss rate for demand accesses
454 system.cpu1.dcache.demand_miss_rate::total 0.004958 # miss rate for demand accesses
455 system.cpu1.dcache.overall_miss_rate::cpu1.data 0.004958 # miss rate for overall accesses
456 system.cpu1.dcache.overall_miss_rate::total 0.004958 # miss rate for overall accesses
457 system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 17914.110429 # average ReadReq miss latency
458 system.cpu1.dcache.ReadReq_avg_miss_latency::total 17914.110429 # average ReadReq miss latency
459 system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20088.785047 # average WriteReq miss latency
460 system.cpu1.dcache.WriteReq_avg_miss_latency::total 20088.785047 # average WriteReq miss latency
461 system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 4463.636364 # average SwapReq miss latency
462 system.cpu1.dcache.SwapReq_avg_miss_latency::total 4463.636364 # average SwapReq miss latency
463 system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18775.925926 # average overall miss latency
464 system.cpu1.dcache.demand_avg_miss_latency::total 18775.925926 # average overall miss latency
465 system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18775.925926 # average overall miss latency
466 system.cpu1.dcache.overall_avg_miss_latency::total 18775.925926 # average overall miss latency
467 system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
468 system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
469 system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
470 system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
471 system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
472 system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
473 system.cpu1.dcache.fast_writes 0 # number of fast writes performed
474 system.cpu1.dcache.cache_copies 0 # number of cache copies performed
475 system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 163 # number of ReadReq MSHR misses
476 system.cpu1.dcache.ReadReq_mshr_misses::total 163 # number of ReadReq MSHR misses
477 system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 107 # number of WriteReq MSHR misses
478 system.cpu1.dcache.WriteReq_mshr_misses::total 107 # number of WriteReq MSHR misses
479 system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 55 # number of SwapReq MSHR misses
480 system.cpu1.dcache.SwapReq_mshr_misses::total 55 # number of SwapReq MSHR misses
481 system.cpu1.dcache.demand_mshr_misses::cpu1.data 270 # number of demand (read+write) MSHR misses
482 system.cpu1.dcache.demand_mshr_misses::total 270 # number of demand (read+write) MSHR misses
483 system.cpu1.dcache.overall_mshr_misses::cpu1.data 270 # number of overall MSHR misses
484 system.cpu1.dcache.overall_mshr_misses::total 270 # number of overall MSHR misses
485 system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2757000 # number of ReadReq MSHR miss cycles
486 system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2757000 # number of ReadReq MSHR miss cycles
487 system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2042500 # number of WriteReq MSHR miss cycles
488 system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2042500 # number of WriteReq MSHR miss cycles
489 system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 190500 # number of SwapReq MSHR miss cycles
490 system.cpu1.dcache.SwapReq_mshr_miss_latency::total 190500 # number of SwapReq MSHR miss cycles
491 system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4799500 # number of demand (read+write) MSHR miss cycles
492 system.cpu1.dcache.demand_mshr_miss_latency::total 4799500 # number of demand (read+write) MSHR miss cycles
493 system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4799500 # number of overall MSHR miss cycles
494 system.cpu1.dcache.overall_mshr_miss_latency::total 4799500 # number of overall MSHR miss cycles
495 system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003951 # mshr miss rate for ReadReq accesses
496 system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003951 # mshr miss rate for ReadReq accesses
497 system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.008105 # mshr miss rate for WriteReq accesses
498 system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.008105 # mshr miss rate for WriteReq accesses
499 system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.808824 # mshr miss rate for SwapReq accesses
500 system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.808824 # mshr miss rate for SwapReq accesses
501 system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.004958 # mshr miss rate for demand accesses
502 system.cpu1.dcache.demand_mshr_miss_rate::total 0.004958 # mshr miss rate for demand accesses
503 system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.004958 # mshr miss rate for overall accesses
504 system.cpu1.dcache.overall_mshr_miss_rate::total 0.004958 # mshr miss rate for overall accesses
505 system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 16914.110429 # average ReadReq mshr miss latency
506 system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 16914.110429 # average ReadReq mshr miss latency
507 system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 19088.785047 # average WriteReq mshr miss latency
508 system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 19088.785047 # average WriteReq mshr miss latency
509 system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 3463.636364 # average SwapReq mshr miss latency
510 system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 3463.636364 # average SwapReq mshr miss latency
511 system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17775.925926 # average overall mshr miss latency
512 system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17775.925926 # average overall mshr miss latency
513 system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17775.925926 # average overall mshr miss latency
514 system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17775.925926 # average overall mshr miss latency
515 system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
516 system.cpu1.icache.tags.replacements 280 # number of replacements
517 system.cpu1.icache.tags.tagsinuse 67.000483 # Cycle average of tags in use
518 system.cpu1.icache.tags.total_refs 168496 # Total number of references to valid blocks.
519 system.cpu1.icache.tags.sampled_refs 366 # Sample count of references to valid blocks.
520 system.cpu1.icache.tags.avg_refs 460.371585 # Average number of references to valid blocks.
521 system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
522 system.cpu1.icache.tags.occ_blocks::cpu1.inst 67.000483 # Average occupied blocks per requestor
523 system.cpu1.icache.tags.occ_percent::cpu1.inst 0.130860 # Average percentage of cache occupancy
524 system.cpu1.icache.tags.occ_percent::total 0.130860 # Average percentage of cache occupancy
525 system.cpu1.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id
526 system.cpu1.icache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id
527 system.cpu1.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id
528 system.cpu1.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id
529 system.cpu1.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id
530 system.cpu1.icache.tags.tag_accesses 169228 # Number of tag accesses
531 system.cpu1.icache.tags.data_accesses 169228 # Number of data accesses
532 system.cpu1.icache.ReadReq_hits::cpu1.inst 168496 # number of ReadReq hits
533 system.cpu1.icache.ReadReq_hits::total 168496 # number of ReadReq hits
534 system.cpu1.icache.demand_hits::cpu1.inst 168496 # number of demand (read+write) hits
535 system.cpu1.icache.demand_hits::total 168496 # number of demand (read+write) hits
536 system.cpu1.icache.overall_hits::cpu1.inst 168496 # number of overall hits
537 system.cpu1.icache.overall_hits::total 168496 # number of overall hits
538 system.cpu1.icache.ReadReq_misses::cpu1.inst 366 # number of ReadReq misses
539 system.cpu1.icache.ReadReq_misses::total 366 # number of ReadReq misses
540 system.cpu1.icache.demand_misses::cpu1.inst 366 # number of demand (read+write) misses
541 system.cpu1.icache.demand_misses::total 366 # number of demand (read+write) misses
542 system.cpu1.icache.overall_misses::cpu1.inst 366 # number of overall misses
543 system.cpu1.icache.overall_misses::total 366 # number of overall misses
544 system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5681500 # number of ReadReq miss cycles
545 system.cpu1.icache.ReadReq_miss_latency::total 5681500 # number of ReadReq miss cycles
546 system.cpu1.icache.demand_miss_latency::cpu1.inst 5681500 # number of demand (read+write) miss cycles
547 system.cpu1.icache.demand_miss_latency::total 5681500 # number of demand (read+write) miss cycles
548 system.cpu1.icache.overall_miss_latency::cpu1.inst 5681500 # number of overall miss cycles
549 system.cpu1.icache.overall_miss_latency::total 5681500 # number of overall miss cycles
550 system.cpu1.icache.ReadReq_accesses::cpu1.inst 168862 # number of ReadReq accesses(hits+misses)
551 system.cpu1.icache.ReadReq_accesses::total 168862 # number of ReadReq accesses(hits+misses)
552 system.cpu1.icache.demand_accesses::cpu1.inst 168862 # number of demand (read+write) accesses
553 system.cpu1.icache.demand_accesses::total 168862 # number of demand (read+write) accesses
554 system.cpu1.icache.overall_accesses::cpu1.inst 168862 # number of overall (read+write) accesses
555 system.cpu1.icache.overall_accesses::total 168862 # number of overall (read+write) accesses
556 system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002167 # miss rate for ReadReq accesses
557 system.cpu1.icache.ReadReq_miss_rate::total 0.002167 # miss rate for ReadReq accesses
558 system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002167 # miss rate for demand accesses
559 system.cpu1.icache.demand_miss_rate::total 0.002167 # miss rate for demand accesses
560 system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002167 # miss rate for overall accesses
561 system.cpu1.icache.overall_miss_rate::total 0.002167 # miss rate for overall accesses
562 system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15523.224044 # average ReadReq miss latency
563 system.cpu1.icache.ReadReq_avg_miss_latency::total 15523.224044 # average ReadReq miss latency
564 system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15523.224044 # average overall miss latency
565 system.cpu1.icache.demand_avg_miss_latency::total 15523.224044 # average overall miss latency
566 system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15523.224044 # average overall miss latency
567 system.cpu1.icache.overall_avg_miss_latency::total 15523.224044 # average overall miss latency
568 system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
569 system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
570 system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
571 system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
572 system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
573 system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
574 system.cpu1.icache.fast_writes 0 # number of fast writes performed
575 system.cpu1.icache.cache_copies 0 # number of cache copies performed
576 system.cpu1.icache.writebacks::writebacks 280 # number of writebacks
577 system.cpu1.icache.writebacks::total 280 # number of writebacks
578 system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 366 # number of ReadReq MSHR misses
579 system.cpu1.icache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses
580 system.cpu1.icache.demand_mshr_misses::cpu1.inst 366 # number of demand (read+write) MSHR misses
581 system.cpu1.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses
582 system.cpu1.icache.overall_mshr_misses::cpu1.inst 366 # number of overall MSHR misses
583 system.cpu1.icache.overall_mshr_misses::total 366 # number of overall MSHR misses
584 system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5315500 # number of ReadReq MSHR miss cycles
585 system.cpu1.icache.ReadReq_mshr_miss_latency::total 5315500 # number of ReadReq MSHR miss cycles
586 system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5315500 # number of demand (read+write) MSHR miss cycles
587 system.cpu1.icache.demand_mshr_miss_latency::total 5315500 # number of demand (read+write) MSHR miss cycles
588 system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5315500 # number of overall MSHR miss cycles
589 system.cpu1.icache.overall_mshr_miss_latency::total 5315500 # number of overall MSHR miss cycles
590 system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.002167 # mshr miss rate for ReadReq accesses
591 system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.002167 # mshr miss rate for ReadReq accesses
592 system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.002167 # mshr miss rate for demand accesses
593 system.cpu1.icache.demand_mshr_miss_rate::total 0.002167 # mshr miss rate for demand accesses
594 system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.002167 # mshr miss rate for overall accesses
595 system.cpu1.icache.overall_mshr_miss_rate::total 0.002167 # mshr miss rate for overall accesses
596 system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 14523.224044 # average ReadReq mshr miss latency
597 system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 14523.224044 # average ReadReq mshr miss latency
598 system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 14523.224044 # average overall mshr miss latency
599 system.cpu1.icache.demand_avg_mshr_miss_latency::total 14523.224044 # average overall mshr miss latency
600 system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 14523.224044 # average overall mshr miss latency
601 system.cpu1.icache.overall_avg_mshr_miss_latency::total 14523.224044 # average overall mshr miss latency
602 system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
603 system.cpu2.numCycles 529681 # number of cpu cycles simulated
604 system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
605 system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
606 system.cpu2.committedInsts 165415 # Number of instructions committed
607 system.cpu2.committedOps 165415 # Number of ops (including micro ops) committed
608 system.cpu2.num_int_alu_accesses 110386 # Number of integer alu accesses
609 system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses
610 system.cpu2.num_func_calls 637 # number of times a function call or return occured
611 system.cpu2.num_conditional_control_insts 31522 # number of instructions that are conditional controls
612 system.cpu2.num_int_insts 110386 # number of integer instructions
613 system.cpu2.num_fp_insts 0 # number of float instructions
614 system.cpu2.num_int_register_reads 277687 # number of times the integer registers were read
615 system.cpu2.num_int_register_writes 105904 # number of times the integer registers were written
616 system.cpu2.num_fp_register_reads 0 # number of times the floating registers were read
617 system.cpu2.num_fp_register_writes 0 # number of times the floating registers were written
618 system.cpu2.num_mem_refs 55033 # number of memory refs
619 system.cpu2.num_load_insts 40858 # Number of load instructions
620 system.cpu2.num_store_insts 14175 # Number of store instructions
621 system.cpu2.num_idle_cycles 74150.001720 # Number of idle cycles
622 system.cpu2.num_busy_cycles 455530.998280 # Number of busy cycles
623 system.cpu2.not_idle_fraction 0.860010 # Percentage of non-idle cycles
624 system.cpu2.idle_fraction 0.139990 # Percentage of idle cycles
625 system.cpu2.Branches 33177 # Number of branches fetched
626 system.cpu2.op_class::No_OpClass 23956 14.48% 14.48% # Class of executed instruction
627 system.cpu2.op_class::IntAlu 74457 45.00% 59.48% # Class of executed instruction
628 system.cpu2.op_class::IntMult 0 0.00% 59.48% # Class of executed instruction
629 system.cpu2.op_class::IntDiv 0 0.00% 59.48% # Class of executed instruction
630 system.cpu2.op_class::FloatAdd 0 0.00% 59.48% # Class of executed instruction
631 system.cpu2.op_class::FloatCmp 0 0.00% 59.48% # Class of executed instruction
632 system.cpu2.op_class::FloatCvt 0 0.00% 59.48% # Class of executed instruction
633 system.cpu2.op_class::FloatMult 0 0.00% 59.48% # Class of executed instruction
634 system.cpu2.op_class::FloatDiv 0 0.00% 59.48% # Class of executed instruction
635 system.cpu2.op_class::FloatSqrt 0 0.00% 59.48% # Class of executed instruction
636 system.cpu2.op_class::SimdAdd 0 0.00% 59.48% # Class of executed instruction
637 system.cpu2.op_class::SimdAddAcc 0 0.00% 59.48% # Class of executed instruction
638 system.cpu2.op_class::SimdAlu 0 0.00% 59.48% # Class of executed instruction
639 system.cpu2.op_class::SimdCmp 0 0.00% 59.48% # Class of executed instruction
640 system.cpu2.op_class::SimdCvt 0 0.00% 59.48% # Class of executed instruction
641 system.cpu2.op_class::SimdMisc 0 0.00% 59.48% # Class of executed instruction
642 system.cpu2.op_class::SimdMult 0 0.00% 59.48% # Class of executed instruction
643 system.cpu2.op_class::SimdMultAcc 0 0.00% 59.48% # Class of executed instruction
644 system.cpu2.op_class::SimdShift 0 0.00% 59.48% # Class of executed instruction
645 system.cpu2.op_class::SimdShiftAcc 0 0.00% 59.48% # Class of executed instruction
646 system.cpu2.op_class::SimdSqrt 0 0.00% 59.48% # Class of executed instruction
647 system.cpu2.op_class::SimdFloatAdd 0 0.00% 59.48% # Class of executed instruction
648 system.cpu2.op_class::SimdFloatAlu 0 0.00% 59.48% # Class of executed instruction
649 system.cpu2.op_class::SimdFloatCmp 0 0.00% 59.48% # Class of executed instruction
650 system.cpu2.op_class::SimdFloatCvt 0 0.00% 59.48% # Class of executed instruction
651 system.cpu2.op_class::SimdFloatDiv 0 0.00% 59.48% # Class of executed instruction
652 system.cpu2.op_class::SimdFloatMisc 0 0.00% 59.48% # Class of executed instruction
653 system.cpu2.op_class::SimdFloatMult 0 0.00% 59.48% # Class of executed instruction
654 system.cpu2.op_class::SimdFloatMultAcc 0 0.00% 59.48% # Class of executed instruction
655 system.cpu2.op_class::SimdFloatSqrt 0 0.00% 59.48% # Class of executed instruction
656 system.cpu2.op_class::MemRead 52859 31.95% 91.43% # Class of executed instruction
657 system.cpu2.op_class::MemWrite 14175 8.57% 100.00% # Class of executed instruction
658 system.cpu2.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
659 system.cpu2.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
660 system.cpu2.op_class::total 165447 # Class of executed instruction
661 system.cpu2.dcache.tags.replacements 0 # number of replacements
662 system.cpu2.dcache.tags.tagsinuse 27.486829 # Cycle average of tags in use
663 system.cpu2.dcache.tags.total_refs 30625 # Total number of references to valid blocks.
664 system.cpu2.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks.
665 system.cpu2.dcache.tags.avg_refs 1056.034483 # Average number of references to valid blocks.
666 system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
667 system.cpu2.dcache.tags.occ_blocks::cpu2.data 27.486829 # Average occupied blocks per requestor
668 system.cpu2.dcache.tags.occ_percent::cpu2.data 0.053685 # Average percentage of cache occupancy
669 system.cpu2.dcache.tags.occ_percent::total 0.053685 # Average percentage of cache occupancy
670 system.cpu2.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id
671 system.cpu2.dcache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id
672 system.cpu2.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id
673 system.cpu2.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id
674 system.cpu2.dcache.tags.tag_accesses 220352 # Number of tag accesses
675 system.cpu2.dcache.tags.data_accesses 220352 # Number of data accesses
676 system.cpu2.dcache.ReadReq_hits::cpu2.data 40687 # number of ReadReq hits
677 system.cpu2.dcache.ReadReq_hits::total 40687 # number of ReadReq hits
678 system.cpu2.dcache.WriteReq_hits::cpu2.data 13994 # number of WriteReq hits
679 system.cpu2.dcache.WriteReq_hits::total 13994 # number of WriteReq hits
680 system.cpu2.dcache.SwapReq_hits::cpu2.data 13 # number of SwapReq hits
681 system.cpu2.dcache.SwapReq_hits::total 13 # number of SwapReq hits
682 system.cpu2.dcache.demand_hits::cpu2.data 54681 # number of demand (read+write) hits
683 system.cpu2.dcache.demand_hits::total 54681 # number of demand (read+write) hits
684 system.cpu2.dcache.overall_hits::cpu2.data 54681 # number of overall hits
685 system.cpu2.dcache.overall_hits::total 54681 # number of overall hits
686 system.cpu2.dcache.ReadReq_misses::cpu2.data 163 # number of ReadReq misses
687 system.cpu2.dcache.ReadReq_misses::total 163 # number of ReadReq misses
688 system.cpu2.dcache.WriteReq_misses::cpu2.data 108 # number of WriteReq misses
689 system.cpu2.dcache.WriteReq_misses::total 108 # number of WriteReq misses
690 system.cpu2.dcache.SwapReq_misses::cpu2.data 58 # number of SwapReq misses
691 system.cpu2.dcache.SwapReq_misses::total 58 # number of SwapReq misses
692 system.cpu2.dcache.demand_misses::cpu2.data 271 # number of demand (read+write) misses
693 system.cpu2.dcache.demand_misses::total 271 # number of demand (read+write) misses
694 system.cpu2.dcache.overall_misses::cpu2.data 271 # number of overall misses
695 system.cpu2.dcache.overall_misses::total 271 # number of overall misses
696 system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 3093500 # number of ReadReq miss cycles
697 system.cpu2.dcache.ReadReq_miss_latency::total 3093500 # number of ReadReq miss cycles
698 system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2328000 # number of WriteReq miss cycles
699 system.cpu2.dcache.WriteReq_miss_latency::total 2328000 # number of WriteReq miss cycles
700 system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 260500 # number of SwapReq miss cycles
701 system.cpu2.dcache.SwapReq_miss_latency::total 260500 # number of SwapReq miss cycles
702 system.cpu2.dcache.demand_miss_latency::cpu2.data 5421500 # number of demand (read+write) miss cycles
703 system.cpu2.dcache.demand_miss_latency::total 5421500 # number of demand (read+write) miss cycles
704 system.cpu2.dcache.overall_miss_latency::cpu2.data 5421500 # number of overall miss cycles
705 system.cpu2.dcache.overall_miss_latency::total 5421500 # number of overall miss cycles
706 system.cpu2.dcache.ReadReq_accesses::cpu2.data 40850 # number of ReadReq accesses(hits+misses)
707 system.cpu2.dcache.ReadReq_accesses::total 40850 # number of ReadReq accesses(hits+misses)
708 system.cpu2.dcache.WriteReq_accesses::cpu2.data 14102 # number of WriteReq accesses(hits+misses)
709 system.cpu2.dcache.WriteReq_accesses::total 14102 # number of WriteReq accesses(hits+misses)
710 system.cpu2.dcache.SwapReq_accesses::cpu2.data 71 # number of SwapReq accesses(hits+misses)
711 system.cpu2.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses)
712 system.cpu2.dcache.demand_accesses::cpu2.data 54952 # number of demand (read+write) accesses
713 system.cpu2.dcache.demand_accesses::total 54952 # number of demand (read+write) accesses
714 system.cpu2.dcache.overall_accesses::cpu2.data 54952 # number of overall (read+write) accesses
715 system.cpu2.dcache.overall_accesses::total 54952 # number of overall (read+write) accesses
716 system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003990 # miss rate for ReadReq accesses
717 system.cpu2.dcache.ReadReq_miss_rate::total 0.003990 # miss rate for ReadReq accesses
718 system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.007658 # miss rate for WriteReq accesses
719 system.cpu2.dcache.WriteReq_miss_rate::total 0.007658 # miss rate for WriteReq accesses
720 system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.816901 # miss rate for SwapReq accesses
721 system.cpu2.dcache.SwapReq_miss_rate::total 0.816901 # miss rate for SwapReq accesses
722 system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004932 # miss rate for demand accesses
723 system.cpu2.dcache.demand_miss_rate::total 0.004932 # miss rate for demand accesses
724 system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004932 # miss rate for overall accesses
725 system.cpu2.dcache.overall_miss_rate::total 0.004932 # miss rate for overall accesses
726 system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 18978.527607 # average ReadReq miss latency
727 system.cpu2.dcache.ReadReq_avg_miss_latency::total 18978.527607 # average ReadReq miss latency
728 system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 21555.555556 # average WriteReq miss latency
729 system.cpu2.dcache.WriteReq_avg_miss_latency::total 21555.555556 # average WriteReq miss latency
730 system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 4491.379310 # average SwapReq miss latency
731 system.cpu2.dcache.SwapReq_avg_miss_latency::total 4491.379310 # average SwapReq miss latency
732 system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 20005.535055 # average overall miss latency
733 system.cpu2.dcache.demand_avg_miss_latency::total 20005.535055 # average overall miss latency
734 system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 20005.535055 # average overall miss latency
735 system.cpu2.dcache.overall_avg_miss_latency::total 20005.535055 # average overall miss latency
736 system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
737 system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
738 system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
739 system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked
740 system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
741 system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
742 system.cpu2.dcache.fast_writes 0 # number of fast writes performed
743 system.cpu2.dcache.cache_copies 0 # number of cache copies performed
744 system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 163 # number of ReadReq MSHR misses
745 system.cpu2.dcache.ReadReq_mshr_misses::total 163 # number of ReadReq MSHR misses
746 system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 108 # number of WriteReq MSHR misses
747 system.cpu2.dcache.WriteReq_mshr_misses::total 108 # number of WriteReq MSHR misses
748 system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 58 # number of SwapReq MSHR misses
749 system.cpu2.dcache.SwapReq_mshr_misses::total 58 # number of SwapReq MSHR misses
750 system.cpu2.dcache.demand_mshr_misses::cpu2.data 271 # number of demand (read+write) MSHR misses
751 system.cpu2.dcache.demand_mshr_misses::total 271 # number of demand (read+write) MSHR misses
752 system.cpu2.dcache.overall_mshr_misses::cpu2.data 271 # number of overall MSHR misses
753 system.cpu2.dcache.overall_mshr_misses::total 271 # number of overall MSHR misses
754 system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 2930500 # number of ReadReq MSHR miss cycles
755 system.cpu2.dcache.ReadReq_mshr_miss_latency::total 2930500 # number of ReadReq MSHR miss cycles
756 system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 2220000 # number of WriteReq MSHR miss cycles
757 system.cpu2.dcache.WriteReq_mshr_miss_latency::total 2220000 # number of WriteReq MSHR miss cycles
758 system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 202500 # number of SwapReq MSHR miss cycles
759 system.cpu2.dcache.SwapReq_mshr_miss_latency::total 202500 # number of SwapReq MSHR miss cycles
760 system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 5150500 # number of demand (read+write) MSHR miss cycles
761 system.cpu2.dcache.demand_mshr_miss_latency::total 5150500 # number of demand (read+write) MSHR miss cycles
762 system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 5150500 # number of overall MSHR miss cycles
763 system.cpu2.dcache.overall_mshr_miss_latency::total 5150500 # number of overall MSHR miss cycles
764 system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003990 # mshr miss rate for ReadReq accesses
765 system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003990 # mshr miss rate for ReadReq accesses
766 system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.007658 # mshr miss rate for WriteReq accesses
767 system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.007658 # mshr miss rate for WriteReq accesses
768 system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.816901 # mshr miss rate for SwapReq accesses
769 system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.816901 # mshr miss rate for SwapReq accesses
770 system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004932 # mshr miss rate for demand accesses
771 system.cpu2.dcache.demand_mshr_miss_rate::total 0.004932 # mshr miss rate for demand accesses
772 system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004932 # mshr miss rate for overall accesses
773 system.cpu2.dcache.overall_mshr_miss_rate::total 0.004932 # mshr miss rate for overall accesses
774 system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 17978.527607 # average ReadReq mshr miss latency
775 system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 17978.527607 # average ReadReq mshr miss latency
776 system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 20555.555556 # average WriteReq mshr miss latency
777 system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 20555.555556 # average WriteReq mshr miss latency
778 system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 3491.379310 # average SwapReq mshr miss latency
779 system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 3491.379310 # average SwapReq mshr miss latency
780 system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 19005.535055 # average overall mshr miss latency
781 system.cpu2.dcache.demand_avg_mshr_miss_latency::total 19005.535055 # average overall mshr miss latency
782 system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 19005.535055 # average overall mshr miss latency
783 system.cpu2.dcache.overall_avg_mshr_miss_latency::total 19005.535055 # average overall mshr miss latency
784 system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
785 system.cpu2.icache.tags.replacements 280 # number of replacements
786 system.cpu2.icache.tags.tagsinuse 69.407713 # Cycle average of tags in use
787 system.cpu2.icache.tags.total_refs 165082 # Total number of references to valid blocks.
788 system.cpu2.icache.tags.sampled_refs 366 # Sample count of references to valid blocks.
789 system.cpu2.icache.tags.avg_refs 451.043716 # Average number of references to valid blocks.
790 system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
791 system.cpu2.icache.tags.occ_blocks::cpu2.inst 69.407713 # Average occupied blocks per requestor
792 system.cpu2.icache.tags.occ_percent::cpu2.inst 0.135562 # Average percentage of cache occupancy
793 system.cpu2.icache.tags.occ_percent::total 0.135562 # Average percentage of cache occupancy
794 system.cpu2.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id
795 system.cpu2.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id
796 system.cpu2.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id
797 system.cpu2.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id
798 system.cpu2.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id
799 system.cpu2.icache.tags.tag_accesses 165814 # Number of tag accesses
800 system.cpu2.icache.tags.data_accesses 165814 # Number of data accesses
801 system.cpu2.icache.ReadReq_hits::cpu2.inst 165082 # number of ReadReq hits
802 system.cpu2.icache.ReadReq_hits::total 165082 # number of ReadReq hits
803 system.cpu2.icache.demand_hits::cpu2.inst 165082 # number of demand (read+write) hits
804 system.cpu2.icache.demand_hits::total 165082 # number of demand (read+write) hits
805 system.cpu2.icache.overall_hits::cpu2.inst 165082 # number of overall hits
806 system.cpu2.icache.overall_hits::total 165082 # number of overall hits
807 system.cpu2.icache.ReadReq_misses::cpu2.inst 366 # number of ReadReq misses
808 system.cpu2.icache.ReadReq_misses::total 366 # number of ReadReq misses
809 system.cpu2.icache.demand_misses::cpu2.inst 366 # number of demand (read+write) misses
810 system.cpu2.icache.demand_misses::total 366 # number of demand (read+write) misses
811 system.cpu2.icache.overall_misses::cpu2.inst 366 # number of overall misses
812 system.cpu2.icache.overall_misses::total 366 # number of overall misses
813 system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 8101000 # number of ReadReq miss cycles
814 system.cpu2.icache.ReadReq_miss_latency::total 8101000 # number of ReadReq miss cycles
815 system.cpu2.icache.demand_miss_latency::cpu2.inst 8101000 # number of demand (read+write) miss cycles
816 system.cpu2.icache.demand_miss_latency::total 8101000 # number of demand (read+write) miss cycles
817 system.cpu2.icache.overall_miss_latency::cpu2.inst 8101000 # number of overall miss cycles
818 system.cpu2.icache.overall_miss_latency::total 8101000 # number of overall miss cycles
819 system.cpu2.icache.ReadReq_accesses::cpu2.inst 165448 # number of ReadReq accesses(hits+misses)
820 system.cpu2.icache.ReadReq_accesses::total 165448 # number of ReadReq accesses(hits+misses)
821 system.cpu2.icache.demand_accesses::cpu2.inst 165448 # number of demand (read+write) accesses
822 system.cpu2.icache.demand_accesses::total 165448 # number of demand (read+write) accesses
823 system.cpu2.icache.overall_accesses::cpu2.inst 165448 # number of overall (read+write) accesses
824 system.cpu2.icache.overall_accesses::total 165448 # number of overall (read+write) accesses
825 system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002212 # miss rate for ReadReq accesses
826 system.cpu2.icache.ReadReq_miss_rate::total 0.002212 # miss rate for ReadReq accesses
827 system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002212 # miss rate for demand accesses
828 system.cpu2.icache.demand_miss_rate::total 0.002212 # miss rate for demand accesses
829 system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002212 # miss rate for overall accesses
830 system.cpu2.icache.overall_miss_rate::total 0.002212 # miss rate for overall accesses
831 system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 22133.879781 # average ReadReq miss latency
832 system.cpu2.icache.ReadReq_avg_miss_latency::total 22133.879781 # average ReadReq miss latency
833 system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 22133.879781 # average overall miss latency
834 system.cpu2.icache.demand_avg_miss_latency::total 22133.879781 # average overall miss latency
835 system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 22133.879781 # average overall miss latency
836 system.cpu2.icache.overall_avg_miss_latency::total 22133.879781 # average overall miss latency
837 system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
838 system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
839 system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked
840 system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked
841 system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
842 system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
843 system.cpu2.icache.fast_writes 0 # number of fast writes performed
844 system.cpu2.icache.cache_copies 0 # number of cache copies performed
845 system.cpu2.icache.writebacks::writebacks 280 # number of writebacks
846 system.cpu2.icache.writebacks::total 280 # number of writebacks
847 system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 366 # number of ReadReq MSHR misses
848 system.cpu2.icache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses
849 system.cpu2.icache.demand_mshr_misses::cpu2.inst 366 # number of demand (read+write) MSHR misses
850 system.cpu2.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses
851 system.cpu2.icache.overall_mshr_misses::cpu2.inst 366 # number of overall MSHR misses
852 system.cpu2.icache.overall_mshr_misses::total 366 # number of overall MSHR misses
853 system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 7735000 # number of ReadReq MSHR miss cycles
854 system.cpu2.icache.ReadReq_mshr_miss_latency::total 7735000 # number of ReadReq MSHR miss cycles
855 system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 7735000 # number of demand (read+write) MSHR miss cycles
856 system.cpu2.icache.demand_mshr_miss_latency::total 7735000 # number of demand (read+write) MSHR miss cycles
857 system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 7735000 # number of overall MSHR miss cycles
858 system.cpu2.icache.overall_mshr_miss_latency::total 7735000 # number of overall MSHR miss cycles
859 system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.002212 # mshr miss rate for ReadReq accesses
860 system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.002212 # mshr miss rate for ReadReq accesses
861 system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.002212 # mshr miss rate for demand accesses
862 system.cpu2.icache.demand_mshr_miss_rate::total 0.002212 # mshr miss rate for demand accesses
863 system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.002212 # mshr miss rate for overall accesses
864 system.cpu2.icache.overall_mshr_miss_rate::total 0.002212 # mshr miss rate for overall accesses
865 system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 21133.879781 # average ReadReq mshr miss latency
866 system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 21133.879781 # average ReadReq mshr miss latency
867 system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 21133.879781 # average overall mshr miss latency
868 system.cpu2.icache.demand_avg_mshr_miss_latency::total 21133.879781 # average overall mshr miss latency
869 system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 21133.879781 # average overall mshr miss latency
870 system.cpu2.icache.overall_avg_mshr_miss_latency::total 21133.879781 # average overall mshr miss latency
871 system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate
872 system.cpu3.numCycles 529680 # number of cpu cycles simulated
873 system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
874 system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed
875 system.cpu3.committedInsts 169884 # Number of instructions committed
876 system.cpu3.committedOps 169884 # Number of ops (including micro ops) committed
877 system.cpu3.num_int_alu_accesses 110793 # Number of integer alu accesses
878 system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses
879 system.cpu3.num_func_calls 637 # number of times a function call or return occured
880 system.cpu3.num_conditional_control_insts 33553 # number of instructions that are conditional controls
881 system.cpu3.num_int_insts 110793 # number of integer instructions
882 system.cpu3.num_fp_insts 0 # number of float instructions
883 system.cpu3.num_int_register_reads 271193 # number of times the integer registers were read
884 system.cpu3.num_int_register_writes 102450 # number of times the integer registers were written
885 system.cpu3.num_fp_register_reads 0 # number of times the floating registers were read
886 system.cpu3.num_fp_register_writes 0 # number of times the floating registers were written
887 system.cpu3.num_mem_refs 53409 # number of memory refs
888 system.cpu3.num_load_insts 41060 # Number of load instructions
889 system.cpu3.num_store_insts 12349 # Number of store instructions
890 system.cpu3.num_idle_cycles 74420.861217 # Number of idle cycles
891 system.cpu3.num_busy_cycles 455259.138783 # Number of busy cycles
892 system.cpu3.not_idle_fraction 0.859498 # Percentage of non-idle cycles
893 system.cpu3.idle_fraction 0.140502 # Percentage of idle cycles
894 system.cpu3.Branches 35208 # Number of branches fetched
895 system.cpu3.op_class::No_OpClass 25987 15.29% 15.29% # Class of executed instruction
896 system.cpu3.op_class::IntAlu 74660 43.94% 59.23% # Class of executed instruction
897 system.cpu3.op_class::IntMult 0 0.00% 59.23% # Class of executed instruction
898 system.cpu3.op_class::IntDiv 0 0.00% 59.23% # Class of executed instruction
899 system.cpu3.op_class::FloatAdd 0 0.00% 59.23% # Class of executed instruction
900 system.cpu3.op_class::FloatCmp 0 0.00% 59.23% # Class of executed instruction
901 system.cpu3.op_class::FloatCvt 0 0.00% 59.23% # Class of executed instruction
902 system.cpu3.op_class::FloatMult 0 0.00% 59.23% # Class of executed instruction
903 system.cpu3.op_class::FloatDiv 0 0.00% 59.23% # Class of executed instruction
904 system.cpu3.op_class::FloatSqrt 0 0.00% 59.23% # Class of executed instruction
905 system.cpu3.op_class::SimdAdd 0 0.00% 59.23% # Class of executed instruction
906 system.cpu3.op_class::SimdAddAcc 0 0.00% 59.23% # Class of executed instruction
907 system.cpu3.op_class::SimdAlu 0 0.00% 59.23% # Class of executed instruction
908 system.cpu3.op_class::SimdCmp 0 0.00% 59.23% # Class of executed instruction
909 system.cpu3.op_class::SimdCvt 0 0.00% 59.23% # Class of executed instruction
910 system.cpu3.op_class::SimdMisc 0 0.00% 59.23% # Class of executed instruction
911 system.cpu3.op_class::SimdMult 0 0.00% 59.23% # Class of executed instruction
912 system.cpu3.op_class::SimdMultAcc 0 0.00% 59.23% # Class of executed instruction
913 system.cpu3.op_class::SimdShift 0 0.00% 59.23% # Class of executed instruction
914 system.cpu3.op_class::SimdShiftAcc 0 0.00% 59.23% # Class of executed instruction
915 system.cpu3.op_class::SimdSqrt 0 0.00% 59.23% # Class of executed instruction
916 system.cpu3.op_class::SimdFloatAdd 0 0.00% 59.23% # Class of executed instruction
917 system.cpu3.op_class::SimdFloatAlu 0 0.00% 59.23% # Class of executed instruction
918 system.cpu3.op_class::SimdFloatCmp 0 0.00% 59.23% # Class of executed instruction
919 system.cpu3.op_class::SimdFloatCvt 0 0.00% 59.23% # Class of executed instruction
920 system.cpu3.op_class::SimdFloatDiv 0 0.00% 59.23% # Class of executed instruction
921 system.cpu3.op_class::SimdFloatMisc 0 0.00% 59.23% # Class of executed instruction
922 system.cpu3.op_class::SimdFloatMult 0 0.00% 59.23% # Class of executed instruction
923 system.cpu3.op_class::SimdFloatMultAcc 0 0.00% 59.23% # Class of executed instruction
924 system.cpu3.op_class::SimdFloatSqrt 0 0.00% 59.23% # Class of executed instruction
925 system.cpu3.op_class::MemRead 56920 33.50% 92.73% # Class of executed instruction
926 system.cpu3.op_class::MemWrite 12349 7.27% 100.00% # Class of executed instruction
927 system.cpu3.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
928 system.cpu3.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
929 system.cpu3.op_class::total 169916 # Class of executed instruction
930 system.cpu3.dcache.tags.replacements 0 # number of replacements
931 system.cpu3.dcache.tags.tagsinuse 25.679518 # Cycle average of tags in use
932 system.cpu3.dcache.tags.total_refs 26969 # Total number of references to valid blocks.
933 system.cpu3.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks.
934 system.cpu3.dcache.tags.avg_refs 929.965517 # Average number of references to valid blocks.
935 system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
936 system.cpu3.dcache.tags.occ_blocks::cpu3.data 25.679518 # Average occupied blocks per requestor
937 system.cpu3.dcache.tags.occ_percent::cpu3.data 0.050155 # Average percentage of cache occupancy
938 system.cpu3.dcache.tags.occ_percent::total 0.050155 # Average percentage of cache occupancy
939 system.cpu3.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id
940 system.cpu3.dcache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id
941 system.cpu3.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id
942 system.cpu3.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id
943 system.cpu3.dcache.tags.tag_accesses 213856 # Number of tag accesses
944 system.cpu3.dcache.tags.data_accesses 213856 # Number of data accesses
945 system.cpu3.dcache.ReadReq_hits::cpu3.data 40892 # number of ReadReq hits
946 system.cpu3.dcache.ReadReq_hits::total 40892 # number of ReadReq hits
947 system.cpu3.dcache.WriteReq_hits::cpu3.data 12169 # number of WriteReq hits
948 system.cpu3.dcache.WriteReq_hits::total 12169 # number of WriteReq hits
949 system.cpu3.dcache.SwapReq_hits::cpu3.data 14 # number of SwapReq hits
950 system.cpu3.dcache.SwapReq_hits::total 14 # number of SwapReq hits
951 system.cpu3.dcache.demand_hits::cpu3.data 53061 # number of demand (read+write) hits
952 system.cpu3.dcache.demand_hits::total 53061 # number of demand (read+write) hits
953 system.cpu3.dcache.overall_hits::cpu3.data 53061 # number of overall hits
954 system.cpu3.dcache.overall_hits::total 53061 # number of overall hits
955 system.cpu3.dcache.ReadReq_misses::cpu3.data 161 # number of ReadReq misses
956 system.cpu3.dcache.ReadReq_misses::total 161 # number of ReadReq misses
957 system.cpu3.dcache.WriteReq_misses::cpu3.data 107 # number of WriteReq misses
958 system.cpu3.dcache.WriteReq_misses::total 107 # number of WriteReq misses
959 system.cpu3.dcache.SwapReq_misses::cpu3.data 57 # number of SwapReq misses
960 system.cpu3.dcache.SwapReq_misses::total 57 # number of SwapReq misses
961 system.cpu3.dcache.demand_misses::cpu3.data 268 # number of demand (read+write) misses
962 system.cpu3.dcache.demand_misses::total 268 # number of demand (read+write) misses
963 system.cpu3.dcache.overall_misses::cpu3.data 268 # number of overall misses
964 system.cpu3.dcache.overall_misses::total 268 # number of overall misses
965 system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 2856500 # number of ReadReq miss cycles
966 system.cpu3.dcache.ReadReq_miss_latency::total 2856500 # number of ReadReq miss cycles
967 system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 2210000 # number of WriteReq miss cycles
968 system.cpu3.dcache.WriteReq_miss_latency::total 2210000 # number of WriteReq miss cycles
969 system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 258500 # number of SwapReq miss cycles
970 system.cpu3.dcache.SwapReq_miss_latency::total 258500 # number of SwapReq miss cycles
971 system.cpu3.dcache.demand_miss_latency::cpu3.data 5066500 # number of demand (read+write) miss cycles
972 system.cpu3.dcache.demand_miss_latency::total 5066500 # number of demand (read+write) miss cycles
973 system.cpu3.dcache.overall_miss_latency::cpu3.data 5066500 # number of overall miss cycles
974 system.cpu3.dcache.overall_miss_latency::total 5066500 # number of overall miss cycles
975 system.cpu3.dcache.ReadReq_accesses::cpu3.data 41053 # number of ReadReq accesses(hits+misses)
976 system.cpu3.dcache.ReadReq_accesses::total 41053 # number of ReadReq accesses(hits+misses)
977 system.cpu3.dcache.WriteReq_accesses::cpu3.data 12276 # number of WriteReq accesses(hits+misses)
978 system.cpu3.dcache.WriteReq_accesses::total 12276 # number of WriteReq accesses(hits+misses)
979 system.cpu3.dcache.SwapReq_accesses::cpu3.data 71 # number of SwapReq accesses(hits+misses)
980 system.cpu3.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses)
981 system.cpu3.dcache.demand_accesses::cpu3.data 53329 # number of demand (read+write) accesses
982 system.cpu3.dcache.demand_accesses::total 53329 # number of demand (read+write) accesses
983 system.cpu3.dcache.overall_accesses::cpu3.data 53329 # number of overall (read+write) accesses
984 system.cpu3.dcache.overall_accesses::total 53329 # number of overall (read+write) accesses
985 system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.003922 # miss rate for ReadReq accesses
986 system.cpu3.dcache.ReadReq_miss_rate::total 0.003922 # miss rate for ReadReq accesses
987 system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.008716 # miss rate for WriteReq accesses
988 system.cpu3.dcache.WriteReq_miss_rate::total 0.008716 # miss rate for WriteReq accesses
989 system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.802817 # miss rate for SwapReq accesses
990 system.cpu3.dcache.SwapReq_miss_rate::total 0.802817 # miss rate for SwapReq accesses
991 system.cpu3.dcache.demand_miss_rate::cpu3.data 0.005025 # miss rate for demand accesses
992 system.cpu3.dcache.demand_miss_rate::total 0.005025 # miss rate for demand accesses
993 system.cpu3.dcache.overall_miss_rate::cpu3.data 0.005025 # miss rate for overall accesses
994 system.cpu3.dcache.overall_miss_rate::total 0.005025 # miss rate for overall accesses
995 system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 17742.236025 # average ReadReq miss latency
996 system.cpu3.dcache.ReadReq_avg_miss_latency::total 17742.236025 # average ReadReq miss latency
997 system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 20654.205607 # average WriteReq miss latency
998 system.cpu3.dcache.WriteReq_avg_miss_latency::total 20654.205607 # average WriteReq miss latency
999 system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 4535.087719 # average SwapReq miss latency
1000 system.cpu3.dcache.SwapReq_avg_miss_latency::total 4535.087719 # average SwapReq miss latency
1001 system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 18904.850746 # average overall miss latency
1002 system.cpu3.dcache.demand_avg_miss_latency::total 18904.850746 # average overall miss latency
1003 system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 18904.850746 # average overall miss latency
1004 system.cpu3.dcache.overall_avg_miss_latency::total 18904.850746 # average overall miss latency
1005 system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1006 system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1007 system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
1008 system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked
1009 system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1010 system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1011 system.cpu3.dcache.fast_writes 0 # number of fast writes performed
1012 system.cpu3.dcache.cache_copies 0 # number of cache copies performed
1013 system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 161 # number of ReadReq MSHR misses
1014 system.cpu3.dcache.ReadReq_mshr_misses::total 161 # number of ReadReq MSHR misses
1015 system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 107 # number of WriteReq MSHR misses
1016 system.cpu3.dcache.WriteReq_mshr_misses::total 107 # number of WriteReq MSHR misses
1017 system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 57 # number of SwapReq MSHR misses
1018 system.cpu3.dcache.SwapReq_mshr_misses::total 57 # number of SwapReq MSHR misses
1019 system.cpu3.dcache.demand_mshr_misses::cpu3.data 268 # number of demand (read+write) MSHR misses
1020 system.cpu3.dcache.demand_mshr_misses::total 268 # number of demand (read+write) MSHR misses
1021 system.cpu3.dcache.overall_mshr_misses::cpu3.data 268 # number of overall MSHR misses
1022 system.cpu3.dcache.overall_mshr_misses::total 268 # number of overall MSHR misses
1023 system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 2695500 # number of ReadReq MSHR miss cycles
1024 system.cpu3.dcache.ReadReq_mshr_miss_latency::total 2695500 # number of ReadReq MSHR miss cycles
1025 system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 2103000 # number of WriteReq MSHR miss cycles
1026 system.cpu3.dcache.WriteReq_mshr_miss_latency::total 2103000 # number of WriteReq MSHR miss cycles
1027 system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 201500 # number of SwapReq MSHR miss cycles
1028 system.cpu3.dcache.SwapReq_mshr_miss_latency::total 201500 # number of SwapReq MSHR miss cycles
1029 system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 4798500 # number of demand (read+write) MSHR miss cycles
1030 system.cpu3.dcache.demand_mshr_miss_latency::total 4798500 # number of demand (read+write) MSHR miss cycles
1031 system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 4798500 # number of overall MSHR miss cycles
1032 system.cpu3.dcache.overall_mshr_miss_latency::total 4798500 # number of overall MSHR miss cycles
1033 system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003922 # mshr miss rate for ReadReq accesses
1034 system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003922 # mshr miss rate for ReadReq accesses
1035 system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.008716 # mshr miss rate for WriteReq accesses
1036 system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.008716 # mshr miss rate for WriteReq accesses
1037 system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.802817 # mshr miss rate for SwapReq accesses
1038 system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.802817 # mshr miss rate for SwapReq accesses
1039 system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.005025 # mshr miss rate for demand accesses
1040 system.cpu3.dcache.demand_mshr_miss_rate::total 0.005025 # mshr miss rate for demand accesses
1041 system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.005025 # mshr miss rate for overall accesses
1042 system.cpu3.dcache.overall_mshr_miss_rate::total 0.005025 # mshr miss rate for overall accesses
1043 system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 16742.236025 # average ReadReq mshr miss latency
1044 system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 16742.236025 # average ReadReq mshr miss latency
1045 system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 19654.205607 # average WriteReq mshr miss latency
1046 system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 19654.205607 # average WriteReq mshr miss latency
1047 system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 3535.087719 # average SwapReq mshr miss latency
1048 system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 3535.087719 # average SwapReq mshr miss latency
1049 system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 17904.850746 # average overall mshr miss latency
1050 system.cpu3.dcache.demand_avg_mshr_miss_latency::total 17904.850746 # average overall mshr miss latency
1051 system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 17904.850746 # average overall mshr miss latency
1052 system.cpu3.dcache.overall_avg_mshr_miss_latency::total 17904.850746 # average overall mshr miss latency
1053 system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1054 system.cpu3.icache.tags.replacements 281 # number of replacements
1055 system.cpu3.icache.tags.tagsinuse 64.991831 # Cycle average of tags in use
1056 system.cpu3.icache.tags.total_refs 169550 # Total number of references to valid blocks.
1057 system.cpu3.icache.tags.sampled_refs 367 # Sample count of references to valid blocks.
1058 system.cpu3.icache.tags.avg_refs 461.989101 # Average number of references to valid blocks.
1059 system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1060 system.cpu3.icache.tags.occ_blocks::cpu3.inst 64.991831 # Average occupied blocks per requestor
1061 system.cpu3.icache.tags.occ_percent::cpu3.inst 0.126937 # Average percentage of cache occupancy
1062 system.cpu3.icache.tags.occ_percent::total 0.126937 # Average percentage of cache occupancy
1063 system.cpu3.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id
1064 system.cpu3.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id
1065 system.cpu3.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id
1066 system.cpu3.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id
1067 system.cpu3.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id
1068 system.cpu3.icache.tags.tag_accesses 170284 # Number of tag accesses
1069 system.cpu3.icache.tags.data_accesses 170284 # Number of data accesses
1070 system.cpu3.icache.ReadReq_hits::cpu3.inst 169550 # number of ReadReq hits
1071 system.cpu3.icache.ReadReq_hits::total 169550 # number of ReadReq hits
1072 system.cpu3.icache.demand_hits::cpu3.inst 169550 # number of demand (read+write) hits
1073 system.cpu3.icache.demand_hits::total 169550 # number of demand (read+write) hits
1074 system.cpu3.icache.overall_hits::cpu3.inst 169550 # number of overall hits
1075 system.cpu3.icache.overall_hits::total 169550 # number of overall hits
1076 system.cpu3.icache.ReadReq_misses::cpu3.inst 367 # number of ReadReq misses
1077 system.cpu3.icache.ReadReq_misses::total 367 # number of ReadReq misses
1078 system.cpu3.icache.demand_misses::cpu3.inst 367 # number of demand (read+write) misses
1079 system.cpu3.icache.demand_misses::total 367 # number of demand (read+write) misses
1080 system.cpu3.icache.overall_misses::cpu3.inst 367 # number of overall misses
1081 system.cpu3.icache.overall_misses::total 367 # number of overall misses
1082 system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 5473500 # number of ReadReq miss cycles
1083 system.cpu3.icache.ReadReq_miss_latency::total 5473500 # number of ReadReq miss cycles
1084 system.cpu3.icache.demand_miss_latency::cpu3.inst 5473500 # number of demand (read+write) miss cycles
1085 system.cpu3.icache.demand_miss_latency::total 5473500 # number of demand (read+write) miss cycles
1086 system.cpu3.icache.overall_miss_latency::cpu3.inst 5473500 # number of overall miss cycles
1087 system.cpu3.icache.overall_miss_latency::total 5473500 # number of overall miss cycles
1088 system.cpu3.icache.ReadReq_accesses::cpu3.inst 169917 # number of ReadReq accesses(hits+misses)
1089 system.cpu3.icache.ReadReq_accesses::total 169917 # number of ReadReq accesses(hits+misses)
1090 system.cpu3.icache.demand_accesses::cpu3.inst 169917 # number of demand (read+write) accesses
1091 system.cpu3.icache.demand_accesses::total 169917 # number of demand (read+write) accesses
1092 system.cpu3.icache.overall_accesses::cpu3.inst 169917 # number of overall (read+write) accesses
1093 system.cpu3.icache.overall_accesses::total 169917 # number of overall (read+write) accesses
1094 system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002160 # miss rate for ReadReq accesses
1095 system.cpu3.icache.ReadReq_miss_rate::total 0.002160 # miss rate for ReadReq accesses
1096 system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002160 # miss rate for demand accesses
1097 system.cpu3.icache.demand_miss_rate::total 0.002160 # miss rate for demand accesses
1098 system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002160 # miss rate for overall accesses
1099 system.cpu3.icache.overall_miss_rate::total 0.002160 # miss rate for overall accesses
1100 system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 14914.168937 # average ReadReq miss latency
1101 system.cpu3.icache.ReadReq_avg_miss_latency::total 14914.168937 # average ReadReq miss latency
1102 system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 14914.168937 # average overall miss latency
1103 system.cpu3.icache.demand_avg_miss_latency::total 14914.168937 # average overall miss latency
1104 system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 14914.168937 # average overall miss latency
1105 system.cpu3.icache.overall_avg_miss_latency::total 14914.168937 # average overall miss latency
1106 system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1107 system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1108 system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked
1109 system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked
1110 system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1111 system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1112 system.cpu3.icache.fast_writes 0 # number of fast writes performed
1113 system.cpu3.icache.cache_copies 0 # number of cache copies performed
1114 system.cpu3.icache.writebacks::writebacks 281 # number of writebacks
1115 system.cpu3.icache.writebacks::total 281 # number of writebacks
1116 system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 367 # number of ReadReq MSHR misses
1117 system.cpu3.icache.ReadReq_mshr_misses::total 367 # number of ReadReq MSHR misses
1118 system.cpu3.icache.demand_mshr_misses::cpu3.inst 367 # number of demand (read+write) MSHR misses
1119 system.cpu3.icache.demand_mshr_misses::total 367 # number of demand (read+write) MSHR misses
1120 system.cpu3.icache.overall_mshr_misses::cpu3.inst 367 # number of overall MSHR misses
1121 system.cpu3.icache.overall_mshr_misses::total 367 # number of overall MSHR misses
1122 system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 5106500 # number of ReadReq MSHR miss cycles
1123 system.cpu3.icache.ReadReq_mshr_miss_latency::total 5106500 # number of ReadReq MSHR miss cycles
1124 system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 5106500 # number of demand (read+write) MSHR miss cycles
1125 system.cpu3.icache.demand_mshr_miss_latency::total 5106500 # number of demand (read+write) MSHR miss cycles
1126 system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 5106500 # number of overall MSHR miss cycles
1127 system.cpu3.icache.overall_mshr_miss_latency::total 5106500 # number of overall MSHR miss cycles
1128 system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.002160 # mshr miss rate for ReadReq accesses
1129 system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.002160 # mshr miss rate for ReadReq accesses
1130 system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.002160 # mshr miss rate for demand accesses
1131 system.cpu3.icache.demand_mshr_miss_rate::total 0.002160 # mshr miss rate for demand accesses
1132 system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.002160 # mshr miss rate for overall accesses
1133 system.cpu3.icache.overall_mshr_miss_rate::total 0.002160 # mshr miss rate for overall accesses
1134 system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 13914.168937 # average ReadReq mshr miss latency
1135 system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 13914.168937 # average ReadReq mshr miss latency
1136 system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 13914.168937 # average overall mshr miss latency
1137 system.cpu3.icache.demand_avg_mshr_miss_latency::total 13914.168937 # average overall mshr miss latency
1138 system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 13914.168937 # average overall mshr miss latency
1139 system.cpu3.icache.overall_avg_mshr_miss_latency::total 13914.168937 # average overall mshr miss latency
1140 system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1141 system.l2c.tags.replacements 0 # number of replacements
1142 system.l2c.tags.tagsinuse 347.318197 # Cycle average of tags in use
1143 system.l2c.tags.total_refs 1714 # Total number of references to valid blocks.
1144 system.l2c.tags.sampled_refs 429 # Sample count of references to valid blocks.
1145 system.l2c.tags.avg_refs 3.995338 # Average number of references to valid blocks.
1146 system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1147 system.l2c.tags.occ_blocks::writebacks 0.882018 # Average occupied blocks per requestor
1148 system.l2c.tags.occ_blocks::cpu0.inst 230.794628 # Average occupied blocks per requestor
1149 system.l2c.tags.occ_blocks::cpu0.data 54.021394 # Average occupied blocks per requestor
1150 system.l2c.tags.occ_blocks::cpu1.inst 6.166785 # Average occupied blocks per requestor
1151 system.l2c.tags.occ_blocks::cpu1.data 0.835671 # Average occupied blocks per requestor
1152 system.l2c.tags.occ_blocks::cpu2.inst 46.779239 # Average occupied blocks per requestor
1153 system.l2c.tags.occ_blocks::cpu2.data 6.090035 # Average occupied blocks per requestor
1154 system.l2c.tags.occ_blocks::cpu3.inst 0.944334 # Average occupied blocks per requestor
1155 system.l2c.tags.occ_blocks::cpu3.data 0.804093 # Average occupied blocks per requestor
1156 system.l2c.tags.occ_percent::writebacks 0.000013 # Average percentage of cache occupancy
1157 system.l2c.tags.occ_percent::cpu0.inst 0.003522 # Average percentage of cache occupancy
1158 system.l2c.tags.occ_percent::cpu0.data 0.000824 # Average percentage of cache occupancy
1159 system.l2c.tags.occ_percent::cpu1.inst 0.000094 # Average percentage of cache occupancy
1160 system.l2c.tags.occ_percent::cpu1.data 0.000013 # Average percentage of cache occupancy
1161 system.l2c.tags.occ_percent::cpu2.inst 0.000714 # Average percentage of cache occupancy
1162 system.l2c.tags.occ_percent::cpu2.data 0.000093 # Average percentage of cache occupancy
1163 system.l2c.tags.occ_percent::cpu3.inst 0.000014 # Average percentage of cache occupancy
1164 system.l2c.tags.occ_percent::cpu3.data 0.000012 # Average percentage of cache occupancy
1165 system.l2c.tags.occ_percent::total 0.005300 # Average percentage of cache occupancy
1166 system.l2c.tags.occ_task_id_blocks::1024 429 # Occupied blocks per task id
1167 system.l2c.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id
1168 system.l2c.tags.age_task_id_blocks_1024::2 374 # Occupied blocks per task id
1169 system.l2c.tags.occ_task_id_percent::1024 0.006546 # Percentage of cache occupancy per task id
1170 system.l2c.tags.tag_accesses 19669 # Number of tag accesses
1171 system.l2c.tags.data_accesses 19669 # Number of data accesses
1172 system.l2c.WritebackDirty_hits::writebacks 1 # number of WritebackDirty hits
1173 system.l2c.WritebackDirty_hits::total 1 # number of WritebackDirty hits
1174 system.l2c.WritebackClean_hits::writebacks 495 # number of WritebackClean hits
1175 system.l2c.WritebackClean_hits::total 495 # number of WritebackClean hits
1176 system.l2c.UpgradeReq_hits::cpu0.data 2 # number of UpgradeReq hits
1177 system.l2c.UpgradeReq_hits::total 2 # number of UpgradeReq hits
1178 system.l2c.ReadCleanReq_hits::cpu0.inst 182 # number of ReadCleanReq hits
1179 system.l2c.ReadCleanReq_hits::cpu1.inst 352 # number of ReadCleanReq hits
1180 system.l2c.ReadCleanReq_hits::cpu2.inst 301 # number of ReadCleanReq hits
1181 system.l2c.ReadCleanReq_hits::cpu3.inst 357 # number of ReadCleanReq hits
1182 system.l2c.ReadCleanReq_hits::total 1192 # number of ReadCleanReq hits
1183 system.l2c.ReadSharedReq_hits::cpu0.data 5 # number of ReadSharedReq hits
1184 system.l2c.ReadSharedReq_hits::cpu1.data 9 # number of ReadSharedReq hits
1185 system.l2c.ReadSharedReq_hits::cpu2.data 3 # number of ReadSharedReq hits
1186 system.l2c.ReadSharedReq_hits::cpu3.data 9 # number of ReadSharedReq hits
1187 system.l2c.ReadSharedReq_hits::total 26 # number of ReadSharedReq hits
1188 system.l2c.demand_hits::cpu0.inst 182 # number of demand (read+write) hits
1189 system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits
1190 system.l2c.demand_hits::cpu1.inst 352 # number of demand (read+write) hits
1191 system.l2c.demand_hits::cpu1.data 9 # number of demand (read+write) hits
1192 system.l2c.demand_hits::cpu2.inst 301 # number of demand (read+write) hits
1193 system.l2c.demand_hits::cpu2.data 3 # number of demand (read+write) hits
1194 system.l2c.demand_hits::cpu3.inst 357 # number of demand (read+write) hits
1195 system.l2c.demand_hits::cpu3.data 9 # number of demand (read+write) hits
1196 system.l2c.demand_hits::total 1218 # number of demand (read+write) hits
1197 system.l2c.overall_hits::cpu0.inst 182 # number of overall hits
1198 system.l2c.overall_hits::cpu0.data 5 # number of overall hits
1199 system.l2c.overall_hits::cpu1.inst 352 # number of overall hits
1200 system.l2c.overall_hits::cpu1.data 9 # number of overall hits
1201 system.l2c.overall_hits::cpu2.inst 301 # number of overall hits
1202 system.l2c.overall_hits::cpu2.data 3 # number of overall hits
1203 system.l2c.overall_hits::cpu3.inst 357 # number of overall hits
1204 system.l2c.overall_hits::cpu3.data 9 # number of overall hits
1205 system.l2c.overall_hits::total 1218 # number of overall hits
1206 system.l2c.UpgradeReq_misses::cpu0.data 28 # number of UpgradeReq misses
1207 system.l2c.UpgradeReq_misses::cpu1.data 15 # number of UpgradeReq misses
1208 system.l2c.UpgradeReq_misses::cpu2.data 17 # number of UpgradeReq misses
1209 system.l2c.UpgradeReq_misses::cpu3.data 16 # number of UpgradeReq misses
1210 system.l2c.UpgradeReq_misses::total 76 # number of UpgradeReq misses
1211 system.l2c.ReadExReq_misses::cpu0.data 99 # number of ReadExReq misses
1212 system.l2c.ReadExReq_misses::cpu1.data 14 # number of ReadExReq misses
1213 system.l2c.ReadExReq_misses::cpu2.data 15 # number of ReadExReq misses
1214 system.l2c.ReadExReq_misses::cpu3.data 14 # number of ReadExReq misses
1215 system.l2c.ReadExReq_misses::total 142 # number of ReadExReq misses
1216 system.l2c.ReadCleanReq_misses::cpu0.inst 285 # number of ReadCleanReq misses
1217 system.l2c.ReadCleanReq_misses::cpu1.inst 14 # number of ReadCleanReq misses
1218 system.l2c.ReadCleanReq_misses::cpu2.inst 65 # number of ReadCleanReq misses
1219 system.l2c.ReadCleanReq_misses::cpu3.inst 10 # number of ReadCleanReq misses
1220 system.l2c.ReadCleanReq_misses::total 374 # number of ReadCleanReq misses
1221 system.l2c.ReadSharedReq_misses::cpu0.data 66 # number of ReadSharedReq misses
1222 system.l2c.ReadSharedReq_misses::cpu1.data 2 # number of ReadSharedReq misses
1223 system.l2c.ReadSharedReq_misses::cpu2.data 8 # number of ReadSharedReq misses
1224 system.l2c.ReadSharedReq_misses::cpu3.data 2 # number of ReadSharedReq misses
1225 system.l2c.ReadSharedReq_misses::total 78 # number of ReadSharedReq misses
1226 system.l2c.demand_misses::cpu0.inst 285 # number of demand (read+write) misses
1227 system.l2c.demand_misses::cpu0.data 165 # number of demand (read+write) misses
1228 system.l2c.demand_misses::cpu1.inst 14 # number of demand (read+write) misses
1229 system.l2c.demand_misses::cpu1.data 16 # number of demand (read+write) misses
1230 system.l2c.demand_misses::cpu2.inst 65 # number of demand (read+write) misses
1231 system.l2c.demand_misses::cpu2.data 23 # number of demand (read+write) misses
1232 system.l2c.demand_misses::cpu3.inst 10 # number of demand (read+write) misses
1233 system.l2c.demand_misses::cpu3.data 16 # number of demand (read+write) misses
1234 system.l2c.demand_misses::total 594 # number of demand (read+write) misses
1235 system.l2c.overall_misses::cpu0.inst 285 # number of overall misses
1236 system.l2c.overall_misses::cpu0.data 165 # number of overall misses
1237 system.l2c.overall_misses::cpu1.inst 14 # number of overall misses
1238 system.l2c.overall_misses::cpu1.data 16 # number of overall misses
1239 system.l2c.overall_misses::cpu2.inst 65 # number of overall misses
1240 system.l2c.overall_misses::cpu2.data 23 # number of overall misses
1241 system.l2c.overall_misses::cpu3.inst 10 # number of overall misses
1242 system.l2c.overall_misses::cpu3.data 16 # number of overall misses
1243 system.l2c.overall_misses::total 594 # number of overall misses
1244 system.l2c.ReadExReq_miss_latency::cpu0.data 5892000 # number of ReadExReq miss cycles
1245 system.l2c.ReadExReq_miss_latency::cpu1.data 842000 # number of ReadExReq miss cycles
1246 system.l2c.ReadExReq_miss_latency::cpu2.data 896000 # number of ReadExReq miss cycles
1247 system.l2c.ReadExReq_miss_latency::cpu3.data 840000 # number of ReadExReq miss cycles
1248 system.l2c.ReadExReq_miss_latency::total 8470000 # number of ReadExReq miss cycles
1249 system.l2c.ReadCleanReq_miss_latency::cpu0.inst 16964000 # number of ReadCleanReq miss cycles
1250 system.l2c.ReadCleanReq_miss_latency::cpu1.inst 821500 # number of ReadCleanReq miss cycles
1251 system.l2c.ReadCleanReq_miss_latency::cpu2.inst 3820000 # number of ReadCleanReq miss cycles
1252 system.l2c.ReadCleanReq_miss_latency::cpu3.inst 553500 # number of ReadCleanReq miss cycles
1253 system.l2c.ReadCleanReq_miss_latency::total 22159000 # number of ReadCleanReq miss cycles
1254 system.l2c.ReadSharedReq_miss_latency::cpu0.data 3927500 # number of ReadSharedReq miss cycles
1255 system.l2c.ReadSharedReq_miss_latency::cpu1.data 118500 # number of ReadSharedReq miss cycles
1256 system.l2c.ReadSharedReq_miss_latency::cpu2.data 476000 # number of ReadSharedReq miss cycles
1257 system.l2c.ReadSharedReq_miss_latency::cpu3.data 118000 # number of ReadSharedReq miss cycles
1258 system.l2c.ReadSharedReq_miss_latency::total 4640000 # number of ReadSharedReq miss cycles
1259 system.l2c.demand_miss_latency::cpu0.inst 16964000 # number of demand (read+write) miss cycles
1260 system.l2c.demand_miss_latency::cpu0.data 9819500 # number of demand (read+write) miss cycles
1261 system.l2c.demand_miss_latency::cpu1.inst 821500 # number of demand (read+write) miss cycles
1262 system.l2c.demand_miss_latency::cpu1.data 960500 # number of demand (read+write) miss cycles
1263 system.l2c.demand_miss_latency::cpu2.inst 3820000 # number of demand (read+write) miss cycles
1264 system.l2c.demand_miss_latency::cpu2.data 1372000 # number of demand (read+write) miss cycles
1265 system.l2c.demand_miss_latency::cpu3.inst 553500 # number of demand (read+write) miss cycles
1266 system.l2c.demand_miss_latency::cpu3.data 958000 # number of demand (read+write) miss cycles
1267 system.l2c.demand_miss_latency::total 35269000 # number of demand (read+write) miss cycles
1268 system.l2c.overall_miss_latency::cpu0.inst 16964000 # number of overall miss cycles
1269 system.l2c.overall_miss_latency::cpu0.data 9819500 # number of overall miss cycles
1270 system.l2c.overall_miss_latency::cpu1.inst 821500 # number of overall miss cycles
1271 system.l2c.overall_miss_latency::cpu1.data 960500 # number of overall miss cycles
1272 system.l2c.overall_miss_latency::cpu2.inst 3820000 # number of overall miss cycles
1273 system.l2c.overall_miss_latency::cpu2.data 1372000 # number of overall miss cycles
1274 system.l2c.overall_miss_latency::cpu3.inst 553500 # number of overall miss cycles
1275 system.l2c.overall_miss_latency::cpu3.data 958000 # number of overall miss cycles
1276 system.l2c.overall_miss_latency::total 35269000 # number of overall miss cycles
1277 system.l2c.WritebackDirty_accesses::writebacks 1 # number of WritebackDirty accesses(hits+misses)
1278 system.l2c.WritebackDirty_accesses::total 1 # number of WritebackDirty accesses(hits+misses)
1279 system.l2c.WritebackClean_accesses::writebacks 495 # number of WritebackClean accesses(hits+misses)
1280 system.l2c.WritebackClean_accesses::total 495 # number of WritebackClean accesses(hits+misses)
1281 system.l2c.UpgradeReq_accesses::cpu0.data 30 # number of UpgradeReq accesses(hits+misses)
1282 system.l2c.UpgradeReq_accesses::cpu1.data 15 # number of UpgradeReq accesses(hits+misses)
1283 system.l2c.UpgradeReq_accesses::cpu2.data 17 # number of UpgradeReq accesses(hits+misses)
1284 system.l2c.UpgradeReq_accesses::cpu3.data 16 # number of UpgradeReq accesses(hits+misses)
1285 system.l2c.UpgradeReq_accesses::total 78 # number of UpgradeReq accesses(hits+misses)
1286 system.l2c.ReadExReq_accesses::cpu0.data 99 # number of ReadExReq accesses(hits+misses)
1287 system.l2c.ReadExReq_accesses::cpu1.data 14 # number of ReadExReq accesses(hits+misses)
1288 system.l2c.ReadExReq_accesses::cpu2.data 15 # number of ReadExReq accesses(hits+misses)
1289 system.l2c.ReadExReq_accesses::cpu3.data 14 # number of ReadExReq accesses(hits+misses)
1290 system.l2c.ReadExReq_accesses::total 142 # number of ReadExReq accesses(hits+misses)
1291 system.l2c.ReadCleanReq_accesses::cpu0.inst 467 # number of ReadCleanReq accesses(hits+misses)
1292 system.l2c.ReadCleanReq_accesses::cpu1.inst 366 # number of ReadCleanReq accesses(hits+misses)
1293 system.l2c.ReadCleanReq_accesses::cpu2.inst 366 # number of ReadCleanReq accesses(hits+misses)
1294 system.l2c.ReadCleanReq_accesses::cpu3.inst 367 # number of ReadCleanReq accesses(hits+misses)
1295 system.l2c.ReadCleanReq_accesses::total 1566 # number of ReadCleanReq accesses(hits+misses)
1296 system.l2c.ReadSharedReq_accesses::cpu0.data 71 # number of ReadSharedReq accesses(hits+misses)
1297 system.l2c.ReadSharedReq_accesses::cpu1.data 11 # number of ReadSharedReq accesses(hits+misses)
1298 system.l2c.ReadSharedReq_accesses::cpu2.data 11 # number of ReadSharedReq accesses(hits+misses)
1299 system.l2c.ReadSharedReq_accesses::cpu3.data 11 # number of ReadSharedReq accesses(hits+misses)
1300 system.l2c.ReadSharedReq_accesses::total 104 # number of ReadSharedReq accesses(hits+misses)
1301 system.l2c.demand_accesses::cpu0.inst 467 # number of demand (read+write) accesses
1302 system.l2c.demand_accesses::cpu0.data 170 # number of demand (read+write) accesses
1303 system.l2c.demand_accesses::cpu1.inst 366 # number of demand (read+write) accesses
1304 system.l2c.demand_accesses::cpu1.data 25 # number of demand (read+write) accesses
1305 system.l2c.demand_accesses::cpu2.inst 366 # number of demand (read+write) accesses
1306 system.l2c.demand_accesses::cpu2.data 26 # number of demand (read+write) accesses
1307 system.l2c.demand_accesses::cpu3.inst 367 # number of demand (read+write) accesses
1308 system.l2c.demand_accesses::cpu3.data 25 # number of demand (read+write) accesses
1309 system.l2c.demand_accesses::total 1812 # number of demand (read+write) accesses
1310 system.l2c.overall_accesses::cpu0.inst 467 # number of overall (read+write) accesses
1311 system.l2c.overall_accesses::cpu0.data 170 # number of overall (read+write) accesses
1312 system.l2c.overall_accesses::cpu1.inst 366 # number of overall (read+write) accesses
1313 system.l2c.overall_accesses::cpu1.data 25 # number of overall (read+write) accesses
1314 system.l2c.overall_accesses::cpu2.inst 366 # number of overall (read+write) accesses
1315 system.l2c.overall_accesses::cpu2.data 26 # number of overall (read+write) accesses
1316 system.l2c.overall_accesses::cpu3.inst 367 # number of overall (read+write) accesses
1317 system.l2c.overall_accesses::cpu3.data 25 # number of overall (read+write) accesses
1318 system.l2c.overall_accesses::total 1812 # number of overall (read+write) accesses
1319 system.l2c.UpgradeReq_miss_rate::cpu0.data 0.933333 # miss rate for UpgradeReq accesses
1320 system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses
1321 system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses
1322 system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses
1323 system.l2c.UpgradeReq_miss_rate::total 0.974359 # miss rate for UpgradeReq accesses
1324 system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses
1325 system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses
1326 system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses
1327 system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses
1328 system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
1329 system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.610278 # miss rate for ReadCleanReq accesses
1330 system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.038251 # miss rate for ReadCleanReq accesses
1331 system.l2c.ReadCleanReq_miss_rate::cpu2.inst 0.177596 # miss rate for ReadCleanReq accesses
1332 system.l2c.ReadCleanReq_miss_rate::cpu3.inst 0.027248 # miss rate for ReadCleanReq accesses
1333 system.l2c.ReadCleanReq_miss_rate::total 0.238825 # miss rate for ReadCleanReq accesses
1334 system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.929577 # miss rate for ReadSharedReq accesses
1335 system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.181818 # miss rate for ReadSharedReq accesses
1336 system.l2c.ReadSharedReq_miss_rate::cpu2.data 0.727273 # miss rate for ReadSharedReq accesses
1337 system.l2c.ReadSharedReq_miss_rate::cpu3.data 0.181818 # miss rate for ReadSharedReq accesses
1338 system.l2c.ReadSharedReq_miss_rate::total 0.750000 # miss rate for ReadSharedReq accesses
1339 system.l2c.demand_miss_rate::cpu0.inst 0.610278 # miss rate for demand accesses
1340 system.l2c.demand_miss_rate::cpu0.data 0.970588 # miss rate for demand accesses
1341 system.l2c.demand_miss_rate::cpu1.inst 0.038251 # miss rate for demand accesses
1342 system.l2c.demand_miss_rate::cpu1.data 0.640000 # miss rate for demand accesses
1343 system.l2c.demand_miss_rate::cpu2.inst 0.177596 # miss rate for demand accesses
1344 system.l2c.demand_miss_rate::cpu2.data 0.884615 # miss rate for demand accesses
1345 system.l2c.demand_miss_rate::cpu3.inst 0.027248 # miss rate for demand accesses
1346 system.l2c.demand_miss_rate::cpu3.data 0.640000 # miss rate for demand accesses
1347 system.l2c.demand_miss_rate::total 0.327815 # miss rate for demand accesses
1348 system.l2c.overall_miss_rate::cpu0.inst 0.610278 # miss rate for overall accesses
1349 system.l2c.overall_miss_rate::cpu0.data 0.970588 # miss rate for overall accesses
1350 system.l2c.overall_miss_rate::cpu1.inst 0.038251 # miss rate for overall accesses
1351 system.l2c.overall_miss_rate::cpu1.data 0.640000 # miss rate for overall accesses
1352 system.l2c.overall_miss_rate::cpu2.inst 0.177596 # miss rate for overall accesses
1353 system.l2c.overall_miss_rate::cpu2.data 0.884615 # miss rate for overall accesses
1354 system.l2c.overall_miss_rate::cpu3.inst 0.027248 # miss rate for overall accesses
1355 system.l2c.overall_miss_rate::cpu3.data 0.640000 # miss rate for overall accesses
1356 system.l2c.overall_miss_rate::total 0.327815 # miss rate for overall accesses
1357 system.l2c.ReadExReq_avg_miss_latency::cpu0.data 59515.151515 # average ReadExReq miss latency
1358 system.l2c.ReadExReq_avg_miss_latency::cpu1.data 60142.857143 # average ReadExReq miss latency
1359 system.l2c.ReadExReq_avg_miss_latency::cpu2.data 59733.333333 # average ReadExReq miss latency
1360 system.l2c.ReadExReq_avg_miss_latency::cpu3.data 60000 # average ReadExReq miss latency
1361 system.l2c.ReadExReq_avg_miss_latency::total 59647.887324 # average ReadExReq miss latency
1362 system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 59522.807018 # average ReadCleanReq miss latency
1363 system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 58678.571429 # average ReadCleanReq miss latency
1364 system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 58769.230769 # average ReadCleanReq miss latency
1365 system.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst 55350 # average ReadCleanReq miss latency
1366 system.l2c.ReadCleanReq_avg_miss_latency::total 59248.663102 # average ReadCleanReq miss latency
1367 system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 59507.575758 # average ReadSharedReq miss latency
1368 system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 59250 # average ReadSharedReq miss latency
1369 system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 59500 # average ReadSharedReq miss latency
1370 system.l2c.ReadSharedReq_avg_miss_latency::cpu3.data 59000 # average ReadSharedReq miss latency
1371 system.l2c.ReadSharedReq_avg_miss_latency::total 59487.179487 # average ReadSharedReq miss latency
1372 system.l2c.demand_avg_miss_latency::cpu0.inst 59522.807018 # average overall miss latency
1373 system.l2c.demand_avg_miss_latency::cpu0.data 59512.121212 # average overall miss latency
1374 system.l2c.demand_avg_miss_latency::cpu1.inst 58678.571429 # average overall miss latency
1375 system.l2c.demand_avg_miss_latency::cpu1.data 60031.250000 # average overall miss latency
1376 system.l2c.demand_avg_miss_latency::cpu2.inst 58769.230769 # average overall miss latency
1377 system.l2c.demand_avg_miss_latency::cpu2.data 59652.173913 # average overall miss latency
1378 system.l2c.demand_avg_miss_latency::cpu3.inst 55350 # average overall miss latency
1379 system.l2c.demand_avg_miss_latency::cpu3.data 59875 # average overall miss latency
1380 system.l2c.demand_avg_miss_latency::total 59375.420875 # average overall miss latency
1381 system.l2c.overall_avg_miss_latency::cpu0.inst 59522.807018 # average overall miss latency
1382 system.l2c.overall_avg_miss_latency::cpu0.data 59512.121212 # average overall miss latency
1383 system.l2c.overall_avg_miss_latency::cpu1.inst 58678.571429 # average overall miss latency
1384 system.l2c.overall_avg_miss_latency::cpu1.data 60031.250000 # average overall miss latency
1385 system.l2c.overall_avg_miss_latency::cpu2.inst 58769.230769 # average overall miss latency
1386 system.l2c.overall_avg_miss_latency::cpu2.data 59652.173913 # average overall miss latency
1387 system.l2c.overall_avg_miss_latency::cpu3.inst 55350 # average overall miss latency
1388 system.l2c.overall_avg_miss_latency::cpu3.data 59875 # average overall miss latency
1389 system.l2c.overall_avg_miss_latency::total 59375.420875 # average overall miss latency
1390 system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1391 system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
1392 system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
1393 system.l2c.blocked::no_targets 0 # number of cycles access was blocked
1394 system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1395 system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1396 system.l2c.fast_writes 0 # number of fast writes performed
1397 system.l2c.cache_copies 0 # number of cache copies performed
1398 system.l2c.ReadCleanReq_mshr_hits::cpu1.inst 7 # number of ReadCleanReq MSHR hits
1399 system.l2c.ReadCleanReq_mshr_hits::cpu2.inst 7 # number of ReadCleanReq MSHR hits
1400 system.l2c.ReadCleanReq_mshr_hits::cpu3.inst 6 # number of ReadCleanReq MSHR hits
1401 system.l2c.ReadCleanReq_mshr_hits::total 20 # number of ReadCleanReq MSHR hits
1402 system.l2c.ReadSharedReq_mshr_hits::cpu1.data 1 # number of ReadSharedReq MSHR hits
1403 system.l2c.ReadSharedReq_mshr_hits::cpu3.data 1 # number of ReadSharedReq MSHR hits
1404 system.l2c.ReadSharedReq_mshr_hits::total 2 # number of ReadSharedReq MSHR hits
1405 system.l2c.demand_mshr_hits::cpu1.inst 7 # number of demand (read+write) MSHR hits
1406 system.l2c.demand_mshr_hits::cpu1.data 1 # number of demand (read+write) MSHR hits
1407 system.l2c.demand_mshr_hits::cpu2.inst 7 # number of demand (read+write) MSHR hits
1408 system.l2c.demand_mshr_hits::cpu3.inst 6 # number of demand (read+write) MSHR hits
1409 system.l2c.demand_mshr_hits::cpu3.data 1 # number of demand (read+write) MSHR hits
1410 system.l2c.demand_mshr_hits::total 22 # number of demand (read+write) MSHR hits
1411 system.l2c.overall_mshr_hits::cpu1.inst 7 # number of overall MSHR hits
1412 system.l2c.overall_mshr_hits::cpu1.data 1 # number of overall MSHR hits
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1414 system.l2c.overall_mshr_hits::cpu3.inst 6 # number of overall MSHR hits
1415 system.l2c.overall_mshr_hits::cpu3.data 1 # number of overall MSHR hits
1416 system.l2c.overall_mshr_hits::total 22 # number of overall MSHR hits
1417 system.l2c.UpgradeReq_mshr_misses::cpu0.data 28 # number of UpgradeReq MSHR misses
1418 system.l2c.UpgradeReq_mshr_misses::cpu1.data 15 # number of UpgradeReq MSHR misses
1419 system.l2c.UpgradeReq_mshr_misses::cpu2.data 17 # number of UpgradeReq MSHR misses
1420 system.l2c.UpgradeReq_mshr_misses::cpu3.data 16 # number of UpgradeReq MSHR misses
1421 system.l2c.UpgradeReq_mshr_misses::total 76 # number of UpgradeReq MSHR misses
1422 system.l2c.ReadExReq_mshr_misses::cpu0.data 99 # number of ReadExReq MSHR misses
1423 system.l2c.ReadExReq_mshr_misses::cpu1.data 14 # number of ReadExReq MSHR misses
1424 system.l2c.ReadExReq_mshr_misses::cpu2.data 15 # number of ReadExReq MSHR misses
1425 system.l2c.ReadExReq_mshr_misses::cpu3.data 14 # number of ReadExReq MSHR misses
1426 system.l2c.ReadExReq_mshr_misses::total 142 # number of ReadExReq MSHR misses
1427 system.l2c.ReadCleanReq_mshr_misses::cpu0.inst 285 # number of ReadCleanReq MSHR misses
1428 system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 7 # number of ReadCleanReq MSHR misses
1429 system.l2c.ReadCleanReq_mshr_misses::cpu2.inst 58 # number of ReadCleanReq MSHR misses
1430 system.l2c.ReadCleanReq_mshr_misses::cpu3.inst 4 # number of ReadCleanReq MSHR misses
1431 system.l2c.ReadCleanReq_mshr_misses::total 354 # number of ReadCleanReq MSHR misses
1432 system.l2c.ReadSharedReq_mshr_misses::cpu0.data 66 # number of ReadSharedReq MSHR misses
1433 system.l2c.ReadSharedReq_mshr_misses::cpu1.data 1 # number of ReadSharedReq MSHR misses
1434 system.l2c.ReadSharedReq_mshr_misses::cpu2.data 8 # number of ReadSharedReq MSHR misses
1435 system.l2c.ReadSharedReq_mshr_misses::cpu3.data 1 # number of ReadSharedReq MSHR misses
1436 system.l2c.ReadSharedReq_mshr_misses::total 76 # number of ReadSharedReq MSHR misses
1437 system.l2c.demand_mshr_misses::cpu0.inst 285 # number of demand (read+write) MSHR misses
1438 system.l2c.demand_mshr_misses::cpu0.data 165 # number of demand (read+write) MSHR misses
1439 system.l2c.demand_mshr_misses::cpu1.inst 7 # number of demand (read+write) MSHR misses
1440 system.l2c.demand_mshr_misses::cpu1.data 15 # number of demand (read+write) MSHR misses
1441 system.l2c.demand_mshr_misses::cpu2.inst 58 # number of demand (read+write) MSHR misses
1442 system.l2c.demand_mshr_misses::cpu2.data 23 # number of demand (read+write) MSHR misses
1443 system.l2c.demand_mshr_misses::cpu3.inst 4 # number of demand (read+write) MSHR misses
1444 system.l2c.demand_mshr_misses::cpu3.data 15 # number of demand (read+write) MSHR misses
1445 system.l2c.demand_mshr_misses::total 572 # number of demand (read+write) MSHR misses
1446 system.l2c.overall_mshr_misses::cpu0.inst 285 # number of overall MSHR misses
1447 system.l2c.overall_mshr_misses::cpu0.data 165 # number of overall MSHR misses
1448 system.l2c.overall_mshr_misses::cpu1.inst 7 # number of overall MSHR misses
1449 system.l2c.overall_mshr_misses::cpu1.data 15 # number of overall MSHR misses
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1451 system.l2c.overall_mshr_misses::cpu2.data 23 # number of overall MSHR misses
1452 system.l2c.overall_mshr_misses::cpu3.inst 4 # number of overall MSHR misses
1453 system.l2c.overall_mshr_misses::cpu3.data 15 # number of overall MSHR misses
1454 system.l2c.overall_mshr_misses::total 572 # number of overall MSHR misses
1455 system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 1418500 # number of UpgradeReq MSHR miss cycles
1456 system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 762498 # number of UpgradeReq MSHR miss cycles
1457 system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 864497 # number of UpgradeReq MSHR miss cycles
1458 system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 813997 # number of UpgradeReq MSHR miss cycles
1459 system.l2c.UpgradeReq_mshr_miss_latency::total 3859492 # number of UpgradeReq MSHR miss cycles
1460 system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4902000 # number of ReadExReq MSHR miss cycles
1461 system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 702000 # number of ReadExReq MSHR miss cycles
1462 system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 746000 # number of ReadExReq MSHR miss cycles
1463 system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 700000 # number of ReadExReq MSHR miss cycles
1464 system.l2c.ReadExReq_mshr_miss_latency::total 7050000 # number of ReadExReq MSHR miss cycles
1465 system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 14114000 # number of ReadCleanReq MSHR miss cycles
1466 system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 351500 # number of ReadCleanReq MSHR miss cycles
1467 system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst 2872000 # number of ReadCleanReq MSHR miss cycles
1468 system.l2c.ReadCleanReq_mshr_miss_latency::cpu3.inst 199000 # number of ReadCleanReq MSHR miss cycles
1469 system.l2c.ReadCleanReq_mshr_miss_latency::total 17536500 # number of ReadCleanReq MSHR miss cycles
1470 system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 3267500 # number of ReadSharedReq MSHR miss cycles
1471 system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 49500 # number of ReadSharedReq MSHR miss cycles
1472 system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data 396000 # number of ReadSharedReq MSHR miss cycles
1473 system.l2c.ReadSharedReq_mshr_miss_latency::cpu3.data 49500 # number of ReadSharedReq MSHR miss cycles
1474 system.l2c.ReadSharedReq_mshr_miss_latency::total 3762500 # number of ReadSharedReq MSHR miss cycles
1475 system.l2c.demand_mshr_miss_latency::cpu0.inst 14114000 # number of demand (read+write) MSHR miss cycles
1476 system.l2c.demand_mshr_miss_latency::cpu0.data 8169500 # number of demand (read+write) MSHR miss cycles
1477 system.l2c.demand_mshr_miss_latency::cpu1.inst 351500 # number of demand (read+write) MSHR miss cycles
1478 system.l2c.demand_mshr_miss_latency::cpu1.data 751500 # number of demand (read+write) MSHR miss cycles
1479 system.l2c.demand_mshr_miss_latency::cpu2.inst 2872000 # number of demand (read+write) MSHR miss cycles
1480 system.l2c.demand_mshr_miss_latency::cpu2.data 1142000 # number of demand (read+write) MSHR miss cycles
1481 system.l2c.demand_mshr_miss_latency::cpu3.inst 199000 # number of demand (read+write) MSHR miss cycles
1482 system.l2c.demand_mshr_miss_latency::cpu3.data 749500 # number of demand (read+write) MSHR miss cycles
1483 system.l2c.demand_mshr_miss_latency::total 28349000 # number of demand (read+write) MSHR miss cycles
1484 system.l2c.overall_mshr_miss_latency::cpu0.inst 14114000 # number of overall MSHR miss cycles
1485 system.l2c.overall_mshr_miss_latency::cpu0.data 8169500 # number of overall MSHR miss cycles
1486 system.l2c.overall_mshr_miss_latency::cpu1.inst 351500 # number of overall MSHR miss cycles
1487 system.l2c.overall_mshr_miss_latency::cpu1.data 751500 # number of overall MSHR miss cycles
1488 system.l2c.overall_mshr_miss_latency::cpu2.inst 2872000 # number of overall MSHR miss cycles
1489 system.l2c.overall_mshr_miss_latency::cpu2.data 1142000 # number of overall MSHR miss cycles
1490 system.l2c.overall_mshr_miss_latency::cpu3.inst 199000 # number of overall MSHR miss cycles
1491 system.l2c.overall_mshr_miss_latency::cpu3.data 749500 # number of overall MSHR miss cycles
1492 system.l2c.overall_mshr_miss_latency::total 28349000 # number of overall MSHR miss cycles
1493 system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.933333 # mshr miss rate for UpgradeReq accesses
1494 system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses
1495 system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses
1496 system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses
1497 system.l2c.UpgradeReq_mshr_miss_rate::total 0.974359 # mshr miss rate for UpgradeReq accesses
1498 system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses
1499 system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses
1500 system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses
1501 system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses
1502 system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
1503 system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for ReadCleanReq accesses
1504 system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.019126 # mshr miss rate for ReadCleanReq accesses
1505 system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.158470 # mshr miss rate for ReadCleanReq accesses
1506 system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst 0.010899 # mshr miss rate for ReadCleanReq accesses
1507 system.l2c.ReadCleanReq_mshr_miss_rate::total 0.226054 # mshr miss rate for ReadCleanReq accesses
1508 system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.929577 # mshr miss rate for ReadSharedReq accesses
1509 system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.090909 # mshr miss rate for ReadSharedReq accesses
1510 system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.727273 # mshr miss rate for ReadSharedReq accesses
1511 system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data 0.090909 # mshr miss rate for ReadSharedReq accesses
1512 system.l2c.ReadSharedReq_mshr_miss_rate::total 0.730769 # mshr miss rate for ReadSharedReq accesses
1513 system.l2c.demand_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for demand accesses
1514 system.l2c.demand_mshr_miss_rate::cpu0.data 0.970588 # mshr miss rate for demand accesses
1515 system.l2c.demand_mshr_miss_rate::cpu1.inst 0.019126 # mshr miss rate for demand accesses
1516 system.l2c.demand_mshr_miss_rate::cpu1.data 0.600000 # mshr miss rate for demand accesses
1517 system.l2c.demand_mshr_miss_rate::cpu2.inst 0.158470 # mshr miss rate for demand accesses
1518 system.l2c.demand_mshr_miss_rate::cpu2.data 0.884615 # mshr miss rate for demand accesses
1519 system.l2c.demand_mshr_miss_rate::cpu3.inst 0.010899 # mshr miss rate for demand accesses
1520 system.l2c.demand_mshr_miss_rate::cpu3.data 0.600000 # mshr miss rate for demand accesses
1521 system.l2c.demand_mshr_miss_rate::total 0.315673 # mshr miss rate for demand accesses
1522 system.l2c.overall_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for overall accesses
1523 system.l2c.overall_mshr_miss_rate::cpu0.data 0.970588 # mshr miss rate for overall accesses
1524 system.l2c.overall_mshr_miss_rate::cpu1.inst 0.019126 # mshr miss rate for overall accesses
1525 system.l2c.overall_mshr_miss_rate::cpu1.data 0.600000 # mshr miss rate for overall accesses
1526 system.l2c.overall_mshr_miss_rate::cpu2.inst 0.158470 # mshr miss rate for overall accesses
1527 system.l2c.overall_mshr_miss_rate::cpu2.data 0.884615 # mshr miss rate for overall accesses
1528 system.l2c.overall_mshr_miss_rate::cpu3.inst 0.010899 # mshr miss rate for overall accesses
1529 system.l2c.overall_mshr_miss_rate::cpu3.data 0.600000 # mshr miss rate for overall accesses
1530 system.l2c.overall_mshr_miss_rate::total 0.315673 # mshr miss rate for overall accesses
1531 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 50660.714286 # average UpgradeReq mshr miss latency
1532 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 50833.200000 # average UpgradeReq mshr miss latency
1533 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 50852.764706 # average UpgradeReq mshr miss latency
1534 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 50874.812500 # average UpgradeReq mshr miss latency
1535 system.l2c.UpgradeReq_avg_mshr_miss_latency::total 50782.789474 # average UpgradeReq mshr miss latency
1536 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 49515.151515 # average ReadExReq mshr miss latency
1537 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 50142.857143 # average ReadExReq mshr miss latency
1538 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 49733.333333 # average ReadExReq mshr miss latency
1539 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 50000 # average ReadExReq mshr miss latency
1540 system.l2c.ReadExReq_avg_mshr_miss_latency::total 49647.887324 # average ReadExReq mshr miss latency
1541 system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 49522.807018 # average ReadCleanReq mshr miss latency
1542 system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 50214.285714 # average ReadCleanReq mshr miss latency
1543 system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 49517.241379 # average ReadCleanReq mshr miss latency
1544 system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 49750 # average ReadCleanReq mshr miss latency
1545 system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 49538.135593 # average ReadCleanReq mshr miss latency
1546 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 49507.575758 # average ReadSharedReq mshr miss latency
1547 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 49500 # average ReadSharedReq mshr miss latency
1548 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 49500 # average ReadSharedReq mshr miss latency
1549 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 49500 # average ReadSharedReq mshr miss latency
1550 system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 49506.578947 # average ReadSharedReq mshr miss latency
1551 system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 49522.807018 # average overall mshr miss latency
1552 system.l2c.demand_avg_mshr_miss_latency::cpu0.data 49512.121212 # average overall mshr miss latency
1553 system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 50214.285714 # average overall mshr miss latency
1554 system.l2c.demand_avg_mshr_miss_latency::cpu1.data 50100 # average overall mshr miss latency
1555 system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 49517.241379 # average overall mshr miss latency
1556 system.l2c.demand_avg_mshr_miss_latency::cpu2.data 49652.173913 # average overall mshr miss latency
1557 system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 49750 # average overall mshr miss latency
1558 system.l2c.demand_avg_mshr_miss_latency::cpu3.data 49966.666667 # average overall mshr miss latency
1559 system.l2c.demand_avg_mshr_miss_latency::total 49561.188811 # average overall mshr miss latency
1560 system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 49522.807018 # average overall mshr miss latency
1561 system.l2c.overall_avg_mshr_miss_latency::cpu0.data 49512.121212 # average overall mshr miss latency
1562 system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 50214.285714 # average overall mshr miss latency
1563 system.l2c.overall_avg_mshr_miss_latency::cpu1.data 50100 # average overall mshr miss latency
1564 system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 49517.241379 # average overall mshr miss latency
1565 system.l2c.overall_avg_mshr_miss_latency::cpu2.data 49652.173913 # average overall mshr miss latency
1566 system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 49750 # average overall mshr miss latency
1567 system.l2c.overall_avg_mshr_miss_latency::cpu3.data 49966.666667 # average overall mshr miss latency
1568 system.l2c.overall_avg_mshr_miss_latency::total 49561.188811 # average overall mshr miss latency
1569 system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
1570 system.membus.trans_dist::ReadResp 430 # Transaction distribution
1571 system.membus.trans_dist::UpgradeReq 271 # Transaction distribution
1572 system.membus.trans_dist::UpgradeResp 76 # Transaction distribution
1573 system.membus.trans_dist::ReadExReq 208 # Transaction distribution
1574 system.membus.trans_dist::ReadExResp 142 # Transaction distribution
1575 system.membus.trans_dist::ReadSharedReq 430 # Transaction distribution
1576 system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1557 # Packet count per connected master and slave (bytes)
1577 system.membus.pkt_count::total 1557 # Packet count per connected master and slave (bytes)
1578 system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 36608 # Cumulative packet size per connected master and slave (bytes)
1579 system.membus.pkt_size::total 36608 # Cumulative packet size per connected master and slave (bytes)
1580 system.membus.snoops 261 # Total snoops (count)
1581 system.membus.snoop_fanout::samples 915 # Request fanout histogram
1582 system.membus.snoop_fanout::mean 0 # Request fanout histogram
1583 system.membus.snoop_fanout::stdev 0 # Request fanout histogram
1584 system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1585 system.membus.snoop_fanout::0 915 100.00% 100.00% # Request fanout histogram
1586 system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
1587 system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1588 system.membus.snoop_fanout::min_value 0 # Request fanout histogram
1589 system.membus.snoop_fanout::max_value 0 # Request fanout histogram
1590 system.membus.snoop_fanout::total 915 # Request fanout histogram
1591 system.membus.reqLayer0.occupancy 677632 # Layer occupancy (ticks)
1592 system.membus.reqLayer0.utilization 0.3 # Layer utilization (%)
1593 system.membus.respLayer1.occupancy 2936000 # Layer occupancy (ticks)
1594 system.membus.respLayer1.utilization 1.1 # Layer utilization (%)
1595 system.toL2Bus.snoop_filter.tot_requests 3980 # Total number of requests made to the snoop filter.
1596 system.toL2Bus.snoop_filter.hit_single_requests 1113 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1597 system.toL2Bus.snoop_filter.hit_multi_requests 1865 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1598 system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
1599 system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1600 system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1601 system.toL2Bus.trans_dist::ReadResp 2221 # Transaction distribution
1602 system.toL2Bus.trans_dist::WritebackDirty 1 # Transaction distribution
1603 system.toL2Bus.trans_dist::WritebackClean 495 # Transaction distribution
1604 system.toL2Bus.trans_dist::CleanEvict 1 # Transaction distribution
1605 system.toL2Bus.trans_dist::UpgradeReq 273 # Transaction distribution
1606 system.toL2Bus.trans_dist::UpgradeResp 273 # Transaction distribution
1607 system.toL2Bus.trans_dist::ReadExReq 428 # Transaction distribution
1608 system.toL2Bus.trans_dist::ReadExResp 428 # Transaction distribution
1609 system.toL2Bus.trans_dist::ReadCleanReq 1566 # Transaction distribution
1610 system.toL2Bus.trans_dist::ReadSharedReq 655 # Transaction distribution
1611 system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1077 # Packet count per connected master and slave (bytes)
1612 system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 579 # Packet count per connected master and slave (bytes)
1613 system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 849 # Packet count per connected master and slave (bytes)
1614 system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 365 # Packet count per connected master and slave (bytes)
1615 system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 849 # Packet count per connected master and slave (bytes)
1616 system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 372 # Packet count per connected master and slave (bytes)
1617 system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 852 # Packet count per connected master and slave (bytes)
1618 system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 366 # Packet count per connected master and slave (bytes)
1619 system.toL2Bus.pkt_count::total 5309 # Packet count per connected master and slave (bytes)
1620 system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 39040 # Cumulative packet size per connected master and slave (bytes)
1621 system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 10944 # Cumulative packet size per connected master and slave (bytes)
1622 system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 30912 # Cumulative packet size per connected master and slave (bytes)
1623 system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes)
1624 system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 30912 # Cumulative packet size per connected master and slave (bytes)
1625 system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1664 # Cumulative packet size per connected master and slave (bytes)
1626 system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 31040 # Cumulative packet size per connected master and slave (bytes)
1627 system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes)
1628 system.toL2Bus.pkt_size::total 147712 # Cumulative packet size per connected master and slave (bytes)
1629 system.toL2Bus.snoops 1032 # Total snoops (count)
1630 system.toL2Bus.snoop_fanout::samples 2922 # Request fanout histogram
1631 system.toL2Bus.snoop_fanout::mean 1.269678 # Request fanout histogram
1632 system.toL2Bus.snoop_fanout::stdev 1.154527 # Request fanout histogram
1633 system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1634 system.toL2Bus.snoop_fanout::0 1002 34.29% 34.29% # Request fanout histogram
1635 system.toL2Bus.snoop_fanout::1 787 26.93% 61.23% # Request fanout histogram
1636 system.toL2Bus.snoop_fanout::2 476 16.29% 77.52% # Request fanout histogram
1637 system.toL2Bus.snoop_fanout::3 657 22.48% 100.00% # Request fanout histogram
1638 system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
1639 system.toL2Bus.snoop_fanout::5 0 0.00% 100.00% # Request fanout histogram
1640 system.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
1641 system.toL2Bus.snoop_fanout::7 0 0.00% 100.00% # Request fanout histogram
1642 system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram
1643 system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1644 system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
1645 system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
1646 system.toL2Bus.snoop_fanout::total 2922 # Request fanout histogram
1647 system.toL2Bus.reqLayer0.occupancy 3050992 # Layer occupancy (ticks)
1648 system.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%)
1649 system.toL2Bus.respLayer0.occupancy 700999 # Layer occupancy (ticks)
1650 system.toL2Bus.respLayer0.utilization 0.3 # Layer utilization (%)
1651 system.toL2Bus.respLayer1.occupancy 495500 # Layer occupancy (ticks)
1652 system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
1653 system.toL2Bus.respLayer2.occupancy 552489 # Layer occupancy (ticks)
1654 system.toL2Bus.respLayer2.utilization 0.2 # Layer utilization (%)
1655 system.toL2Bus.respLayer3.occupancy 432972 # Layer occupancy (ticks)
1656 system.toL2Bus.respLayer3.utilization 0.2 # Layer utilization (%)
1657 system.toL2Bus.respLayer4.occupancy 552491 # Layer occupancy (ticks)
1658 system.toL2Bus.respLayer4.utilization 0.2 # Layer utilization (%)
1659 system.toL2Bus.respLayer5.occupancy 434474 # Layer occupancy (ticks)
1660 system.toL2Bus.respLayer5.utilization 0.2 # Layer utilization (%)
1661 system.toL2Bus.respLayer6.occupancy 553492 # Layer occupancy (ticks)
1662 system.toL2Bus.respLayer6.utilization 0.2 # Layer utilization (%)
1663 system.toL2Bus.respLayer7.occupancy 427974 # Layer occupancy (ticks)
1664 system.toL2Bus.respLayer7.utilization 0.2 # Layer utilization (%)
1666 ---------- End Simulation Statistics ----------
projects / gem5.git / blob