2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.000262 # Number of seconds simulated
4 sim_ticks 262299000 # Number of ticks simulated
5 final_tick 262299000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 1271827 # Simulator instruction rate (inst/s)
8 host_op_rate 1271784 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 503510999 # Simulator tick rate (ticks/s)
10 host_mem_usage 230932 # Number of bytes of host memory used
11 host_seconds 0.52 # Real time elapsed on the host
12 sim_insts 662502 # Number of instructions simulated
13 sim_ops 662502 # Number of ops (including micro ops) simulated
14 system.physmem.bytes_read::cpu0.inst 18240 # Number of bytes read from this memory
15 system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory
16 system.physmem.bytes_read::cpu1.inst 3776 # Number of bytes read from this memory
17 system.physmem.bytes_read::cpu1.data 1408 # Number of bytes read from this memory
18 system.physmem.bytes_read::cpu2.inst 576 # Number of bytes read from this memory
19 system.physmem.bytes_read::cpu2.data 1024 # Number of bytes read from this memory
20 system.physmem.bytes_read::cpu3.inst 64 # Number of bytes read from this memory
21 system.physmem.bytes_read::cpu3.data 960 # Number of bytes read from this memory
22 system.physmem.bytes_read::total 36608 # Number of bytes read from this memory
23 system.physmem.bytes_inst_read::cpu0.inst 18240 # Number of instructions bytes read from this memory
24 system.physmem.bytes_inst_read::cpu1.inst 3776 # Number of instructions bytes read from this memory
25 system.physmem.bytes_inst_read::cpu2.inst 576 # Number of instructions bytes read from this memory
26 system.physmem.bytes_inst_read::cpu3.inst 64 # Number of instructions bytes read from this memory
27 system.physmem.bytes_inst_read::total 22656 # Number of instructions bytes read from this memory
28 system.physmem.num_reads::cpu0.inst 285 # Number of read requests responded to by this memory
29 system.physmem.num_reads::cpu0.data 165 # Number of read requests responded to by this memory
30 system.physmem.num_reads::cpu1.inst 59 # Number of read requests responded to by this memory
31 system.physmem.num_reads::cpu1.data 22 # Number of read requests responded to by this memory
32 system.physmem.num_reads::cpu2.inst 9 # Number of read requests responded to by this memory
33 system.physmem.num_reads::cpu2.data 16 # Number of read requests responded to by this memory
34 system.physmem.num_reads::cpu3.inst 1 # Number of read requests responded to by this memory
35 system.physmem.num_reads::cpu3.data 15 # Number of read requests responded to by this memory
36 system.physmem.num_reads::total 572 # Number of read requests responded to by this memory
37 system.physmem.bw_read::cpu0.inst 69538961 # Total read bandwidth from this memory (bytes/s)
38 system.physmem.bw_read::cpu0.data 40259399 # Total read bandwidth from this memory (bytes/s)
39 system.physmem.bw_read::cpu1.inst 14395785 # Total read bandwidth from this memory (bytes/s)
40 system.physmem.bw_read::cpu1.data 5367920 # Total read bandwidth from this memory (bytes/s)
41 system.physmem.bw_read::cpu2.inst 2195967 # Total read bandwidth from this memory (bytes/s)
42 system.physmem.bw_read::cpu2.data 3903942 # Total read bandwidth from this memory (bytes/s)
43 system.physmem.bw_read::cpu3.inst 243996 # Total read bandwidth from this memory (bytes/s)
44 system.physmem.bw_read::cpu3.data 3659945 # Total read bandwidth from this memory (bytes/s)
45 system.physmem.bw_read::total 139565915 # Total read bandwidth from this memory (bytes/s)
46 system.physmem.bw_inst_read::cpu0.inst 69538961 # Instruction read bandwidth from this memory (bytes/s)
47 system.physmem.bw_inst_read::cpu1.inst 14395785 # Instruction read bandwidth from this memory (bytes/s)
48 system.physmem.bw_inst_read::cpu2.inst 2195967 # Instruction read bandwidth from this memory (bytes/s)
49 system.physmem.bw_inst_read::cpu3.inst 243996 # Instruction read bandwidth from this memory (bytes/s)
50 system.physmem.bw_inst_read::total 86374710 # Instruction read bandwidth from this memory (bytes/s)
51 system.physmem.bw_total::cpu0.inst 69538961 # Total bandwidth to/from this memory (bytes/s)
52 system.physmem.bw_total::cpu0.data 40259399 # Total bandwidth to/from this memory (bytes/s)
53 system.physmem.bw_total::cpu1.inst 14395785 # Total bandwidth to/from this memory (bytes/s)
54 system.physmem.bw_total::cpu1.data 5367920 # Total bandwidth to/from this memory (bytes/s)
55 system.physmem.bw_total::cpu2.inst 2195967 # Total bandwidth to/from this memory (bytes/s)
56 system.physmem.bw_total::cpu2.data 3903942 # Total bandwidth to/from this memory (bytes/s)
57 system.physmem.bw_total::cpu3.inst 243996 # Total bandwidth to/from this memory (bytes/s)
58 system.physmem.bw_total::cpu3.data 3659945 # Total bandwidth to/from this memory (bytes/s)
59 system.physmem.bw_total::total 139565915 # Total bandwidth to/from this memory (bytes/s)
60 system.cpu0.workload.num_syscalls 89 # Number of system calls
61 system.cpu0.numCycles 524598 # number of cpu cycles simulated
62 system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
63 system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
64 system.cpu0.committedInsts 158353 # Number of instructions committed
65 system.cpu0.committedOps 158353 # Number of ops (including micro ops) committed
66 system.cpu0.num_int_alu_accesses 109064 # Number of integer alu accesses
67 system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses
68 system.cpu0.num_func_calls 390 # number of times a function call or return occured
69 system.cpu0.num_conditional_control_insts 25994 # number of instructions that are conditional controls
70 system.cpu0.num_int_insts 109064 # number of integer instructions
71 system.cpu0.num_fp_insts 0 # number of float instructions
72 system.cpu0.num_int_register_reads 315336 # number of times the integer registers were read
73 system.cpu0.num_int_register_writes 110671 # number of times the integer registers were written
74 system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read
75 system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written
76 system.cpu0.num_mem_refs 73905 # number of memory refs
77 system.cpu0.num_load_insts 48930 # Number of load instructions
78 system.cpu0.num_store_insts 24975 # Number of store instructions
79 system.cpu0.num_idle_cycles 0 # Number of idle cycles
80 system.cpu0.num_busy_cycles 524598 # Number of busy cycles
81 system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles
82 system.cpu0.idle_fraction 0 # Percentage of idle cycles
83 system.cpu0.icache.replacements 215 # number of replacements
84 system.cpu0.icache.tagsinuse 212.479251 # Cycle average of tags in use
85 system.cpu0.icache.total_refs 157949 # Total number of references to valid blocks.
86 system.cpu0.icache.sampled_refs 467 # Sample count of references to valid blocks.
87 system.cpu0.icache.avg_refs 338.220557 # Average number of references to valid blocks.
88 system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
89 system.cpu0.icache.occ_blocks::cpu0.inst 212.479251 # Average occupied blocks per requestor
90 system.cpu0.icache.occ_percent::cpu0.inst 0.414999 # Average percentage of cache occupancy
91 system.cpu0.icache.occ_percent::total 0.414999 # Average percentage of cache occupancy
92 system.cpu0.icache.ReadReq_hits::cpu0.inst 157949 # number of ReadReq hits
93 system.cpu0.icache.ReadReq_hits::total 157949 # number of ReadReq hits
94 system.cpu0.icache.demand_hits::cpu0.inst 157949 # number of demand (read+write) hits
95 system.cpu0.icache.demand_hits::total 157949 # number of demand (read+write) hits
96 system.cpu0.icache.overall_hits::cpu0.inst 157949 # number of overall hits
97 system.cpu0.icache.overall_hits::total 157949 # number of overall hits
98 system.cpu0.icache.ReadReq_misses::cpu0.inst 467 # number of ReadReq misses
99 system.cpu0.icache.ReadReq_misses::total 467 # number of ReadReq misses
100 system.cpu0.icache.demand_misses::cpu0.inst 467 # number of demand (read+write) misses
101 system.cpu0.icache.demand_misses::total 467 # number of demand (read+write) misses
102 system.cpu0.icache.overall_misses::cpu0.inst 467 # number of overall misses
103 system.cpu0.icache.overall_misses::total 467 # number of overall misses
104 system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 18524000 # number of ReadReq miss cycles
105 system.cpu0.icache.ReadReq_miss_latency::total 18524000 # number of ReadReq miss cycles
106 system.cpu0.icache.demand_miss_latency::cpu0.inst 18524000 # number of demand (read+write) miss cycles
107 system.cpu0.icache.demand_miss_latency::total 18524000 # number of demand (read+write) miss cycles
108 system.cpu0.icache.overall_miss_latency::cpu0.inst 18524000 # number of overall miss cycles
109 system.cpu0.icache.overall_miss_latency::total 18524000 # number of overall miss cycles
110 system.cpu0.icache.ReadReq_accesses::cpu0.inst 158416 # number of ReadReq accesses(hits+misses)
111 system.cpu0.icache.ReadReq_accesses::total 158416 # number of ReadReq accesses(hits+misses)
112 system.cpu0.icache.demand_accesses::cpu0.inst 158416 # number of demand (read+write) accesses
113 system.cpu0.icache.demand_accesses::total 158416 # number of demand (read+write) accesses
114 system.cpu0.icache.overall_accesses::cpu0.inst 158416 # number of overall (read+write) accesses
115 system.cpu0.icache.overall_accesses::total 158416 # number of overall (read+write) accesses
116 system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002948 # miss rate for ReadReq accesses
117 system.cpu0.icache.ReadReq_miss_rate::total 0.002948 # miss rate for ReadReq accesses
118 system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002948 # miss rate for demand accesses
119 system.cpu0.icache.demand_miss_rate::total 0.002948 # miss rate for demand accesses
120 system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002948 # miss rate for overall accesses
121 system.cpu0.icache.overall_miss_rate::total 0.002948 # miss rate for overall accesses
122 system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 39665.952891 # average ReadReq miss latency
123 system.cpu0.icache.ReadReq_avg_miss_latency::total 39665.952891 # average ReadReq miss latency
124 system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 39665.952891 # average overall miss latency
125 system.cpu0.icache.demand_avg_miss_latency::total 39665.952891 # average overall miss latency
126 system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 39665.952891 # average overall miss latency
127 system.cpu0.icache.overall_avg_miss_latency::total 39665.952891 # average overall miss latency
128 system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
129 system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
130 system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
131 system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
132 system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
133 system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
134 system.cpu0.icache.fast_writes 0 # number of fast writes performed
135 system.cpu0.icache.cache_copies 0 # number of cache copies performed
136 system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 467 # number of ReadReq MSHR misses
137 system.cpu0.icache.ReadReq_mshr_misses::total 467 # number of ReadReq MSHR misses
138 system.cpu0.icache.demand_mshr_misses::cpu0.inst 467 # number of demand (read+write) MSHR misses
139 system.cpu0.icache.demand_mshr_misses::total 467 # number of demand (read+write) MSHR misses
140 system.cpu0.icache.overall_mshr_misses::cpu0.inst 467 # number of overall MSHR misses
141 system.cpu0.icache.overall_mshr_misses::total 467 # number of overall MSHR misses
142 system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 17123000 # number of ReadReq MSHR miss cycles
143 system.cpu0.icache.ReadReq_mshr_miss_latency::total 17123000 # number of ReadReq MSHR miss cycles
144 system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 17123000 # number of demand (read+write) MSHR miss cycles
145 system.cpu0.icache.demand_mshr_miss_latency::total 17123000 # number of demand (read+write) MSHR miss cycles
146 system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 17123000 # number of overall MSHR miss cycles
147 system.cpu0.icache.overall_mshr_miss_latency::total 17123000 # number of overall MSHR miss cycles
148 system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.002948 # mshr miss rate for ReadReq accesses
149 system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.002948 # mshr miss rate for ReadReq accesses
150 system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.002948 # mshr miss rate for demand accesses
151 system.cpu0.icache.demand_mshr_miss_rate::total 0.002948 # mshr miss rate for demand accesses
152 system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.002948 # mshr miss rate for overall accesses
153 system.cpu0.icache.overall_mshr_miss_rate::total 0.002948 # mshr miss rate for overall accesses
154 system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36665.952891 # average ReadReq mshr miss latency
155 system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 36665.952891 # average ReadReq mshr miss latency
156 system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 36665.952891 # average overall mshr miss latency
157 system.cpu0.icache.demand_avg_mshr_miss_latency::total 36665.952891 # average overall mshr miss latency
158 system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 36665.952891 # average overall mshr miss latency
159 system.cpu0.icache.overall_avg_mshr_miss_latency::total 36665.952891 # average overall mshr miss latency
160 system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
161 system.cpu0.dcache.replacements 2 # number of replacements
162 system.cpu0.dcache.tagsinuse 145.603716 # Cycle average of tags in use
163 system.cpu0.dcache.total_refs 73381 # Total number of references to valid blocks.
164 system.cpu0.dcache.sampled_refs 167 # Sample count of references to valid blocks.
165 system.cpu0.dcache.avg_refs 439.407186 # Average number of references to valid blocks.
166 system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
167 system.cpu0.dcache.occ_blocks::cpu0.data 145.603716 # Average occupied blocks per requestor
168 system.cpu0.dcache.occ_percent::cpu0.data 0.284382 # Average percentage of cache occupancy
169 system.cpu0.dcache.occ_percent::total 0.284382 # Average percentage of cache occupancy
170 system.cpu0.dcache.ReadReq_hits::cpu0.data 48758 # number of ReadReq hits
171 system.cpu0.dcache.ReadReq_hits::total 48758 # number of ReadReq hits
172 system.cpu0.dcache.WriteReq_hits::cpu0.data 24741 # number of WriteReq hits
173 system.cpu0.dcache.WriteReq_hits::total 24741 # number of WriteReq hits
174 system.cpu0.dcache.SwapReq_hits::cpu0.data 16 # number of SwapReq hits
175 system.cpu0.dcache.SwapReq_hits::total 16 # number of SwapReq hits
176 system.cpu0.dcache.demand_hits::cpu0.data 73499 # number of demand (read+write) hits
177 system.cpu0.dcache.demand_hits::total 73499 # number of demand (read+write) hits
178 system.cpu0.dcache.overall_hits::cpu0.data 73499 # number of overall hits
179 system.cpu0.dcache.overall_hits::total 73499 # number of overall hits
180 system.cpu0.dcache.ReadReq_misses::cpu0.data 162 # number of ReadReq misses
181 system.cpu0.dcache.ReadReq_misses::total 162 # number of ReadReq misses
182 system.cpu0.dcache.WriteReq_misses::cpu0.data 183 # number of WriteReq misses
183 system.cpu0.dcache.WriteReq_misses::total 183 # number of WriteReq misses
184 system.cpu0.dcache.SwapReq_misses::cpu0.data 26 # number of SwapReq misses
185 system.cpu0.dcache.SwapReq_misses::total 26 # number of SwapReq misses
186 system.cpu0.dcache.demand_misses::cpu0.data 345 # number of demand (read+write) misses
187 system.cpu0.dcache.demand_misses::total 345 # number of demand (read+write) misses
188 system.cpu0.dcache.overall_misses::cpu0.data 345 # number of overall misses
189 system.cpu0.dcache.overall_misses::total 345 # number of overall misses
190 system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4747000 # number of ReadReq miss cycles
191 system.cpu0.dcache.ReadReq_miss_latency::total 4747000 # number of ReadReq miss cycles
192 system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7176000 # number of WriteReq miss cycles
193 system.cpu0.dcache.WriteReq_miss_latency::total 7176000 # number of WriteReq miss cycles
194 system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 389000 # number of SwapReq miss cycles
195 system.cpu0.dcache.SwapReq_miss_latency::total 389000 # number of SwapReq miss cycles
196 system.cpu0.dcache.demand_miss_latency::cpu0.data 11923000 # number of demand (read+write) miss cycles
197 system.cpu0.dcache.demand_miss_latency::total 11923000 # number of demand (read+write) miss cycles
198 system.cpu0.dcache.overall_miss_latency::cpu0.data 11923000 # number of overall miss cycles
199 system.cpu0.dcache.overall_miss_latency::total 11923000 # number of overall miss cycles
200 system.cpu0.dcache.ReadReq_accesses::cpu0.data 48920 # number of ReadReq accesses(hits+misses)
201 system.cpu0.dcache.ReadReq_accesses::total 48920 # number of ReadReq accesses(hits+misses)
202 system.cpu0.dcache.WriteReq_accesses::cpu0.data 24924 # number of WriteReq accesses(hits+misses)
203 system.cpu0.dcache.WriteReq_accesses::total 24924 # number of WriteReq accesses(hits+misses)
204 system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses)
205 system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses)
206 system.cpu0.dcache.demand_accesses::cpu0.data 73844 # number of demand (read+write) accesses
207 system.cpu0.dcache.demand_accesses::total 73844 # number of demand (read+write) accesses
208 system.cpu0.dcache.overall_accesses::cpu0.data 73844 # number of overall (read+write) accesses
209 system.cpu0.dcache.overall_accesses::total 73844 # number of overall (read+write) accesses
210 system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.003312 # miss rate for ReadReq accesses
211 system.cpu0.dcache.ReadReq_miss_rate::total 0.003312 # miss rate for ReadReq accesses
212 system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007342 # miss rate for WriteReq accesses
213 system.cpu0.dcache.WriteReq_miss_rate::total 0.007342 # miss rate for WriteReq accesses
214 system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.619048 # miss rate for SwapReq accesses
215 system.cpu0.dcache.SwapReq_miss_rate::total 0.619048 # miss rate for SwapReq accesses
216 system.cpu0.dcache.demand_miss_rate::cpu0.data 0.004672 # miss rate for demand accesses
217 system.cpu0.dcache.demand_miss_rate::total 0.004672 # miss rate for demand accesses
218 system.cpu0.dcache.overall_miss_rate::cpu0.data 0.004672 # miss rate for overall accesses
219 system.cpu0.dcache.overall_miss_rate::total 0.004672 # miss rate for overall accesses
220 system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 29302.469136 # average ReadReq miss latency
221 system.cpu0.dcache.ReadReq_avg_miss_latency::total 29302.469136 # average ReadReq miss latency
222 system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 39213.114754 # average WriteReq miss latency
223 system.cpu0.dcache.WriteReq_avg_miss_latency::total 39213.114754 # average WriteReq miss latency
224 system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 14961.538462 # average SwapReq miss latency
225 system.cpu0.dcache.SwapReq_avg_miss_latency::total 14961.538462 # average SwapReq miss latency
226 system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 34559.420290 # average overall miss latency
227 system.cpu0.dcache.demand_avg_miss_latency::total 34559.420290 # average overall miss latency
228 system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 34559.420290 # average overall miss latency
229 system.cpu0.dcache.overall_avg_miss_latency::total 34559.420290 # average overall miss latency
230 system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
231 system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
232 system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
233 system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
234 system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
235 system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
236 system.cpu0.dcache.fast_writes 0 # number of fast writes performed
237 system.cpu0.dcache.cache_copies 0 # number of cache copies performed
238 system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks
239 system.cpu0.dcache.writebacks::total 1 # number of writebacks
240 system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 162 # number of ReadReq MSHR misses
241 system.cpu0.dcache.ReadReq_mshr_misses::total 162 # number of ReadReq MSHR misses
242 system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 183 # number of WriteReq MSHR misses
243 system.cpu0.dcache.WriteReq_mshr_misses::total 183 # number of WriteReq MSHR misses
244 system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 26 # number of SwapReq MSHR misses
245 system.cpu0.dcache.SwapReq_mshr_misses::total 26 # number of SwapReq MSHR misses
246 system.cpu0.dcache.demand_mshr_misses::cpu0.data 345 # number of demand (read+write) MSHR misses
247 system.cpu0.dcache.demand_mshr_misses::total 345 # number of demand (read+write) MSHR misses
248 system.cpu0.dcache.overall_mshr_misses::cpu0.data 345 # number of overall MSHR misses
249 system.cpu0.dcache.overall_mshr_misses::total 345 # number of overall MSHR misses
250 system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4261000 # number of ReadReq MSHR miss cycles
251 system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4261000 # number of ReadReq MSHR miss cycles
252 system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6627000 # number of WriteReq MSHR miss cycles
253 system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6627000 # number of WriteReq MSHR miss cycles
254 system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 311000 # number of SwapReq MSHR miss cycles
255 system.cpu0.dcache.SwapReq_mshr_miss_latency::total 311000 # number of SwapReq MSHR miss cycles
256 system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10888000 # number of demand (read+write) MSHR miss cycles
257 system.cpu0.dcache.demand_mshr_miss_latency::total 10888000 # number of demand (read+write) MSHR miss cycles
258 system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10888000 # number of overall MSHR miss cycles
259 system.cpu0.dcache.overall_mshr_miss_latency::total 10888000 # number of overall MSHR miss cycles
260 system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.003312 # mshr miss rate for ReadReq accesses
261 system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.003312 # mshr miss rate for ReadReq accesses
262 system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.007342 # mshr miss rate for WriteReq accesses
263 system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007342 # mshr miss rate for WriteReq accesses
264 system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.619048 # mshr miss rate for SwapReq accesses
265 system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.619048 # mshr miss rate for SwapReq accesses
266 system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.004672 # mshr miss rate for demand accesses
267 system.cpu0.dcache.demand_mshr_miss_rate::total 0.004672 # mshr miss rate for demand accesses
268 system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.004672 # mshr miss rate for overall accesses
269 system.cpu0.dcache.overall_mshr_miss_rate::total 0.004672 # mshr miss rate for overall accesses
270 system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26302.469136 # average ReadReq mshr miss latency
271 system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26302.469136 # average ReadReq mshr miss latency
272 system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36213.114754 # average WriteReq mshr miss latency
273 system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36213.114754 # average WriteReq mshr miss latency
274 system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 11961.538462 # average SwapReq mshr miss latency
275 system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 11961.538462 # average SwapReq mshr miss latency
276 system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31559.420290 # average overall mshr miss latency
277 system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31559.420290 # average overall mshr miss latency
278 system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31559.420290 # average overall mshr miss latency
279 system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31559.420290 # average overall mshr miss latency
280 system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
281 system.cpu1.numCycles 524598 # number of cpu cycles simulated
282 system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
283 system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
284 system.cpu1.committedInsts 172389 # Number of instructions committed
285 system.cpu1.committedOps 172389 # Number of ops (including micro ops) committed
286 system.cpu1.num_int_alu_accesses 107964 # Number of integer alu accesses
287 system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses
288 system.cpu1.num_func_calls 637 # number of times a function call or return occured
289 system.cpu1.num_conditional_control_insts 36219 # number of instructions that are conditional controls
290 system.cpu1.num_int_insts 107964 # number of integer instructions
291 system.cpu1.num_fp_insts 0 # number of float instructions
292 system.cpu1.num_int_register_reads 249169 # number of times the integer registers were read
293 system.cpu1.num_int_register_writes 92792 # number of times the integer registers were written
294 system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read
295 system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written
296 system.cpu1.num_mem_refs 47914 # number of memory refs
297 system.cpu1.num_load_insts 39632 # Number of load instructions
298 system.cpu1.num_store_insts 8282 # Number of store instructions
299 system.cpu1.num_idle_cycles 68732.001738 # Number of idle cycles
300 system.cpu1.num_busy_cycles 455865.998262 # Number of busy cycles
301 system.cpu1.not_idle_fraction 0.868982 # Percentage of non-idle cycles
302 system.cpu1.idle_fraction 0.131018 # Percentage of idle cycles
303 system.cpu1.icache.replacements 280 # number of replacements
304 system.cpu1.icache.tagsinuse 70.077944 # Cycle average of tags in use
305 system.cpu1.icache.total_refs 172056 # Total number of references to valid blocks.
306 system.cpu1.icache.sampled_refs 366 # Sample count of references to valid blocks.
307 system.cpu1.icache.avg_refs 470.098361 # Average number of references to valid blocks.
308 system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
309 system.cpu1.icache.occ_blocks::cpu1.inst 70.077944 # Average occupied blocks per requestor
310 system.cpu1.icache.occ_percent::cpu1.inst 0.136871 # Average percentage of cache occupancy
311 system.cpu1.icache.occ_percent::total 0.136871 # Average percentage of cache occupancy
312 system.cpu1.icache.ReadReq_hits::cpu1.inst 172056 # number of ReadReq hits
313 system.cpu1.icache.ReadReq_hits::total 172056 # number of ReadReq hits
314 system.cpu1.icache.demand_hits::cpu1.inst 172056 # number of demand (read+write) hits
315 system.cpu1.icache.demand_hits::total 172056 # number of demand (read+write) hits
316 system.cpu1.icache.overall_hits::cpu1.inst 172056 # number of overall hits
317 system.cpu1.icache.overall_hits::total 172056 # number of overall hits
318 system.cpu1.icache.ReadReq_misses::cpu1.inst 366 # number of ReadReq misses
319 system.cpu1.icache.ReadReq_misses::total 366 # number of ReadReq misses
320 system.cpu1.icache.demand_misses::cpu1.inst 366 # number of demand (read+write) misses
321 system.cpu1.icache.demand_misses::total 366 # number of demand (read+write) misses
322 system.cpu1.icache.overall_misses::cpu1.inst 366 # number of overall misses
323 system.cpu1.icache.overall_misses::total 366 # number of overall misses
324 system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7921500 # number of ReadReq miss cycles
325 system.cpu1.icache.ReadReq_miss_latency::total 7921500 # number of ReadReq miss cycles
326 system.cpu1.icache.demand_miss_latency::cpu1.inst 7921500 # number of demand (read+write) miss cycles
327 system.cpu1.icache.demand_miss_latency::total 7921500 # number of demand (read+write) miss cycles
328 system.cpu1.icache.overall_miss_latency::cpu1.inst 7921500 # number of overall miss cycles
329 system.cpu1.icache.overall_miss_latency::total 7921500 # number of overall miss cycles
330 system.cpu1.icache.ReadReq_accesses::cpu1.inst 172422 # number of ReadReq accesses(hits+misses)
331 system.cpu1.icache.ReadReq_accesses::total 172422 # number of ReadReq accesses(hits+misses)
332 system.cpu1.icache.demand_accesses::cpu1.inst 172422 # number of demand (read+write) accesses
333 system.cpu1.icache.demand_accesses::total 172422 # number of demand (read+write) accesses
334 system.cpu1.icache.overall_accesses::cpu1.inst 172422 # number of overall (read+write) accesses
335 system.cpu1.icache.overall_accesses::total 172422 # number of overall (read+write) accesses
336 system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002123 # miss rate for ReadReq accesses
337 system.cpu1.icache.ReadReq_miss_rate::total 0.002123 # miss rate for ReadReq accesses
338 system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002123 # miss rate for demand accesses
339 system.cpu1.icache.demand_miss_rate::total 0.002123 # miss rate for demand accesses
340 system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002123 # miss rate for overall accesses
341 system.cpu1.icache.overall_miss_rate::total 0.002123 # miss rate for overall accesses
342 system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 21643.442623 # average ReadReq miss latency
343 system.cpu1.icache.ReadReq_avg_miss_latency::total 21643.442623 # average ReadReq miss latency
344 system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 21643.442623 # average overall miss latency
345 system.cpu1.icache.demand_avg_miss_latency::total 21643.442623 # average overall miss latency
346 system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 21643.442623 # average overall miss latency
347 system.cpu1.icache.overall_avg_miss_latency::total 21643.442623 # average overall miss latency
348 system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
349 system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
350 system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
351 system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
352 system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
353 system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
354 system.cpu1.icache.fast_writes 0 # number of fast writes performed
355 system.cpu1.icache.cache_copies 0 # number of cache copies performed
356 system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 366 # number of ReadReq MSHR misses
357 system.cpu1.icache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses
358 system.cpu1.icache.demand_mshr_misses::cpu1.inst 366 # number of demand (read+write) MSHR misses
359 system.cpu1.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses
360 system.cpu1.icache.overall_mshr_misses::cpu1.inst 366 # number of overall MSHR misses
361 system.cpu1.icache.overall_mshr_misses::total 366 # number of overall MSHR misses
362 system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6823000 # number of ReadReq MSHR miss cycles
363 system.cpu1.icache.ReadReq_mshr_miss_latency::total 6823000 # number of ReadReq MSHR miss cycles
364 system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6823000 # number of demand (read+write) MSHR miss cycles
365 system.cpu1.icache.demand_mshr_miss_latency::total 6823000 # number of demand (read+write) MSHR miss cycles
366 system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6823000 # number of overall MSHR miss cycles
367 system.cpu1.icache.overall_mshr_miss_latency::total 6823000 # number of overall MSHR miss cycles
368 system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.002123 # mshr miss rate for ReadReq accesses
369 system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.002123 # mshr miss rate for ReadReq accesses
370 system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.002123 # mshr miss rate for demand accesses
371 system.cpu1.icache.demand_mshr_miss_rate::total 0.002123 # mshr miss rate for demand accesses
372 system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.002123 # mshr miss rate for overall accesses
373 system.cpu1.icache.overall_mshr_miss_rate::total 0.002123 # mshr miss rate for overall accesses
374 system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 18642.076503 # average ReadReq mshr miss latency
375 system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 18642.076503 # average ReadReq mshr miss latency
376 system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 18642.076503 # average overall mshr miss latency
377 system.cpu1.icache.demand_avg_mshr_miss_latency::total 18642.076503 # average overall mshr miss latency
378 system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 18642.076503 # average overall mshr miss latency
379 system.cpu1.icache.overall_avg_mshr_miss_latency::total 18642.076503 # average overall mshr miss latency
380 system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
381 system.cpu1.dcache.replacements 0 # number of replacements
382 system.cpu1.dcache.tagsinuse 27.731444 # Cycle average of tags in use
383 system.cpu1.dcache.total_refs 18765 # Total number of references to valid blocks.
384 system.cpu1.dcache.sampled_refs 29 # Sample count of references to valid blocks.
385 system.cpu1.dcache.avg_refs 647.068966 # Average number of references to valid blocks.
386 system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
387 system.cpu1.dcache.occ_blocks::cpu1.data 27.731444 # Average occupied blocks per requestor
388 system.cpu1.dcache.occ_percent::cpu1.data 0.054163 # Average percentage of cache occupancy
389 system.cpu1.dcache.occ_percent::total 0.054163 # Average percentage of cache occupancy
390 system.cpu1.dcache.ReadReq_hits::cpu1.data 39445 # number of ReadReq hits
391 system.cpu1.dcache.ReadReq_hits::total 39445 # number of ReadReq hits
392 system.cpu1.dcache.WriteReq_hits::cpu1.data 8099 # number of WriteReq hits
393 system.cpu1.dcache.WriteReq_hits::total 8099 # number of WriteReq hits
394 system.cpu1.dcache.SwapReq_hits::cpu1.data 18 # number of SwapReq hits
395 system.cpu1.dcache.SwapReq_hits::total 18 # number of SwapReq hits
396 system.cpu1.dcache.demand_hits::cpu1.data 47544 # number of demand (read+write) hits
397 system.cpu1.dcache.demand_hits::total 47544 # number of demand (read+write) hits
398 system.cpu1.dcache.overall_hits::cpu1.data 47544 # number of overall hits
399 system.cpu1.dcache.overall_hits::total 47544 # number of overall hits
400 system.cpu1.dcache.ReadReq_misses::cpu1.data 179 # number of ReadReq misses
401 system.cpu1.dcache.ReadReq_misses::total 179 # number of ReadReq misses
402 system.cpu1.dcache.WriteReq_misses::cpu1.data 98 # number of WriteReq misses
403 system.cpu1.dcache.WriteReq_misses::total 98 # number of WriteReq misses
404 system.cpu1.dcache.SwapReq_misses::cpu1.data 65 # number of SwapReq misses
405 system.cpu1.dcache.SwapReq_misses::total 65 # number of SwapReq misses
406 system.cpu1.dcache.demand_misses::cpu1.data 277 # number of demand (read+write) misses
407 system.cpu1.dcache.demand_misses::total 277 # number of demand (read+write) misses
408 system.cpu1.dcache.overall_misses::cpu1.data 277 # number of overall misses
409 system.cpu1.dcache.overall_misses::total 277 # number of overall misses
410 system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3683000 # number of ReadReq miss cycles
411 system.cpu1.dcache.ReadReq_miss_latency::total 3683000 # number of ReadReq miss cycles
412 system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1838000 # number of WriteReq miss cycles
413 system.cpu1.dcache.WriteReq_miss_latency::total 1838000 # number of WriteReq miss cycles
414 system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 415000 # number of SwapReq miss cycles
415 system.cpu1.dcache.SwapReq_miss_latency::total 415000 # number of SwapReq miss cycles
416 system.cpu1.dcache.demand_miss_latency::cpu1.data 5521000 # number of demand (read+write) miss cycles
417 system.cpu1.dcache.demand_miss_latency::total 5521000 # number of demand (read+write) miss cycles
418 system.cpu1.dcache.overall_miss_latency::cpu1.data 5521000 # number of overall miss cycles
419 system.cpu1.dcache.overall_miss_latency::total 5521000 # number of overall miss cycles
420 system.cpu1.dcache.ReadReq_accesses::cpu1.data 39624 # number of ReadReq accesses(hits+misses)
421 system.cpu1.dcache.ReadReq_accesses::total 39624 # number of ReadReq accesses(hits+misses)
422 system.cpu1.dcache.WriteReq_accesses::cpu1.data 8197 # number of WriteReq accesses(hits+misses)
423 system.cpu1.dcache.WriteReq_accesses::total 8197 # number of WriteReq accesses(hits+misses)
424 system.cpu1.dcache.SwapReq_accesses::cpu1.data 83 # number of SwapReq accesses(hits+misses)
425 system.cpu1.dcache.SwapReq_accesses::total 83 # number of SwapReq accesses(hits+misses)
426 system.cpu1.dcache.demand_accesses::cpu1.data 47821 # number of demand (read+write) accesses
427 system.cpu1.dcache.demand_accesses::total 47821 # number of demand (read+write) accesses
428 system.cpu1.dcache.overall_accesses::cpu1.data 47821 # number of overall (read+write) accesses
429 system.cpu1.dcache.overall_accesses::total 47821 # number of overall (read+write) accesses
430 system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.004517 # miss rate for ReadReq accesses
431 system.cpu1.dcache.ReadReq_miss_rate::total 0.004517 # miss rate for ReadReq accesses
432 system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.011956 # miss rate for WriteReq accesses
433 system.cpu1.dcache.WriteReq_miss_rate::total 0.011956 # miss rate for WriteReq accesses
434 system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.783133 # miss rate for SwapReq accesses
435 system.cpu1.dcache.SwapReq_miss_rate::total 0.783133 # miss rate for SwapReq accesses
436 system.cpu1.dcache.demand_miss_rate::cpu1.data 0.005792 # miss rate for demand accesses
437 system.cpu1.dcache.demand_miss_rate::total 0.005792 # miss rate for demand accesses
438 system.cpu1.dcache.overall_miss_rate::cpu1.data 0.005792 # miss rate for overall accesses
439 system.cpu1.dcache.overall_miss_rate::total 0.005792 # miss rate for overall accesses
440 system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 20575.418994 # average ReadReq miss latency
441 system.cpu1.dcache.ReadReq_avg_miss_latency::total 20575.418994 # average ReadReq miss latency
442 system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18755.102041 # average WriteReq miss latency
443 system.cpu1.dcache.WriteReq_avg_miss_latency::total 18755.102041 # average WriteReq miss latency
444 system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 6384.615385 # average SwapReq miss latency
445 system.cpu1.dcache.SwapReq_avg_miss_latency::total 6384.615385 # average SwapReq miss latency
446 system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19931.407942 # average overall miss latency
447 system.cpu1.dcache.demand_avg_miss_latency::total 19931.407942 # average overall miss latency
448 system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 19931.407942 # average overall miss latency
449 system.cpu1.dcache.overall_avg_miss_latency::total 19931.407942 # average overall miss latency
450 system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
451 system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
452 system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
453 system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
454 system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
455 system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
456 system.cpu1.dcache.fast_writes 0 # number of fast writes performed
457 system.cpu1.dcache.cache_copies 0 # number of cache copies performed
458 system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 179 # number of ReadReq MSHR misses
459 system.cpu1.dcache.ReadReq_mshr_misses::total 179 # number of ReadReq MSHR misses
460 system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 98 # number of WriteReq MSHR misses
461 system.cpu1.dcache.WriteReq_mshr_misses::total 98 # number of WriteReq MSHR misses
462 system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 65 # number of SwapReq MSHR misses
463 system.cpu1.dcache.SwapReq_mshr_misses::total 65 # number of SwapReq MSHR misses
464 system.cpu1.dcache.demand_mshr_misses::cpu1.data 277 # number of demand (read+write) MSHR misses
465 system.cpu1.dcache.demand_mshr_misses::total 277 # number of demand (read+write) MSHR misses
466 system.cpu1.dcache.overall_mshr_misses::cpu1.data 277 # number of overall MSHR misses
467 system.cpu1.dcache.overall_mshr_misses::total 277 # number of overall MSHR misses
468 system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 3146000 # number of ReadReq MSHR miss cycles
469 system.cpu1.dcache.ReadReq_mshr_miss_latency::total 3146000 # number of ReadReq MSHR miss cycles
470 system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1544000 # number of WriteReq MSHR miss cycles
471 system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1544000 # number of WriteReq MSHR miss cycles
472 system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 220000 # number of SwapReq MSHR miss cycles
473 system.cpu1.dcache.SwapReq_mshr_miss_latency::total 220000 # number of SwapReq MSHR miss cycles
474 system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4690000 # number of demand (read+write) MSHR miss cycles
475 system.cpu1.dcache.demand_mshr_miss_latency::total 4690000 # number of demand (read+write) MSHR miss cycles
476 system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4690000 # number of overall MSHR miss cycles
477 system.cpu1.dcache.overall_mshr_miss_latency::total 4690000 # number of overall MSHR miss cycles
478 system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.004517 # mshr miss rate for ReadReq accesses
479 system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.004517 # mshr miss rate for ReadReq accesses
480 system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.011956 # mshr miss rate for WriteReq accesses
481 system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.011956 # mshr miss rate for WriteReq accesses
482 system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.783133 # mshr miss rate for SwapReq accesses
483 system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.783133 # mshr miss rate for SwapReq accesses
484 system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.005792 # mshr miss rate for demand accesses
485 system.cpu1.dcache.demand_mshr_miss_rate::total 0.005792 # mshr miss rate for demand accesses
486 system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.005792 # mshr miss rate for overall accesses
487 system.cpu1.dcache.overall_mshr_miss_rate::total 0.005792 # mshr miss rate for overall accesses
488 system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 17575.418994 # average ReadReq mshr miss latency
489 system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 17575.418994 # average ReadReq mshr miss latency
490 system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15755.102041 # average WriteReq mshr miss latency
491 system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15755.102041 # average WriteReq mshr miss latency
492 system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 3384.615385 # average SwapReq mshr miss latency
493 system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 3384.615385 # average SwapReq mshr miss latency
494 system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16931.407942 # average overall mshr miss latency
495 system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16931.407942 # average overall mshr miss latency
496 system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16931.407942 # average overall mshr miss latency
497 system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16931.407942 # average overall mshr miss latency
498 system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
499 system.cpu2.numCycles 524598 # number of cpu cycles simulated
500 system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
501 system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
502 system.cpu2.committedInsts 165564 # Number of instructions committed
503 system.cpu2.committedOps 165564 # Number of ops (including micro ops) committed
504 system.cpu2.num_int_alu_accesses 112387 # Number of integer alu accesses
505 system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses
506 system.cpu2.num_func_calls 637 # number of times a function call or return occured
507 system.cpu2.num_conditional_control_insts 30599 # number of instructions that are conditional controls
508 system.cpu2.num_int_insts 112387 # number of integer instructions
509 system.cpu2.num_fp_insts 0 # number of float instructions
510 system.cpu2.num_int_register_reads 289349 # number of times the integer registers were read
511 system.cpu2.num_int_register_writes 110679 # number of times the integer registers were written
512 system.cpu2.num_fp_register_reads 0 # number of times the floating registers were read
513 system.cpu2.num_fp_register_writes 0 # number of times the floating registers were written
514 system.cpu2.num_mem_refs 57957 # number of memory refs
515 system.cpu2.num_load_insts 41868 # Number of load instructions
516 system.cpu2.num_store_insts 16089 # Number of store instructions
517 system.cpu2.num_idle_cycles 68998.001737 # Number of idle cycles
518 system.cpu2.num_busy_cycles 455599.998263 # Number of busy cycles
519 system.cpu2.not_idle_fraction 0.868475 # Percentage of non-idle cycles
520 system.cpu2.idle_fraction 0.131525 # Percentage of idle cycles
521 system.cpu2.icache.replacements 280 # number of replacements
522 system.cpu2.icache.tagsinuse 65.602896 # Cycle average of tags in use
523 system.cpu2.icache.total_refs 165231 # Total number of references to valid blocks.
524 system.cpu2.icache.sampled_refs 366 # Sample count of references to valid blocks.
525 system.cpu2.icache.avg_refs 451.450820 # Average number of references to valid blocks.
526 system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
527 system.cpu2.icache.occ_blocks::cpu2.inst 65.602896 # Average occupied blocks per requestor
528 system.cpu2.icache.occ_percent::cpu2.inst 0.128131 # Average percentage of cache occupancy
529 system.cpu2.icache.occ_percent::total 0.128131 # Average percentage of cache occupancy
530 system.cpu2.icache.ReadReq_hits::cpu2.inst 165231 # number of ReadReq hits
531 system.cpu2.icache.ReadReq_hits::total 165231 # number of ReadReq hits
532 system.cpu2.icache.demand_hits::cpu2.inst 165231 # number of demand (read+write) hits
533 system.cpu2.icache.demand_hits::total 165231 # number of demand (read+write) hits
534 system.cpu2.icache.overall_hits::cpu2.inst 165231 # number of overall hits
535 system.cpu2.icache.overall_hits::total 165231 # number of overall hits
536 system.cpu2.icache.ReadReq_misses::cpu2.inst 366 # number of ReadReq misses
537 system.cpu2.icache.ReadReq_misses::total 366 # number of ReadReq misses
538 system.cpu2.icache.demand_misses::cpu2.inst 366 # number of demand (read+write) misses
539 system.cpu2.icache.demand_misses::total 366 # number of demand (read+write) misses
540 system.cpu2.icache.overall_misses::cpu2.inst 366 # number of overall misses
541 system.cpu2.icache.overall_misses::total 366 # number of overall misses
542 system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 5648500 # number of ReadReq miss cycles
543 system.cpu2.icache.ReadReq_miss_latency::total 5648500 # number of ReadReq miss cycles
544 system.cpu2.icache.demand_miss_latency::cpu2.inst 5648500 # number of demand (read+write) miss cycles
545 system.cpu2.icache.demand_miss_latency::total 5648500 # number of demand (read+write) miss cycles
546 system.cpu2.icache.overall_miss_latency::cpu2.inst 5648500 # number of overall miss cycles
547 system.cpu2.icache.overall_miss_latency::total 5648500 # number of overall miss cycles
548 system.cpu2.icache.ReadReq_accesses::cpu2.inst 165597 # number of ReadReq accesses(hits+misses)
549 system.cpu2.icache.ReadReq_accesses::total 165597 # number of ReadReq accesses(hits+misses)
550 system.cpu2.icache.demand_accesses::cpu2.inst 165597 # number of demand (read+write) accesses
551 system.cpu2.icache.demand_accesses::total 165597 # number of demand (read+write) accesses
552 system.cpu2.icache.overall_accesses::cpu2.inst 165597 # number of overall (read+write) accesses
553 system.cpu2.icache.overall_accesses::total 165597 # number of overall (read+write) accesses
554 system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002210 # miss rate for ReadReq accesses
555 system.cpu2.icache.ReadReq_miss_rate::total 0.002210 # miss rate for ReadReq accesses
556 system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002210 # miss rate for demand accesses
557 system.cpu2.icache.demand_miss_rate::total 0.002210 # miss rate for demand accesses
558 system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002210 # miss rate for overall accesses
559 system.cpu2.icache.overall_miss_rate::total 0.002210 # miss rate for overall accesses
560 system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 15433.060109 # average ReadReq miss latency
561 system.cpu2.icache.ReadReq_avg_miss_latency::total 15433.060109 # average ReadReq miss latency
562 system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 15433.060109 # average overall miss latency
563 system.cpu2.icache.demand_avg_miss_latency::total 15433.060109 # average overall miss latency
564 system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 15433.060109 # average overall miss latency
565 system.cpu2.icache.overall_avg_miss_latency::total 15433.060109 # average overall miss latency
566 system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
567 system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
568 system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked
569 system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked
570 system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
571 system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
572 system.cpu2.icache.fast_writes 0 # number of fast writes performed
573 system.cpu2.icache.cache_copies 0 # number of cache copies performed
574 system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 366 # number of ReadReq MSHR misses
575 system.cpu2.icache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses
576 system.cpu2.icache.demand_mshr_misses::cpu2.inst 366 # number of demand (read+write) MSHR misses
577 system.cpu2.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses
578 system.cpu2.icache.overall_mshr_misses::cpu2.inst 366 # number of overall MSHR misses
579 system.cpu2.icache.overall_mshr_misses::total 366 # number of overall MSHR misses
580 system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 4550500 # number of ReadReq MSHR miss cycles
581 system.cpu2.icache.ReadReq_mshr_miss_latency::total 4550500 # number of ReadReq MSHR miss cycles
582 system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 4550500 # number of demand (read+write) MSHR miss cycles
583 system.cpu2.icache.demand_mshr_miss_latency::total 4550500 # number of demand (read+write) MSHR miss cycles
584 system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 4550500 # number of overall MSHR miss cycles
585 system.cpu2.icache.overall_mshr_miss_latency::total 4550500 # number of overall MSHR miss cycles
586 system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.002210 # mshr miss rate for ReadReq accesses
587 system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.002210 # mshr miss rate for ReadReq accesses
588 system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.002210 # mshr miss rate for demand accesses
589 system.cpu2.icache.demand_mshr_miss_rate::total 0.002210 # mshr miss rate for demand accesses
590 system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.002210 # mshr miss rate for overall accesses
591 system.cpu2.icache.overall_mshr_miss_rate::total 0.002210 # mshr miss rate for overall accesses
592 system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12433.060109 # average ReadReq mshr miss latency
593 system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 12433.060109 # average ReadReq mshr miss latency
594 system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 12433.060109 # average overall mshr miss latency
595 system.cpu2.icache.demand_avg_mshr_miss_latency::total 12433.060109 # average overall mshr miss latency
596 system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 12433.060109 # average overall mshr miss latency
597 system.cpu2.icache.overall_avg_mshr_miss_latency::total 12433.060109 # average overall mshr miss latency
598 system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate
599 system.cpu2.dcache.replacements 0 # number of replacements
600 system.cpu2.dcache.tagsinuse 25.974144 # Cycle average of tags in use
601 system.cpu2.dcache.total_refs 34436 # Total number of references to valid blocks.
602 system.cpu2.dcache.sampled_refs 29 # Sample count of references to valid blocks.
603 system.cpu2.dcache.avg_refs 1187.448276 # Average number of references to valid blocks.
604 system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
605 system.cpu2.dcache.occ_blocks::cpu2.data 25.974144 # Average occupied blocks per requestor
606 system.cpu2.dcache.occ_percent::cpu2.data 0.050731 # Average percentage of cache occupancy
607 system.cpu2.dcache.occ_percent::total 0.050731 # Average percentage of cache occupancy
608 system.cpu2.dcache.ReadReq_hits::cpu2.data 41706 # number of ReadReq hits
609 system.cpu2.dcache.ReadReq_hits::total 41706 # number of ReadReq hits
610 system.cpu2.dcache.WriteReq_hits::cpu2.data 15916 # number of WriteReq hits
611 system.cpu2.dcache.WriteReq_hits::total 15916 # number of WriteReq hits
612 system.cpu2.dcache.SwapReq_hits::cpu2.data 11 # number of SwapReq hits
613 system.cpu2.dcache.SwapReq_hits::total 11 # number of SwapReq hits
614 system.cpu2.dcache.demand_hits::cpu2.data 57622 # number of demand (read+write) hits
615 system.cpu2.dcache.demand_hits::total 57622 # number of demand (read+write) hits
616 system.cpu2.dcache.overall_hits::cpu2.data 57622 # number of overall hits
617 system.cpu2.dcache.overall_hits::total 57622 # number of overall hits
618 system.cpu2.dcache.ReadReq_misses::cpu2.data 154 # number of ReadReq misses
619 system.cpu2.dcache.ReadReq_misses::total 154 # number of ReadReq misses
620 system.cpu2.dcache.WriteReq_misses::cpu2.data 109 # number of WriteReq misses
621 system.cpu2.dcache.WriteReq_misses::total 109 # number of WriteReq misses
622 system.cpu2.dcache.SwapReq_misses::cpu2.data 51 # number of SwapReq misses
623 system.cpu2.dcache.SwapReq_misses::total 51 # number of SwapReq misses
624 system.cpu2.dcache.demand_misses::cpu2.data 263 # number of demand (read+write) misses
625 system.cpu2.dcache.demand_misses::total 263 # number of demand (read+write) misses
626 system.cpu2.dcache.overall_misses::cpu2.data 263 # number of overall misses
627 system.cpu2.dcache.overall_misses::total 263 # number of overall misses
628 system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 2498000 # number of ReadReq miss cycles
629 system.cpu2.dcache.ReadReq_miss_latency::total 2498000 # number of ReadReq miss cycles
630 system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2031000 # number of WriteReq miss cycles
631 system.cpu2.dcache.WriteReq_miss_latency::total 2031000 # number of WriteReq miss cycles
632 system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 305000 # number of SwapReq miss cycles
633 system.cpu2.dcache.SwapReq_miss_latency::total 305000 # number of SwapReq miss cycles
634 system.cpu2.dcache.demand_miss_latency::cpu2.data 4529000 # number of demand (read+write) miss cycles
635 system.cpu2.dcache.demand_miss_latency::total 4529000 # number of demand (read+write) miss cycles
636 system.cpu2.dcache.overall_miss_latency::cpu2.data 4529000 # number of overall miss cycles
637 system.cpu2.dcache.overall_miss_latency::total 4529000 # number of overall miss cycles
638 system.cpu2.dcache.ReadReq_accesses::cpu2.data 41860 # number of ReadReq accesses(hits+misses)
639 system.cpu2.dcache.ReadReq_accesses::total 41860 # number of ReadReq accesses(hits+misses)
640 system.cpu2.dcache.WriteReq_accesses::cpu2.data 16025 # number of WriteReq accesses(hits+misses)
641 system.cpu2.dcache.WriteReq_accesses::total 16025 # number of WriteReq accesses(hits+misses)
642 system.cpu2.dcache.SwapReq_accesses::cpu2.data 62 # number of SwapReq accesses(hits+misses)
643 system.cpu2.dcache.SwapReq_accesses::total 62 # number of SwapReq accesses(hits+misses)
644 system.cpu2.dcache.demand_accesses::cpu2.data 57885 # number of demand (read+write) accesses
645 system.cpu2.dcache.demand_accesses::total 57885 # number of demand (read+write) accesses
646 system.cpu2.dcache.overall_accesses::cpu2.data 57885 # number of overall (read+write) accesses
647 system.cpu2.dcache.overall_accesses::total 57885 # number of overall (read+write) accesses
648 system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003679 # miss rate for ReadReq accesses
649 system.cpu2.dcache.ReadReq_miss_rate::total 0.003679 # miss rate for ReadReq accesses
650 system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.006802 # miss rate for WriteReq accesses
651 system.cpu2.dcache.WriteReq_miss_rate::total 0.006802 # miss rate for WriteReq accesses
652 system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.822581 # miss rate for SwapReq accesses
653 system.cpu2.dcache.SwapReq_miss_rate::total 0.822581 # miss rate for SwapReq accesses
654 system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004543 # miss rate for demand accesses
655 system.cpu2.dcache.demand_miss_rate::total 0.004543 # miss rate for demand accesses
656 system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004543 # miss rate for overall accesses
657 system.cpu2.dcache.overall_miss_rate::total 0.004543 # miss rate for overall accesses
658 system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 16220.779221 # average ReadReq miss latency
659 system.cpu2.dcache.ReadReq_avg_miss_latency::total 16220.779221 # average ReadReq miss latency
660 system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 18633.027523 # average WriteReq miss latency
661 system.cpu2.dcache.WriteReq_avg_miss_latency::total 18633.027523 # average WriteReq miss latency
662 system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 5980.392157 # average SwapReq miss latency
663 system.cpu2.dcache.SwapReq_avg_miss_latency::total 5980.392157 # average SwapReq miss latency
664 system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 17220.532319 # average overall miss latency
665 system.cpu2.dcache.demand_avg_miss_latency::total 17220.532319 # average overall miss latency
666 system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 17220.532319 # average overall miss latency
667 system.cpu2.dcache.overall_avg_miss_latency::total 17220.532319 # average overall miss latency
668 system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
669 system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
670 system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
671 system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked
672 system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
673 system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
674 system.cpu2.dcache.fast_writes 0 # number of fast writes performed
675 system.cpu2.dcache.cache_copies 0 # number of cache copies performed
676 system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 154 # number of ReadReq MSHR misses
677 system.cpu2.dcache.ReadReq_mshr_misses::total 154 # number of ReadReq MSHR misses
678 system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 109 # number of WriteReq MSHR misses
679 system.cpu2.dcache.WriteReq_mshr_misses::total 109 # number of WriteReq MSHR misses
680 system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 51 # number of SwapReq MSHR misses
681 system.cpu2.dcache.SwapReq_mshr_misses::total 51 # number of SwapReq MSHR misses
682 system.cpu2.dcache.demand_mshr_misses::cpu2.data 263 # number of demand (read+write) MSHR misses
683 system.cpu2.dcache.demand_mshr_misses::total 263 # number of demand (read+write) MSHR misses
684 system.cpu2.dcache.overall_mshr_misses::cpu2.data 263 # number of overall MSHR misses
685 system.cpu2.dcache.overall_mshr_misses::total 263 # number of overall MSHR misses
686 system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 2036000 # number of ReadReq MSHR miss cycles
687 system.cpu2.dcache.ReadReq_mshr_miss_latency::total 2036000 # number of ReadReq MSHR miss cycles
688 system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1704000 # number of WriteReq MSHR miss cycles
689 system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1704000 # number of WriteReq MSHR miss cycles
690 system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 152000 # number of SwapReq MSHR miss cycles
691 system.cpu2.dcache.SwapReq_mshr_miss_latency::total 152000 # number of SwapReq MSHR miss cycles
692 system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3740000 # number of demand (read+write) MSHR miss cycles
693 system.cpu2.dcache.demand_mshr_miss_latency::total 3740000 # number of demand (read+write) MSHR miss cycles
694 system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3740000 # number of overall MSHR miss cycles
695 system.cpu2.dcache.overall_mshr_miss_latency::total 3740000 # number of overall MSHR miss cycles
696 system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003679 # mshr miss rate for ReadReq accesses
697 system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003679 # mshr miss rate for ReadReq accesses
698 system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.006802 # mshr miss rate for WriteReq accesses
699 system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.006802 # mshr miss rate for WriteReq accesses
700 system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.822581 # mshr miss rate for SwapReq accesses
701 system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.822581 # mshr miss rate for SwapReq accesses
702 system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004543 # mshr miss rate for demand accesses
703 system.cpu2.dcache.demand_mshr_miss_rate::total 0.004543 # mshr miss rate for demand accesses
704 system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004543 # mshr miss rate for overall accesses
705 system.cpu2.dcache.overall_mshr_miss_rate::total 0.004543 # mshr miss rate for overall accesses
706 system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13220.779221 # average ReadReq mshr miss latency
707 system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 13220.779221 # average ReadReq mshr miss latency
708 system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 15633.027523 # average WriteReq mshr miss latency
709 system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 15633.027523 # average WriteReq mshr miss latency
710 system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 2980.392157 # average SwapReq mshr miss latency
711 system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 2980.392157 # average SwapReq mshr miss latency
712 system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 14220.532319 # average overall mshr miss latency
713 system.cpu2.dcache.demand_avg_mshr_miss_latency::total 14220.532319 # average overall mshr miss latency
714 system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 14220.532319 # average overall mshr miss latency
715 system.cpu2.dcache.overall_avg_mshr_miss_latency::total 14220.532319 # average overall mshr miss latency
716 system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
717 system.cpu3.numCycles 524598 # number of cpu cycles simulated
718 system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
719 system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed
720 system.cpu3.committedInsts 166196 # Number of instructions committed
721 system.cpu3.committedOps 166196 # Number of ops (including micro ops) committed
722 system.cpu3.num_int_alu_accesses 112131 # Number of integer alu accesses
723 system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses
724 system.cpu3.num_func_calls 637 # number of times a function call or return occured
725 system.cpu3.num_conditional_control_insts 31040 # number of instructions that are conditional controls
726 system.cpu3.num_int_insts 112131 # number of integer instructions
727 system.cpu3.num_fp_insts 0 # number of float instructions
728 system.cpu3.num_int_register_reads 286557 # number of times the integer registers were read
729 system.cpu3.num_int_register_writes 109409 # number of times the integer registers were written
730 system.cpu3.num_fp_register_reads 0 # number of times the floating registers were read
731 system.cpu3.num_fp_register_writes 0 # number of times the floating registers were written
732 system.cpu3.num_mem_refs 57260 # number of memory refs
733 system.cpu3.num_load_insts 41737 # Number of load instructions
734 system.cpu3.num_store_insts 15523 # Number of store instructions
735 system.cpu3.num_idle_cycles 69252.001736 # Number of idle cycles
736 system.cpu3.num_busy_cycles 455345.998264 # Number of busy cycles
737 system.cpu3.not_idle_fraction 0.867990 # Percentage of non-idle cycles
738 system.cpu3.idle_fraction 0.132010 # Percentage of idle cycles
739 system.cpu3.icache.replacements 281 # number of replacements
740 system.cpu3.icache.tagsinuse 67.739564 # Cycle average of tags in use
741 system.cpu3.icache.total_refs 165862 # Total number of references to valid blocks.
742 system.cpu3.icache.sampled_refs 367 # Sample count of references to valid blocks.
743 system.cpu3.icache.avg_refs 451.940054 # Average number of references to valid blocks.
744 system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
745 system.cpu3.icache.occ_blocks::cpu3.inst 67.739564 # Average occupied blocks per requestor
746 system.cpu3.icache.occ_percent::cpu3.inst 0.132304 # Average percentage of cache occupancy
747 system.cpu3.icache.occ_percent::total 0.132304 # Average percentage of cache occupancy
748 system.cpu3.icache.ReadReq_hits::cpu3.inst 165862 # number of ReadReq hits
749 system.cpu3.icache.ReadReq_hits::total 165862 # number of ReadReq hits
750 system.cpu3.icache.demand_hits::cpu3.inst 165862 # number of demand (read+write) hits
751 system.cpu3.icache.demand_hits::total 165862 # number of demand (read+write) hits
752 system.cpu3.icache.overall_hits::cpu3.inst 165862 # number of overall hits
753 system.cpu3.icache.overall_hits::total 165862 # number of overall hits
754 system.cpu3.icache.ReadReq_misses::cpu3.inst 367 # number of ReadReq misses
755 system.cpu3.icache.ReadReq_misses::total 367 # number of ReadReq misses
756 system.cpu3.icache.demand_misses::cpu3.inst 367 # number of demand (read+write) misses
757 system.cpu3.icache.demand_misses::total 367 # number of demand (read+write) misses
758 system.cpu3.icache.overall_misses::cpu3.inst 367 # number of overall misses
759 system.cpu3.icache.overall_misses::total 367 # number of overall misses
760 system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 5533500 # number of ReadReq miss cycles
761 system.cpu3.icache.ReadReq_miss_latency::total 5533500 # number of ReadReq miss cycles
762 system.cpu3.icache.demand_miss_latency::cpu3.inst 5533500 # number of demand (read+write) miss cycles
763 system.cpu3.icache.demand_miss_latency::total 5533500 # number of demand (read+write) miss cycles
764 system.cpu3.icache.overall_miss_latency::cpu3.inst 5533500 # number of overall miss cycles
765 system.cpu3.icache.overall_miss_latency::total 5533500 # number of overall miss cycles
766 system.cpu3.icache.ReadReq_accesses::cpu3.inst 166229 # number of ReadReq accesses(hits+misses)
767 system.cpu3.icache.ReadReq_accesses::total 166229 # number of ReadReq accesses(hits+misses)
768 system.cpu3.icache.demand_accesses::cpu3.inst 166229 # number of demand (read+write) accesses
769 system.cpu3.icache.demand_accesses::total 166229 # number of demand (read+write) accesses
770 system.cpu3.icache.overall_accesses::cpu3.inst 166229 # number of overall (read+write) accesses
771 system.cpu3.icache.overall_accesses::total 166229 # number of overall (read+write) accesses
772 system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002208 # miss rate for ReadReq accesses
773 system.cpu3.icache.ReadReq_miss_rate::total 0.002208 # miss rate for ReadReq accesses
774 system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002208 # miss rate for demand accesses
775 system.cpu3.icache.demand_miss_rate::total 0.002208 # miss rate for demand accesses
776 system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002208 # miss rate for overall accesses
777 system.cpu3.icache.overall_miss_rate::total 0.002208 # miss rate for overall accesses
778 system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 15077.656676 # average ReadReq miss latency
779 system.cpu3.icache.ReadReq_avg_miss_latency::total 15077.656676 # average ReadReq miss latency
780 system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 15077.656676 # average overall miss latency
781 system.cpu3.icache.demand_avg_miss_latency::total 15077.656676 # average overall miss latency
782 system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 15077.656676 # average overall miss latency
783 system.cpu3.icache.overall_avg_miss_latency::total 15077.656676 # average overall miss latency
784 system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
785 system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
786 system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked
787 system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked
788 system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
789 system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
790 system.cpu3.icache.fast_writes 0 # number of fast writes performed
791 system.cpu3.icache.cache_copies 0 # number of cache copies performed
792 system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 367 # number of ReadReq MSHR misses
793 system.cpu3.icache.ReadReq_mshr_misses::total 367 # number of ReadReq MSHR misses
794 system.cpu3.icache.demand_mshr_misses::cpu3.inst 367 # number of demand (read+write) MSHR misses
795 system.cpu3.icache.demand_mshr_misses::total 367 # number of demand (read+write) MSHR misses
796 system.cpu3.icache.overall_mshr_misses::cpu3.inst 367 # number of overall MSHR misses
797 system.cpu3.icache.overall_mshr_misses::total 367 # number of overall MSHR misses
798 system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 4432500 # number of ReadReq MSHR miss cycles
799 system.cpu3.icache.ReadReq_mshr_miss_latency::total 4432500 # number of ReadReq MSHR miss cycles
800 system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 4432500 # number of demand (read+write) MSHR miss cycles
801 system.cpu3.icache.demand_mshr_miss_latency::total 4432500 # number of demand (read+write) MSHR miss cycles
802 system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 4432500 # number of overall MSHR miss cycles
803 system.cpu3.icache.overall_mshr_miss_latency::total 4432500 # number of overall MSHR miss cycles
804 system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.002208 # mshr miss rate for ReadReq accesses
805 system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.002208 # mshr miss rate for ReadReq accesses
806 system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.002208 # mshr miss rate for demand accesses
807 system.cpu3.icache.demand_mshr_miss_rate::total 0.002208 # mshr miss rate for demand accesses
808 system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.002208 # mshr miss rate for overall accesses
809 system.cpu3.icache.overall_mshr_miss_rate::total 0.002208 # mshr miss rate for overall accesses
810 system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12077.656676 # average ReadReq mshr miss latency
811 system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12077.656676 # average ReadReq mshr miss latency
812 system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12077.656676 # average overall mshr miss latency
813 system.cpu3.icache.demand_avg_mshr_miss_latency::total 12077.656676 # average overall mshr miss latency
814 system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12077.656676 # average overall mshr miss latency
815 system.cpu3.icache.overall_avg_mshr_miss_latency::total 12077.656676 # average overall mshr miss latency
816 system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate
817 system.cpu3.dcache.replacements 0 # number of replacements
818 system.cpu3.dcache.tagsinuse 26.774212 # Cycle average of tags in use
819 system.cpu3.dcache.total_refs 33417 # Total number of references to valid blocks.
820 system.cpu3.dcache.sampled_refs 30 # Sample count of references to valid blocks.
821 system.cpu3.dcache.avg_refs 1113.900000 # Average number of references to valid blocks.
822 system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
823 system.cpu3.dcache.occ_blocks::cpu3.data 26.774212 # Average occupied blocks per requestor
824 system.cpu3.dcache.occ_percent::cpu3.data 0.052293 # Average percentage of cache occupancy
825 system.cpu3.dcache.occ_percent::total 0.052293 # Average percentage of cache occupancy
826 system.cpu3.dcache.ReadReq_hits::cpu3.data 41574 # number of ReadReq hits
827 system.cpu3.dcache.ReadReq_hits::total 41574 # number of ReadReq hits
828 system.cpu3.dcache.WriteReq_hits::cpu3.data 15348 # number of WriteReq hits
829 system.cpu3.dcache.WriteReq_hits::total 15348 # number of WriteReq hits
830 system.cpu3.dcache.SwapReq_hits::cpu3.data 11 # number of SwapReq hits
831 system.cpu3.dcache.SwapReq_hits::total 11 # number of SwapReq hits
832 system.cpu3.dcache.demand_hits::cpu3.data 56922 # number of demand (read+write) hits
833 system.cpu3.dcache.demand_hits::total 56922 # number of demand (read+write) hits
834 system.cpu3.dcache.overall_hits::cpu3.data 56922 # number of overall hits
835 system.cpu3.dcache.overall_hits::total 56922 # number of overall hits
836 system.cpu3.dcache.ReadReq_misses::cpu3.data 155 # number of ReadReq misses
837 system.cpu3.dcache.ReadReq_misses::total 155 # number of ReadReq misses
838 system.cpu3.dcache.WriteReq_misses::cpu3.data 108 # number of WriteReq misses
839 system.cpu3.dcache.WriteReq_misses::total 108 # number of WriteReq misses
840 system.cpu3.dcache.SwapReq_misses::cpu3.data 54 # number of SwapReq misses
841 system.cpu3.dcache.SwapReq_misses::total 54 # number of SwapReq misses
842 system.cpu3.dcache.demand_misses::cpu3.data 263 # number of demand (read+write) misses
843 system.cpu3.dcache.demand_misses::total 263 # number of demand (read+write) misses
844 system.cpu3.dcache.overall_misses::cpu3.data 263 # number of overall misses
845 system.cpu3.dcache.overall_misses::total 263 # number of overall misses
846 system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 2537000 # number of ReadReq miss cycles
847 system.cpu3.dcache.ReadReq_miss_latency::total 2537000 # number of ReadReq miss cycles
848 system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 2026000 # number of WriteReq miss cycles
849 system.cpu3.dcache.WriteReq_miss_latency::total 2026000 # number of WriteReq miss cycles
850 system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 326000 # number of SwapReq miss cycles
851 system.cpu3.dcache.SwapReq_miss_latency::total 326000 # number of SwapReq miss cycles
852 system.cpu3.dcache.demand_miss_latency::cpu3.data 4563000 # number of demand (read+write) miss cycles
853 system.cpu3.dcache.demand_miss_latency::total 4563000 # number of demand (read+write) miss cycles
854 system.cpu3.dcache.overall_miss_latency::cpu3.data 4563000 # number of overall miss cycles
855 system.cpu3.dcache.overall_miss_latency::total 4563000 # number of overall miss cycles
856 system.cpu3.dcache.ReadReq_accesses::cpu3.data 41729 # number of ReadReq accesses(hits+misses)
857 system.cpu3.dcache.ReadReq_accesses::total 41729 # number of ReadReq accesses(hits+misses)
858 system.cpu3.dcache.WriteReq_accesses::cpu3.data 15456 # number of WriteReq accesses(hits+misses)
859 system.cpu3.dcache.WriteReq_accesses::total 15456 # number of WriteReq accesses(hits+misses)
860 system.cpu3.dcache.SwapReq_accesses::cpu3.data 65 # number of SwapReq accesses(hits+misses)
861 system.cpu3.dcache.SwapReq_accesses::total 65 # number of SwapReq accesses(hits+misses)
862 system.cpu3.dcache.demand_accesses::cpu3.data 57185 # number of demand (read+write) accesses
863 system.cpu3.dcache.demand_accesses::total 57185 # number of demand (read+write) accesses
864 system.cpu3.dcache.overall_accesses::cpu3.data 57185 # number of overall (read+write) accesses
865 system.cpu3.dcache.overall_accesses::total 57185 # number of overall (read+write) accesses
866 system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.003714 # miss rate for ReadReq accesses
867 system.cpu3.dcache.ReadReq_miss_rate::total 0.003714 # miss rate for ReadReq accesses
868 system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.006988 # miss rate for WriteReq accesses
869 system.cpu3.dcache.WriteReq_miss_rate::total 0.006988 # miss rate for WriteReq accesses
870 system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.830769 # miss rate for SwapReq accesses
871 system.cpu3.dcache.SwapReq_miss_rate::total 0.830769 # miss rate for SwapReq accesses
872 system.cpu3.dcache.demand_miss_rate::cpu3.data 0.004599 # miss rate for demand accesses
873 system.cpu3.dcache.demand_miss_rate::total 0.004599 # miss rate for demand accesses
874 system.cpu3.dcache.overall_miss_rate::cpu3.data 0.004599 # miss rate for overall accesses
875 system.cpu3.dcache.overall_miss_rate::total 0.004599 # miss rate for overall accesses
876 system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 16367.741935 # average ReadReq miss latency
877 system.cpu3.dcache.ReadReq_avg_miss_latency::total 16367.741935 # average ReadReq miss latency
878 system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 18759.259259 # average WriteReq miss latency
879 system.cpu3.dcache.WriteReq_avg_miss_latency::total 18759.259259 # average WriteReq miss latency
880 system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 6037.037037 # average SwapReq miss latency
881 system.cpu3.dcache.SwapReq_avg_miss_latency::total 6037.037037 # average SwapReq miss latency
882 system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 17349.809886 # average overall miss latency
883 system.cpu3.dcache.demand_avg_miss_latency::total 17349.809886 # average overall miss latency
884 system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 17349.809886 # average overall miss latency
885 system.cpu3.dcache.overall_avg_miss_latency::total 17349.809886 # average overall miss latency
886 system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
887 system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
888 system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
889 system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked
890 system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
891 system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
892 system.cpu3.dcache.fast_writes 0 # number of fast writes performed
893 system.cpu3.dcache.cache_copies 0 # number of cache copies performed
894 system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 155 # number of ReadReq MSHR misses
895 system.cpu3.dcache.ReadReq_mshr_misses::total 155 # number of ReadReq MSHR misses
896 system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 108 # number of WriteReq MSHR misses
897 system.cpu3.dcache.WriteReq_mshr_misses::total 108 # number of WriteReq MSHR misses
898 system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 54 # number of SwapReq MSHR misses
899 system.cpu3.dcache.SwapReq_mshr_misses::total 54 # number of SwapReq MSHR misses
900 system.cpu3.dcache.demand_mshr_misses::cpu3.data 263 # number of demand (read+write) MSHR misses
901 system.cpu3.dcache.demand_mshr_misses::total 263 # number of demand (read+write) MSHR misses
902 system.cpu3.dcache.overall_mshr_misses::cpu3.data 263 # number of overall MSHR misses
903 system.cpu3.dcache.overall_mshr_misses::total 263 # number of overall MSHR misses
904 system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 2072000 # number of ReadReq MSHR miss cycles
905 system.cpu3.dcache.ReadReq_mshr_miss_latency::total 2072000 # number of ReadReq MSHR miss cycles
906 system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1702000 # number of WriteReq MSHR miss cycles
907 system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1702000 # number of WriteReq MSHR miss cycles
908 system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 164000 # number of SwapReq MSHR miss cycles
909 system.cpu3.dcache.SwapReq_mshr_miss_latency::total 164000 # number of SwapReq MSHR miss cycles
910 system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 3774000 # number of demand (read+write) MSHR miss cycles
911 system.cpu3.dcache.demand_mshr_miss_latency::total 3774000 # number of demand (read+write) MSHR miss cycles
912 system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 3774000 # number of overall MSHR miss cycles
913 system.cpu3.dcache.overall_mshr_miss_latency::total 3774000 # number of overall MSHR miss cycles
914 system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003714 # mshr miss rate for ReadReq accesses
915 system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003714 # mshr miss rate for ReadReq accesses
916 system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.006988 # mshr miss rate for WriteReq accesses
917 system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.006988 # mshr miss rate for WriteReq accesses
918 system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.830769 # mshr miss rate for SwapReq accesses
919 system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.830769 # mshr miss rate for SwapReq accesses
920 system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.004599 # mshr miss rate for demand accesses
921 system.cpu3.dcache.demand_mshr_miss_rate::total 0.004599 # mshr miss rate for demand accesses
922 system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.004599 # mshr miss rate for overall accesses
923 system.cpu3.dcache.overall_mshr_miss_rate::total 0.004599 # mshr miss rate for overall accesses
924 system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 13367.741935 # average ReadReq mshr miss latency
925 system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 13367.741935 # average ReadReq mshr miss latency
926 system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 15759.259259 # average WriteReq mshr miss latency
927 system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 15759.259259 # average WriteReq mshr miss latency
928 system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 3037.037037 # average SwapReq mshr miss latency
929 system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 3037.037037 # average SwapReq mshr miss latency
930 system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 14349.809886 # average overall mshr miss latency
931 system.cpu3.dcache.demand_avg_mshr_miss_latency::total 14349.809886 # average overall mshr miss latency
932 system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 14349.809886 # average overall mshr miss latency
933 system.cpu3.dcache.overall_avg_mshr_miss_latency::total 14349.809886 # average overall mshr miss latency
934 system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
935 system.l2c.replacements 0 # number of replacements
936 system.l2c.tagsinuse 349.180649 # Cycle average of tags in use
937 system.l2c.total_refs 1220 # Total number of references to valid blocks.
938 system.l2c.sampled_refs 429 # Sample count of references to valid blocks.
939 system.l2c.avg_refs 2.843823 # Average number of references to valid blocks.
940 system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
941 system.l2c.occ_blocks::writebacks 0.889759 # Average occupied blocks per requestor
942 system.l2c.occ_blocks::cpu0.inst 231.859241 # Average occupied blocks per requestor
943 system.l2c.occ_blocks::cpu0.data 54.220371 # Average occupied blocks per requestor
944 system.l2c.occ_blocks::cpu1.inst 51.601321 # Average occupied blocks per requestor
945 system.l2c.occ_blocks::cpu1.data 6.129070 # Average occupied blocks per requestor
946 system.l2c.occ_blocks::cpu2.inst 1.917102 # Average occupied blocks per requestor
947 system.l2c.occ_blocks::cpu2.data 0.831909 # Average occupied blocks per requestor
948 system.l2c.occ_blocks::cpu3.inst 0.887228 # Average occupied blocks per requestor
949 system.l2c.occ_blocks::cpu3.data 0.844647 # Average occupied blocks per requestor
950 system.l2c.occ_percent::writebacks 0.000014 # Average percentage of cache occupancy
951 system.l2c.occ_percent::cpu0.inst 0.003538 # Average percentage of cache occupancy
952 system.l2c.occ_percent::cpu0.data 0.000827 # Average percentage of cache occupancy
953 system.l2c.occ_percent::cpu1.inst 0.000787 # Average percentage of cache occupancy
954 system.l2c.occ_percent::cpu1.data 0.000094 # Average percentage of cache occupancy
955 system.l2c.occ_percent::cpu2.inst 0.000029 # Average percentage of cache occupancy
956 system.l2c.occ_percent::cpu2.data 0.000013 # Average percentage of cache occupancy
957 system.l2c.occ_percent::cpu3.inst 0.000014 # Average percentage of cache occupancy
958 system.l2c.occ_percent::cpu3.data 0.000013 # Average percentage of cache occupancy
959 system.l2c.occ_percent::total 0.005328 # Average percentage of cache occupancy
960 system.l2c.ReadReq_hits::cpu0.inst 182 # number of ReadReq hits
961 system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits
962 system.l2c.ReadReq_hits::cpu1.inst 300 # number of ReadReq hits
963 system.l2c.ReadReq_hits::cpu1.data 3 # number of ReadReq hits
964 system.l2c.ReadReq_hits::cpu2.inst 354 # number of ReadReq hits
965 system.l2c.ReadReq_hits::cpu2.data 9 # number of ReadReq hits
966 system.l2c.ReadReq_hits::cpu3.inst 358 # number of ReadReq hits
967 system.l2c.ReadReq_hits::cpu3.data 9 # number of ReadReq hits
968 system.l2c.ReadReq_hits::total 1220 # number of ReadReq hits
969 system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits
970 system.l2c.Writeback_hits::total 1 # number of Writeback hits
971 system.l2c.UpgradeReq_hits::cpu0.data 2 # number of UpgradeReq hits
972 system.l2c.UpgradeReq_hits::total 2 # number of UpgradeReq hits
973 system.l2c.demand_hits::cpu0.inst 182 # number of demand (read+write) hits
974 system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits
975 system.l2c.demand_hits::cpu1.inst 300 # number of demand (read+write) hits
976 system.l2c.demand_hits::cpu1.data 3 # number of demand (read+write) hits
977 system.l2c.demand_hits::cpu2.inst 354 # number of demand (read+write) hits
978 system.l2c.demand_hits::cpu2.data 9 # number of demand (read+write) hits
979 system.l2c.demand_hits::cpu3.inst 358 # number of demand (read+write) hits
980 system.l2c.demand_hits::cpu3.data 9 # number of demand (read+write) hits
981 system.l2c.demand_hits::total 1220 # number of demand (read+write) hits
982 system.l2c.overall_hits::cpu0.inst 182 # number of overall hits
983 system.l2c.overall_hits::cpu0.data 5 # number of overall hits
984 system.l2c.overall_hits::cpu1.inst 300 # number of overall hits
985 system.l2c.overall_hits::cpu1.data 3 # number of overall hits
986 system.l2c.overall_hits::cpu2.inst 354 # number of overall hits
987 system.l2c.overall_hits::cpu2.data 9 # number of overall hits
988 system.l2c.overall_hits::cpu3.inst 358 # number of overall hits
989 system.l2c.overall_hits::cpu3.data 9 # number of overall hits
990 system.l2c.overall_hits::total 1220 # number of overall hits
991 system.l2c.ReadReq_misses::cpu0.inst 285 # number of ReadReq misses
992 system.l2c.ReadReq_misses::cpu0.data 66 # number of ReadReq misses
993 system.l2c.ReadReq_misses::cpu1.inst 66 # number of ReadReq misses
994 system.l2c.ReadReq_misses::cpu1.data 8 # number of ReadReq misses
995 system.l2c.ReadReq_misses::cpu2.inst 12 # number of ReadReq misses
996 system.l2c.ReadReq_misses::cpu2.data 2 # number of ReadReq misses
997 system.l2c.ReadReq_misses::cpu3.inst 9 # number of ReadReq misses
998 system.l2c.ReadReq_misses::cpu3.data 2 # number of ReadReq misses
999 system.l2c.ReadReq_misses::total 450 # number of ReadReq misses
1000 system.l2c.UpgradeReq_misses::cpu0.data 28 # number of UpgradeReq misses
1001 system.l2c.UpgradeReq_misses::cpu1.data 11 # number of UpgradeReq misses
1002 system.l2c.UpgradeReq_misses::cpu2.data 15 # number of UpgradeReq misses
1003 system.l2c.UpgradeReq_misses::cpu3.data 15 # number of UpgradeReq misses
1004 system.l2c.UpgradeReq_misses::total 69 # number of UpgradeReq misses
1005 system.l2c.ReadExReq_misses::cpu0.data 99 # number of ReadExReq misses
1006 system.l2c.ReadExReq_misses::cpu1.data 15 # number of ReadExReq misses
1007 system.l2c.ReadExReq_misses::cpu2.data 14 # number of ReadExReq misses
1008 system.l2c.ReadExReq_misses::cpu3.data 14 # number of ReadExReq misses
1009 system.l2c.ReadExReq_misses::total 142 # number of ReadExReq misses
1010 system.l2c.demand_misses::cpu0.inst 285 # number of demand (read+write) misses
1011 system.l2c.demand_misses::cpu0.data 165 # number of demand (read+write) misses
1012 system.l2c.demand_misses::cpu1.inst 66 # number of demand (read+write) misses
1013 system.l2c.demand_misses::cpu1.data 23 # number of demand (read+write) misses
1014 system.l2c.demand_misses::cpu2.inst 12 # number of demand (read+write) misses
1015 system.l2c.demand_misses::cpu2.data 16 # number of demand (read+write) misses
1016 system.l2c.demand_misses::cpu3.inst 9 # number of demand (read+write) misses
1017 system.l2c.demand_misses::cpu3.data 16 # number of demand (read+write) misses
1018 system.l2c.demand_misses::total 592 # number of demand (read+write) misses
1019 system.l2c.overall_misses::cpu0.inst 285 # number of overall misses
1020 system.l2c.overall_misses::cpu0.data 165 # number of overall misses
1021 system.l2c.overall_misses::cpu1.inst 66 # number of overall misses
1022 system.l2c.overall_misses::cpu1.data 23 # number of overall misses
1023 system.l2c.overall_misses::cpu2.inst 12 # number of overall misses
1024 system.l2c.overall_misses::cpu2.data 16 # number of overall misses
1025 system.l2c.overall_misses::cpu3.inst 9 # number of overall misses
1026 system.l2c.overall_misses::cpu3.data 16 # number of overall misses
1027 system.l2c.overall_misses::total 592 # number of overall misses
1028 system.l2c.ReadReq_miss_latency::cpu0.inst 14822000 # number of ReadReq miss cycles
1029 system.l2c.ReadReq_miss_latency::cpu0.data 3432000 # number of ReadReq miss cycles
1030 system.l2c.ReadReq_miss_latency::cpu1.inst 3402000 # number of ReadReq miss cycles
1031 system.l2c.ReadReq_miss_latency::cpu1.data 411000 # number of ReadReq miss cycles
1032 system.l2c.ReadReq_miss_latency::cpu2.inst 615000 # number of ReadReq miss cycles
1033 system.l2c.ReadReq_miss_latency::cpu2.data 104000 # number of ReadReq miss cycles
1034 system.l2c.ReadReq_miss_latency::cpu3.inst 446000 # number of ReadReq miss cycles
1035 system.l2c.ReadReq_miss_latency::cpu3.data 101000 # number of ReadReq miss cycles
1036 system.l2c.ReadReq_miss_latency::total 23333000 # number of ReadReq miss cycles
1037 system.l2c.ReadExReq_miss_latency::cpu0.data 5148000 # number of ReadExReq miss cycles
1038 system.l2c.ReadExReq_miss_latency::cpu1.data 780000 # number of ReadExReq miss cycles
1039 system.l2c.ReadExReq_miss_latency::cpu2.data 728000 # number of ReadExReq miss cycles
1040 system.l2c.ReadExReq_miss_latency::cpu3.data 728000 # number of ReadExReq miss cycles
1041 system.l2c.ReadExReq_miss_latency::total 7384000 # number of ReadExReq miss cycles
1042 system.l2c.demand_miss_latency::cpu0.inst 14822000 # number of demand (read+write) miss cycles
1043 system.l2c.demand_miss_latency::cpu0.data 8580000 # number of demand (read+write) miss cycles
1044 system.l2c.demand_miss_latency::cpu1.inst 3402000 # number of demand (read+write) miss cycles
1045 system.l2c.demand_miss_latency::cpu1.data 1191000 # number of demand (read+write) miss cycles
1046 system.l2c.demand_miss_latency::cpu2.inst 615000 # number of demand (read+write) miss cycles
1047 system.l2c.demand_miss_latency::cpu2.data 832000 # number of demand (read+write) miss cycles
1048 system.l2c.demand_miss_latency::cpu3.inst 446000 # number of demand (read+write) miss cycles
1049 system.l2c.demand_miss_latency::cpu3.data 829000 # number of demand (read+write) miss cycles
1050 system.l2c.demand_miss_latency::total 30717000 # number of demand (read+write) miss cycles
1051 system.l2c.overall_miss_latency::cpu0.inst 14822000 # number of overall miss cycles
1052 system.l2c.overall_miss_latency::cpu0.data 8580000 # number of overall miss cycles
1053 system.l2c.overall_miss_latency::cpu1.inst 3402000 # number of overall miss cycles
1054 system.l2c.overall_miss_latency::cpu1.data 1191000 # number of overall miss cycles
1055 system.l2c.overall_miss_latency::cpu2.inst 615000 # number of overall miss cycles
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1070 system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses)
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1102 system.l2c.ReadReq_miss_rate::cpu1.data 0.727273 # miss rate for ReadReq accesses
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1110 system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses
1111 system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses
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1173 system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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1239 system.l2c.ReadReq_mshr_miss_latency::total 17203000 # number of ReadReq MSHR miss cycles
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1244 system.l2c.UpgradeReq_mshr_miss_latency::total 2760000 # number of UpgradeReq MSHR miss cycles
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1267 system.l2c.overall_mshr_miss_latency::total 22883000 # number of overall MSHR miss cycles
1268 system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for ReadReq accesses
1269 system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.929577 # mshr miss rate for ReadReq accesses
1270 system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.161202 # mshr miss rate for ReadReq accesses
1271 system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.636364 # mshr miss rate for ReadReq accesses
1272 system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.024590 # mshr miss rate for ReadReq accesses
1273 system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.181818 # mshr miss rate for ReadReq accesses
1274 system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.002725 # mshr miss rate for ReadReq accesses
1275 system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.090909 # mshr miss rate for ReadReq accesses
1276 system.l2c.ReadReq_mshr_miss_rate::total 0.257485 # mshr miss rate for ReadReq accesses
1277 system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.933333 # mshr miss rate for UpgradeReq accesses
1278 system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses
1279 system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses
1280 system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses
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1282 system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses
1283 system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses
1284 system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses
1285 system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses
1286 system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
1287 system.l2c.demand_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for demand accesses
1288 system.l2c.demand_mshr_miss_rate::cpu0.data 0.970588 # mshr miss rate for demand accesses
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1290 system.l2c.demand_mshr_miss_rate::cpu1.data 0.846154 # mshr miss rate for demand accesses
1291 system.l2c.demand_mshr_miss_rate::cpu2.inst 0.024590 # mshr miss rate for demand accesses
1292 system.l2c.demand_mshr_miss_rate::cpu2.data 0.640000 # mshr miss rate for demand accesses
1293 system.l2c.demand_mshr_miss_rate::cpu3.inst 0.002725 # mshr miss rate for demand accesses
1294 system.l2c.demand_mshr_miss_rate::cpu3.data 0.600000 # mshr miss rate for demand accesses
1295 system.l2c.demand_mshr_miss_rate::total 0.315673 # mshr miss rate for demand accesses
1296 system.l2c.overall_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for overall accesses
1297 system.l2c.overall_mshr_miss_rate::cpu0.data 0.970588 # mshr miss rate for overall accesses
1298 system.l2c.overall_mshr_miss_rate::cpu1.inst 0.161202 # mshr miss rate for overall accesses
1299 system.l2c.overall_mshr_miss_rate::cpu1.data 0.846154 # mshr miss rate for overall accesses
1300 system.l2c.overall_mshr_miss_rate::cpu2.inst 0.024590 # mshr miss rate for overall accesses
1301 system.l2c.overall_mshr_miss_rate::cpu2.data 0.640000 # mshr miss rate for overall accesses
1302 system.l2c.overall_mshr_miss_rate::cpu3.inst 0.002725 # mshr miss rate for overall accesses
1303 system.l2c.overall_mshr_miss_rate::cpu3.data 0.600000 # mshr miss rate for overall accesses
1304 system.l2c.overall_mshr_miss_rate::total 0.315673 # mshr miss rate for overall accesses
1305 system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40007.017544 # average ReadReq mshr miss latency
1306 system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40000 # average ReadReq mshr miss latency
1307 system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40000 # average ReadReq mshr miss latency
1308 system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40000 # average ReadReq mshr miss latency
1309 system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 40111.111111 # average ReadReq mshr miss latency
1310 system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 40000 # average ReadReq mshr miss latency
1311 system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 40000 # average ReadReq mshr miss latency
1312 system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 40000 # average ReadReq mshr miss latency
1313 system.l2c.ReadReq_avg_mshr_miss_latency::total 40006.976744 # average ReadReq mshr miss latency
1314 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40000 # average UpgradeReq mshr miss latency
1315 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40000 # average UpgradeReq mshr miss latency
1316 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 40000 # average UpgradeReq mshr miss latency
1317 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 40000 # average UpgradeReq mshr miss latency
1318 system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40000 # average UpgradeReq mshr miss latency
1319 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40000 # average ReadExReq mshr miss latency
1320 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40000 # average ReadExReq mshr miss latency
1321 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 40000 # average ReadExReq mshr miss latency
1322 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 40000 # average ReadExReq mshr miss latency
1323 system.l2c.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
1324 system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40007.017544 # average overall mshr miss latency
1325 system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40000 # average overall mshr miss latency
1326 system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40000 # average overall mshr miss latency
1327 system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40000 # average overall mshr miss latency
1328 system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40111.111111 # average overall mshr miss latency
1329 system.l2c.demand_avg_mshr_miss_latency::cpu2.data 40000 # average overall mshr miss latency
1330 system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency
1331 system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40000 # average overall mshr miss latency
1332 system.l2c.demand_avg_mshr_miss_latency::total 40005.244755 # average overall mshr miss latency
1333 system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40007.017544 # average overall mshr miss latency
1334 system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40000 # average overall mshr miss latency
1335 system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40000 # average overall mshr miss latency
1336 system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40000 # average overall mshr miss latency
1337 system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40111.111111 # average overall mshr miss latency
1338 system.l2c.overall_avg_mshr_miss_latency::cpu2.data 40000 # average overall mshr miss latency
1339 system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency
1340 system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40000 # average overall mshr miss latency
1341 system.l2c.overall_avg_mshr_miss_latency::total 40005.244755 # average overall mshr miss latency
1342 system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
1344 ---------- End Simulation Statistics ----------
projects / gem5.git / blob