2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.000262 # Number of seconds simulated
4 sim_ticks 262298000 # Number of ticks simulated
5 final_tick 262298000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 1330969 # Simulator instruction rate (inst/s)
8 host_op_rate 1330920 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 527074583 # Simulator tick rate (ticks/s)
10 host_mem_usage 221728 # Number of bytes of host memory used
11 host_seconds 0.50 # Real time elapsed on the host
12 sim_insts 662307 # Number of instructions simulated
13 sim_ops 662307 # Number of ops (including micro ops) simulated
14 system.physmem.bytes_read 36608 # Number of bytes read from this memory
15 system.physmem.bytes_inst_read 22656 # Number of instructions bytes read from this memory
16 system.physmem.bytes_written 0 # Number of bytes written to this memory
17 system.physmem.num_reads 572 # Number of read requests responded to by this memory
18 system.physmem.num_writes 0 # Number of write requests responded to by this memory
19 system.physmem.num_other 0 # Number of other requests responded to by this memory
20 system.physmem.bw_read 139566447 # Total read bandwidth from this memory (bytes/s)
21 system.physmem.bw_inst_read 86375039 # Instruction read bandwidth from this memory (bytes/s)
22 system.physmem.bw_total 139566447 # Total bandwidth to/from this memory (bytes/s)
23 system.cpu0.workload.num_syscalls 89 # Number of system calls
24 system.cpu0.numCycles 524596 # number of cpu cycles simulated
25 system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
26 system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
27 system.cpu0.committedInsts 158353 # Number of instructions committed
28 system.cpu0.committedOps 158353 # Number of ops (including micro ops) committed
29 system.cpu0.num_int_alu_accesses 109064 # Number of integer alu accesses
30 system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses
31 system.cpu0.num_func_calls 390 # number of times a function call or return occured
32 system.cpu0.num_conditional_control_insts 25994 # number of instructions that are conditional controls
33 system.cpu0.num_int_insts 109064 # number of integer instructions
34 system.cpu0.num_fp_insts 0 # number of float instructions
35 system.cpu0.num_int_register_reads 315336 # number of times the integer registers were read
36 system.cpu0.num_int_register_writes 110671 # number of times the integer registers were written
37 system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read
38 system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written
39 system.cpu0.num_mem_refs 73905 # number of memory refs
40 system.cpu0.num_load_insts 48930 # Number of load instructions
41 system.cpu0.num_store_insts 24975 # Number of store instructions
42 system.cpu0.num_idle_cycles 0 # Number of idle cycles
43 system.cpu0.num_busy_cycles 524596 # Number of busy cycles
44 system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles
45 system.cpu0.idle_fraction 0 # Percentage of idle cycles
46 system.cpu0.icache.replacements 215 # number of replacements
47 system.cpu0.icache.tagsinuse 212.479188 # Cycle average of tags in use
48 system.cpu0.icache.total_refs 157949 # Total number of references to valid blocks.
49 system.cpu0.icache.sampled_refs 467 # Sample count of references to valid blocks.
50 system.cpu0.icache.avg_refs 338.220557 # Average number of references to valid blocks.
51 system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
52 system.cpu0.icache.occ_blocks::cpu0.inst 212.479188 # Average occupied blocks per requestor
53 system.cpu0.icache.occ_percent::cpu0.inst 0.414998 # Average percentage of cache occupancy
54 system.cpu0.icache.occ_percent::total 0.414998 # Average percentage of cache occupancy
55 system.cpu0.icache.ReadReq_hits::cpu0.inst 157949 # number of ReadReq hits
56 system.cpu0.icache.ReadReq_hits::total 157949 # number of ReadReq hits
57 system.cpu0.icache.demand_hits::cpu0.inst 157949 # number of demand (read+write) hits
58 system.cpu0.icache.demand_hits::total 157949 # number of demand (read+write) hits
59 system.cpu0.icache.overall_hits::cpu0.inst 157949 # number of overall hits
60 system.cpu0.icache.overall_hits::total 157949 # number of overall hits
61 system.cpu0.icache.ReadReq_misses::cpu0.inst 467 # number of ReadReq misses
62 system.cpu0.icache.ReadReq_misses::total 467 # number of ReadReq misses
63 system.cpu0.icache.demand_misses::cpu0.inst 467 # number of demand (read+write) misses
64 system.cpu0.icache.demand_misses::total 467 # number of demand (read+write) misses
65 system.cpu0.icache.overall_misses::cpu0.inst 467 # number of overall misses
66 system.cpu0.icache.overall_misses::total 467 # number of overall misses
67 system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 18524000 # number of ReadReq miss cycles
68 system.cpu0.icache.ReadReq_miss_latency::total 18524000 # number of ReadReq miss cycles
69 system.cpu0.icache.demand_miss_latency::cpu0.inst 18524000 # number of demand (read+write) miss cycles
70 system.cpu0.icache.demand_miss_latency::total 18524000 # number of demand (read+write) miss cycles
71 system.cpu0.icache.overall_miss_latency::cpu0.inst 18524000 # number of overall miss cycles
72 system.cpu0.icache.overall_miss_latency::total 18524000 # number of overall miss cycles
73 system.cpu0.icache.ReadReq_accesses::cpu0.inst 158416 # number of ReadReq accesses(hits+misses)
74 system.cpu0.icache.ReadReq_accesses::total 158416 # number of ReadReq accesses(hits+misses)
75 system.cpu0.icache.demand_accesses::cpu0.inst 158416 # number of demand (read+write) accesses
76 system.cpu0.icache.demand_accesses::total 158416 # number of demand (read+write) accesses
77 system.cpu0.icache.overall_accesses::cpu0.inst 158416 # number of overall (read+write) accesses
78 system.cpu0.icache.overall_accesses::total 158416 # number of overall (read+write) accesses
79 system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002948 # miss rate for ReadReq accesses
80 system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002948 # miss rate for demand accesses
81 system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002948 # miss rate for overall accesses
82 system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 39665.952891 # average ReadReq miss latency
83 system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 39665.952891 # average overall miss latency
84 system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 39665.952891 # average overall miss latency
85 system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
86 system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
87 system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
88 system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
89 system.cpu0.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
90 system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
91 system.cpu0.icache.fast_writes 0 # number of fast writes performed
92 system.cpu0.icache.cache_copies 0 # number of cache copies performed
93 system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 467 # number of ReadReq MSHR misses
94 system.cpu0.icache.ReadReq_mshr_misses::total 467 # number of ReadReq MSHR misses
95 system.cpu0.icache.demand_mshr_misses::cpu0.inst 467 # number of demand (read+write) MSHR misses
96 system.cpu0.icache.demand_mshr_misses::total 467 # number of demand (read+write) MSHR misses
97 system.cpu0.icache.overall_mshr_misses::cpu0.inst 467 # number of overall MSHR misses
98 system.cpu0.icache.overall_mshr_misses::total 467 # number of overall MSHR misses
99 system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 17123000 # number of ReadReq MSHR miss cycles
100 system.cpu0.icache.ReadReq_mshr_miss_latency::total 17123000 # number of ReadReq MSHR miss cycles
101 system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 17123000 # number of demand (read+write) MSHR miss cycles
102 system.cpu0.icache.demand_mshr_miss_latency::total 17123000 # number of demand (read+write) MSHR miss cycles
103 system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 17123000 # number of overall MSHR miss cycles
104 system.cpu0.icache.overall_mshr_miss_latency::total 17123000 # number of overall MSHR miss cycles
105 system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.002948 # mshr miss rate for ReadReq accesses
106 system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.002948 # mshr miss rate for demand accesses
107 system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.002948 # mshr miss rate for overall accesses
108 system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36665.952891 # average ReadReq mshr miss latency
109 system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 36665.952891 # average overall mshr miss latency
110 system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 36665.952891 # average overall mshr miss latency
111 system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
112 system.cpu0.dcache.replacements 9 # number of replacements
113 system.cpu0.dcache.tagsinuse 141.233342 # Cycle average of tags in use
114 system.cpu0.dcache.total_refs 56009 # Total number of references to valid blocks.
115 system.cpu0.dcache.sampled_refs 170 # Sample count of references to valid blocks.
116 system.cpu0.dcache.avg_refs 329.464706 # Average number of references to valid blocks.
117 system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
118 system.cpu0.dcache.occ_blocks::cpu0.data 141.233342 # Average occupied blocks per requestor
119 system.cpu0.dcache.occ_percent::cpu0.data 0.275846 # Average percentage of cache occupancy
120 system.cpu0.dcache.occ_percent::total 0.275846 # Average percentage of cache occupancy
121 system.cpu0.dcache.ReadReq_hits::cpu0.data 48758 # number of ReadReq hits
122 system.cpu0.dcache.ReadReq_hits::total 48758 # number of ReadReq hits
123 system.cpu0.dcache.WriteReq_hits::cpu0.data 24741 # number of WriteReq hits
124 system.cpu0.dcache.WriteReq_hits::total 24741 # number of WriteReq hits
125 system.cpu0.dcache.SwapReq_hits::cpu0.data 16 # number of SwapReq hits
126 system.cpu0.dcache.SwapReq_hits::total 16 # number of SwapReq hits
127 system.cpu0.dcache.demand_hits::cpu0.data 73499 # number of demand (read+write) hits
128 system.cpu0.dcache.demand_hits::total 73499 # number of demand (read+write) hits
129 system.cpu0.dcache.overall_hits::cpu0.data 73499 # number of overall hits
130 system.cpu0.dcache.overall_hits::total 73499 # number of overall hits
131 system.cpu0.dcache.ReadReq_misses::cpu0.data 162 # number of ReadReq misses
132 system.cpu0.dcache.ReadReq_misses::total 162 # number of ReadReq misses
133 system.cpu0.dcache.WriteReq_misses::cpu0.data 183 # number of WriteReq misses
134 system.cpu0.dcache.WriteReq_misses::total 183 # number of WriteReq misses
135 system.cpu0.dcache.SwapReq_misses::cpu0.data 26 # number of SwapReq misses
136 system.cpu0.dcache.SwapReq_misses::total 26 # number of SwapReq misses
137 system.cpu0.dcache.demand_misses::cpu0.data 345 # number of demand (read+write) misses
138 system.cpu0.dcache.demand_misses::total 345 # number of demand (read+write) misses
139 system.cpu0.dcache.overall_misses::cpu0.data 345 # number of overall misses
140 system.cpu0.dcache.overall_misses::total 345 # number of overall misses
141 system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4749000 # number of ReadReq miss cycles
142 system.cpu0.dcache.ReadReq_miss_latency::total 4749000 # number of ReadReq miss cycles
143 system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7175000 # number of WriteReq miss cycles
144 system.cpu0.dcache.WriteReq_miss_latency::total 7175000 # number of WriteReq miss cycles
145 system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 387000 # number of SwapReq miss cycles
146 system.cpu0.dcache.SwapReq_miss_latency::total 387000 # number of SwapReq miss cycles
147 system.cpu0.dcache.demand_miss_latency::cpu0.data 11924000 # number of demand (read+write) miss cycles
148 system.cpu0.dcache.demand_miss_latency::total 11924000 # number of demand (read+write) miss cycles
149 system.cpu0.dcache.overall_miss_latency::cpu0.data 11924000 # number of overall miss cycles
150 system.cpu0.dcache.overall_miss_latency::total 11924000 # number of overall miss cycles
151 system.cpu0.dcache.ReadReq_accesses::cpu0.data 48920 # number of ReadReq accesses(hits+misses)
152 system.cpu0.dcache.ReadReq_accesses::total 48920 # number of ReadReq accesses(hits+misses)
153 system.cpu0.dcache.WriteReq_accesses::cpu0.data 24924 # number of WriteReq accesses(hits+misses)
154 system.cpu0.dcache.WriteReq_accesses::total 24924 # number of WriteReq accesses(hits+misses)
155 system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses)
156 system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses)
157 system.cpu0.dcache.demand_accesses::cpu0.data 73844 # number of demand (read+write) accesses
158 system.cpu0.dcache.demand_accesses::total 73844 # number of demand (read+write) accesses
159 system.cpu0.dcache.overall_accesses::cpu0.data 73844 # number of overall (read+write) accesses
160 system.cpu0.dcache.overall_accesses::total 73844 # number of overall (read+write) accesses
161 system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.003312 # miss rate for ReadReq accesses
162 system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007342 # miss rate for WriteReq accesses
163 system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.619048 # miss rate for SwapReq accesses
164 system.cpu0.dcache.demand_miss_rate::cpu0.data 0.004672 # miss rate for demand accesses
165 system.cpu0.dcache.overall_miss_rate::cpu0.data 0.004672 # miss rate for overall accesses
166 system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 29314.814815 # average ReadReq miss latency
167 system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 39207.650273 # average WriteReq miss latency
168 system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 14884.615385 # average SwapReq miss latency
169 system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 34562.318841 # average overall miss latency
170 system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 34562.318841 # average overall miss latency
171 system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
172 system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
173 system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
174 system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
175 system.cpu0.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
176 system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
177 system.cpu0.dcache.fast_writes 0 # number of fast writes performed
178 system.cpu0.dcache.cache_copies 0 # number of cache copies performed
179 system.cpu0.dcache.writebacks::writebacks 6 # number of writebacks
180 system.cpu0.dcache.writebacks::total 6 # number of writebacks
181 system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 162 # number of ReadReq MSHR misses
182 system.cpu0.dcache.ReadReq_mshr_misses::total 162 # number of ReadReq MSHR misses
183 system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 183 # number of WriteReq MSHR misses
184 system.cpu0.dcache.WriteReq_mshr_misses::total 183 # number of WriteReq MSHR misses
185 system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 26 # number of SwapReq MSHR misses
186 system.cpu0.dcache.SwapReq_mshr_misses::total 26 # number of SwapReq MSHR misses
187 system.cpu0.dcache.demand_mshr_misses::cpu0.data 345 # number of demand (read+write) MSHR misses
188 system.cpu0.dcache.demand_mshr_misses::total 345 # number of demand (read+write) MSHR misses
189 system.cpu0.dcache.overall_mshr_misses::cpu0.data 345 # number of overall MSHR misses
190 system.cpu0.dcache.overall_mshr_misses::total 345 # number of overall MSHR misses
191 system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4263000 # number of ReadReq MSHR miss cycles
192 system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4263000 # number of ReadReq MSHR miss cycles
193 system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6626000 # number of WriteReq MSHR miss cycles
194 system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6626000 # number of WriteReq MSHR miss cycles
195 system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 309000 # number of SwapReq MSHR miss cycles
196 system.cpu0.dcache.SwapReq_mshr_miss_latency::total 309000 # number of SwapReq MSHR miss cycles
197 system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10889000 # number of demand (read+write) MSHR miss cycles
198 system.cpu0.dcache.demand_mshr_miss_latency::total 10889000 # number of demand (read+write) MSHR miss cycles
199 system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10889000 # number of overall MSHR miss cycles
200 system.cpu0.dcache.overall_mshr_miss_latency::total 10889000 # number of overall MSHR miss cycles
201 system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.003312 # mshr miss rate for ReadReq accesses
202 system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.007342 # mshr miss rate for WriteReq accesses
203 system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.619048 # mshr miss rate for SwapReq accesses
204 system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.004672 # mshr miss rate for demand accesses
205 system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.004672 # mshr miss rate for overall accesses
206 system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26314.814815 # average ReadReq mshr miss latency
207 system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36207.650273 # average WriteReq mshr miss latency
208 system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 11884.615385 # average SwapReq mshr miss latency
209 system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31562.318841 # average overall mshr miss latency
210 system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31562.318841 # average overall mshr miss latency
211 system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
212 system.cpu1.numCycles 524596 # number of cpu cycles simulated
213 system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
214 system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
215 system.cpu1.committedInsts 172325 # Number of instructions committed
216 system.cpu1.committedOps 172325 # Number of ops (including micro ops) committed
217 system.cpu1.num_int_alu_accesses 107932 # Number of integer alu accesses
218 system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses
219 system.cpu1.num_func_calls 637 # number of times a function call or return occured
220 system.cpu1.num_conditional_control_insts 36203 # number of instructions that are conditional controls
221 system.cpu1.num_int_insts 107932 # number of integer instructions
222 system.cpu1.num_fp_insts 0 # number of float instructions
223 system.cpu1.num_int_register_reads 249091 # number of times the integer registers were read
224 system.cpu1.num_int_register_writes 92744 # number of times the integer registers were written
225 system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read
226 system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written
227 system.cpu1.num_mem_refs 47898 # number of memory refs
228 system.cpu1.num_load_insts 39616 # Number of load instructions
229 system.cpu1.num_store_insts 8282 # Number of store instructions
230 system.cpu1.num_idle_cycles 68578.001739 # Number of idle cycles
231 system.cpu1.num_busy_cycles 456017.998261 # Number of busy cycles
232 system.cpu1.not_idle_fraction 0.869275 # Percentage of non-idle cycles
233 system.cpu1.idle_fraction 0.130725 # Percentage of idle cycles
234 system.cpu1.icache.replacements 280 # number of replacements
235 system.cpu1.icache.tagsinuse 70.076133 # Cycle average of tags in use
236 system.cpu1.icache.total_refs 171992 # Total number of references to valid blocks.
237 system.cpu1.icache.sampled_refs 366 # Sample count of references to valid blocks.
238 system.cpu1.icache.avg_refs 469.923497 # Average number of references to valid blocks.
239 system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
240 system.cpu1.icache.occ_blocks::cpu1.inst 70.076133 # Average occupied blocks per requestor
241 system.cpu1.icache.occ_percent::cpu1.inst 0.136867 # Average percentage of cache occupancy
242 system.cpu1.icache.occ_percent::total 0.136867 # Average percentage of cache occupancy
243 system.cpu1.icache.ReadReq_hits::cpu1.inst 171992 # number of ReadReq hits
244 system.cpu1.icache.ReadReq_hits::total 171992 # number of ReadReq hits
245 system.cpu1.icache.demand_hits::cpu1.inst 171992 # number of demand (read+write) hits
246 system.cpu1.icache.demand_hits::total 171992 # number of demand (read+write) hits
247 system.cpu1.icache.overall_hits::cpu1.inst 171992 # number of overall hits
248 system.cpu1.icache.overall_hits::total 171992 # number of overall hits
249 system.cpu1.icache.ReadReq_misses::cpu1.inst 366 # number of ReadReq misses
250 system.cpu1.icache.ReadReq_misses::total 366 # number of ReadReq misses
251 system.cpu1.icache.demand_misses::cpu1.inst 366 # number of demand (read+write) misses
252 system.cpu1.icache.demand_misses::total 366 # number of demand (read+write) misses
253 system.cpu1.icache.overall_misses::cpu1.inst 366 # number of overall misses
254 system.cpu1.icache.overall_misses::total 366 # number of overall misses
255 system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7920500 # number of ReadReq miss cycles
256 system.cpu1.icache.ReadReq_miss_latency::total 7920500 # number of ReadReq miss cycles
257 system.cpu1.icache.demand_miss_latency::cpu1.inst 7920500 # number of demand (read+write) miss cycles
258 system.cpu1.icache.demand_miss_latency::total 7920500 # number of demand (read+write) miss cycles
259 system.cpu1.icache.overall_miss_latency::cpu1.inst 7920500 # number of overall miss cycles
260 system.cpu1.icache.overall_miss_latency::total 7920500 # number of overall miss cycles
261 system.cpu1.icache.ReadReq_accesses::cpu1.inst 172358 # number of ReadReq accesses(hits+misses)
262 system.cpu1.icache.ReadReq_accesses::total 172358 # number of ReadReq accesses(hits+misses)
263 system.cpu1.icache.demand_accesses::cpu1.inst 172358 # number of demand (read+write) accesses
264 system.cpu1.icache.demand_accesses::total 172358 # number of demand (read+write) accesses
265 system.cpu1.icache.overall_accesses::cpu1.inst 172358 # number of overall (read+write) accesses
266 system.cpu1.icache.overall_accesses::total 172358 # number of overall (read+write) accesses
267 system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002123 # miss rate for ReadReq accesses
268 system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002123 # miss rate for demand accesses
269 system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002123 # miss rate for overall accesses
270 system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 21640.710383 # average ReadReq miss latency
271 system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 21640.710383 # average overall miss latency
272 system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 21640.710383 # average overall miss latency
273 system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
274 system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
275 system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
276 system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
277 system.cpu1.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
278 system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
279 system.cpu1.icache.fast_writes 0 # number of fast writes performed
280 system.cpu1.icache.cache_copies 0 # number of cache copies performed
281 system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 366 # number of ReadReq MSHR misses
282 system.cpu1.icache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses
283 system.cpu1.icache.demand_mshr_misses::cpu1.inst 366 # number of demand (read+write) MSHR misses
284 system.cpu1.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses
285 system.cpu1.icache.overall_mshr_misses::cpu1.inst 366 # number of overall MSHR misses
286 system.cpu1.icache.overall_mshr_misses::total 366 # number of overall MSHR misses
287 system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6822000 # number of ReadReq MSHR miss cycles
288 system.cpu1.icache.ReadReq_mshr_miss_latency::total 6822000 # number of ReadReq MSHR miss cycles
289 system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6822000 # number of demand (read+write) MSHR miss cycles
290 system.cpu1.icache.demand_mshr_miss_latency::total 6822000 # number of demand (read+write) MSHR miss cycles
291 system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6822000 # number of overall MSHR miss cycles
292 system.cpu1.icache.overall_mshr_miss_latency::total 6822000 # number of overall MSHR miss cycles
293 system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.002123 # mshr miss rate for ReadReq accesses
294 system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.002123 # mshr miss rate for demand accesses
295 system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.002123 # mshr miss rate for overall accesses
296 system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 18639.344262 # average ReadReq mshr miss latency
297 system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 18639.344262 # average overall mshr miss latency
298 system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 18639.344262 # average overall mshr miss latency
299 system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
300 system.cpu1.dcache.replacements 2 # number of replacements
301 system.cpu1.dcache.tagsinuse 26.693562 # Cycle average of tags in use
302 system.cpu1.dcache.total_refs 18908 # Total number of references to valid blocks.
303 system.cpu1.dcache.sampled_refs 31 # Sample count of references to valid blocks.
304 system.cpu1.dcache.avg_refs 609.935484 # Average number of references to valid blocks.
305 system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
306 system.cpu1.dcache.occ_blocks::cpu1.data 26.693562 # Average occupied blocks per requestor
307 system.cpu1.dcache.occ_percent::cpu1.data 0.052136 # Average percentage of cache occupancy
308 system.cpu1.dcache.occ_percent::total 0.052136 # Average percentage of cache occupancy
309 system.cpu1.dcache.ReadReq_hits::cpu1.data 39428 # number of ReadReq hits
310 system.cpu1.dcache.ReadReq_hits::total 39428 # number of ReadReq hits
311 system.cpu1.dcache.WriteReq_hits::cpu1.data 8099 # number of WriteReq hits
312 system.cpu1.dcache.WriteReq_hits::total 8099 # number of WriteReq hits
313 system.cpu1.dcache.SwapReq_hits::cpu1.data 18 # number of SwapReq hits
314 system.cpu1.dcache.SwapReq_hits::total 18 # number of SwapReq hits
315 system.cpu1.dcache.demand_hits::cpu1.data 47527 # number of demand (read+write) hits
316 system.cpu1.dcache.demand_hits::total 47527 # number of demand (read+write) hits
317 system.cpu1.dcache.overall_hits::cpu1.data 47527 # number of overall hits
318 system.cpu1.dcache.overall_hits::total 47527 # number of overall hits
319 system.cpu1.dcache.ReadReq_misses::cpu1.data 181 # number of ReadReq misses
320 system.cpu1.dcache.ReadReq_misses::total 181 # number of ReadReq misses
321 system.cpu1.dcache.WriteReq_misses::cpu1.data 98 # number of WriteReq misses
322 system.cpu1.dcache.WriteReq_misses::total 98 # number of WriteReq misses
323 system.cpu1.dcache.SwapReq_misses::cpu1.data 65 # number of SwapReq misses
324 system.cpu1.dcache.SwapReq_misses::total 65 # number of SwapReq misses
325 system.cpu1.dcache.demand_misses::cpu1.data 279 # number of demand (read+write) misses
326 system.cpu1.dcache.demand_misses::total 279 # number of demand (read+write) misses
327 system.cpu1.dcache.overall_misses::cpu1.data 279 # number of overall misses
328 system.cpu1.dcache.overall_misses::total 279 # number of overall misses
329 system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3713000 # number of ReadReq miss cycles
330 system.cpu1.dcache.ReadReq_miss_latency::total 3713000 # number of ReadReq miss cycles
331 system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1889000 # number of WriteReq miss cycles
332 system.cpu1.dcache.WriteReq_miss_latency::total 1889000 # number of WriteReq miss cycles
333 system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 415000 # number of SwapReq miss cycles
334 system.cpu1.dcache.SwapReq_miss_latency::total 415000 # number of SwapReq miss cycles
335 system.cpu1.dcache.demand_miss_latency::cpu1.data 5602000 # number of demand (read+write) miss cycles
336 system.cpu1.dcache.demand_miss_latency::total 5602000 # number of demand (read+write) miss cycles
337 system.cpu1.dcache.overall_miss_latency::cpu1.data 5602000 # number of overall miss cycles
338 system.cpu1.dcache.overall_miss_latency::total 5602000 # number of overall miss cycles
339 system.cpu1.dcache.ReadReq_accesses::cpu1.data 39609 # number of ReadReq accesses(hits+misses)
340 system.cpu1.dcache.ReadReq_accesses::total 39609 # number of ReadReq accesses(hits+misses)
341 system.cpu1.dcache.WriteReq_accesses::cpu1.data 8197 # number of WriteReq accesses(hits+misses)
342 system.cpu1.dcache.WriteReq_accesses::total 8197 # number of WriteReq accesses(hits+misses)
343 system.cpu1.dcache.SwapReq_accesses::cpu1.data 83 # number of SwapReq accesses(hits+misses)
344 system.cpu1.dcache.SwapReq_accesses::total 83 # number of SwapReq accesses(hits+misses)
345 system.cpu1.dcache.demand_accesses::cpu1.data 47806 # number of demand (read+write) accesses
346 system.cpu1.dcache.demand_accesses::total 47806 # number of demand (read+write) accesses
347 system.cpu1.dcache.overall_accesses::cpu1.data 47806 # number of overall (read+write) accesses
348 system.cpu1.dcache.overall_accesses::total 47806 # number of overall (read+write) accesses
349 system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.004570 # miss rate for ReadReq accesses
350 system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.011956 # miss rate for WriteReq accesses
351 system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.783133 # miss rate for SwapReq accesses
352 system.cpu1.dcache.demand_miss_rate::cpu1.data 0.005836 # miss rate for demand accesses
353 system.cpu1.dcache.overall_miss_rate::cpu1.data 0.005836 # miss rate for overall accesses
354 system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 20513.812155 # average ReadReq miss latency
355 system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 19275.510204 # average WriteReq miss latency
356 system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 6384.615385 # average SwapReq miss latency
357 system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20078.853047 # average overall miss latency
358 system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20078.853047 # average overall miss latency
359 system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
360 system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
361 system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
362 system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
363 system.cpu1.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
364 system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
365 system.cpu1.dcache.fast_writes 0 # number of fast writes performed
366 system.cpu1.dcache.cache_copies 0 # number of cache copies performed
367 system.cpu1.dcache.writebacks::writebacks 1 # number of writebacks
368 system.cpu1.dcache.writebacks::total 1 # number of writebacks
369 system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 181 # number of ReadReq MSHR misses
370 system.cpu1.dcache.ReadReq_mshr_misses::total 181 # number of ReadReq MSHR misses
371 system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 98 # number of WriteReq MSHR misses
372 system.cpu1.dcache.WriteReq_mshr_misses::total 98 # number of WriteReq MSHR misses
373 system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 65 # number of SwapReq MSHR misses
374 system.cpu1.dcache.SwapReq_mshr_misses::total 65 # number of SwapReq MSHR misses
375 system.cpu1.dcache.demand_mshr_misses::cpu1.data 279 # number of demand (read+write) MSHR misses
376 system.cpu1.dcache.demand_mshr_misses::total 279 # number of demand (read+write) MSHR misses
377 system.cpu1.dcache.overall_mshr_misses::cpu1.data 279 # number of overall MSHR misses
378 system.cpu1.dcache.overall_mshr_misses::total 279 # number of overall MSHR misses
379 system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 3170000 # number of ReadReq MSHR miss cycles
380 system.cpu1.dcache.ReadReq_mshr_miss_latency::total 3170000 # number of ReadReq MSHR miss cycles
381 system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1595000 # number of WriteReq MSHR miss cycles
382 system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1595000 # number of WriteReq MSHR miss cycles
383 system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 220000 # number of SwapReq MSHR miss cycles
384 system.cpu1.dcache.SwapReq_mshr_miss_latency::total 220000 # number of SwapReq MSHR miss cycles
385 system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4765000 # number of demand (read+write) MSHR miss cycles
386 system.cpu1.dcache.demand_mshr_miss_latency::total 4765000 # number of demand (read+write) MSHR miss cycles
387 system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4765000 # number of overall MSHR miss cycles
388 system.cpu1.dcache.overall_mshr_miss_latency::total 4765000 # number of overall MSHR miss cycles
389 system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.004570 # mshr miss rate for ReadReq accesses
390 system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.011956 # mshr miss rate for WriteReq accesses
391 system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.783133 # mshr miss rate for SwapReq accesses
392 system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.005836 # mshr miss rate for demand accesses
393 system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.005836 # mshr miss rate for overall accesses
394 system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 17513.812155 # average ReadReq mshr miss latency
395 system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16275.510204 # average WriteReq mshr miss latency
396 system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 3384.615385 # average SwapReq mshr miss latency
397 system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17078.853047 # average overall mshr miss latency
398 system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17078.853047 # average overall mshr miss latency
399 system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
400 system.cpu2.numCycles 524596 # number of cpu cycles simulated
401 system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
402 system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
403 system.cpu2.committedInsts 165499 # Number of instructions committed
404 system.cpu2.committedOps 165499 # Number of ops (including micro ops) committed
405 system.cpu2.num_int_alu_accesses 112355 # Number of integer alu accesses
406 system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses
407 system.cpu2.num_func_calls 637 # number of times a function call or return occured
408 system.cpu2.num_conditional_control_insts 30582 # number of instructions that are conditional controls
409 system.cpu2.num_int_insts 112355 # number of integer instructions
410 system.cpu2.num_fp_insts 0 # number of float instructions
411 system.cpu2.num_int_register_reads 289268 # number of times the integer registers were read
412 system.cpu2.num_int_register_writes 110631 # number of times the integer registers were written
413 system.cpu2.num_fp_register_reads 0 # number of times the floating registers were read
414 system.cpu2.num_fp_register_writes 0 # number of times the floating registers were written
415 system.cpu2.num_mem_refs 57941 # number of memory refs
416 system.cpu2.num_load_insts 41852 # Number of load instructions
417 system.cpu2.num_store_insts 16089 # Number of store instructions
418 system.cpu2.num_idle_cycles 68840.001738 # Number of idle cycles
419 system.cpu2.num_busy_cycles 455755.998262 # Number of busy cycles
420 system.cpu2.not_idle_fraction 0.868775 # Percentage of non-idle cycles
421 system.cpu2.idle_fraction 0.131225 # Percentage of idle cycles
422 system.cpu2.icache.replacements 280 # number of replacements
423 system.cpu2.icache.tagsinuse 65.601019 # Cycle average of tags in use
424 system.cpu2.icache.total_refs 165166 # Total number of references to valid blocks.
425 system.cpu2.icache.sampled_refs 366 # Sample count of references to valid blocks.
426 system.cpu2.icache.avg_refs 451.273224 # Average number of references to valid blocks.
427 system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
428 system.cpu2.icache.occ_blocks::cpu2.inst 65.601019 # Average occupied blocks per requestor
429 system.cpu2.icache.occ_percent::cpu2.inst 0.128127 # Average percentage of cache occupancy
430 system.cpu2.icache.occ_percent::total 0.128127 # Average percentage of cache occupancy
431 system.cpu2.icache.ReadReq_hits::cpu2.inst 165166 # number of ReadReq hits
432 system.cpu2.icache.ReadReq_hits::total 165166 # number of ReadReq hits
433 system.cpu2.icache.demand_hits::cpu2.inst 165166 # number of demand (read+write) hits
434 system.cpu2.icache.demand_hits::total 165166 # number of demand (read+write) hits
435 system.cpu2.icache.overall_hits::cpu2.inst 165166 # number of overall hits
436 system.cpu2.icache.overall_hits::total 165166 # number of overall hits
437 system.cpu2.icache.ReadReq_misses::cpu2.inst 366 # number of ReadReq misses
438 system.cpu2.icache.ReadReq_misses::total 366 # number of ReadReq misses
439 system.cpu2.icache.demand_misses::cpu2.inst 366 # number of demand (read+write) misses
440 system.cpu2.icache.demand_misses::total 366 # number of demand (read+write) misses
441 system.cpu2.icache.overall_misses::cpu2.inst 366 # number of overall misses
442 system.cpu2.icache.overall_misses::total 366 # number of overall misses
443 system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 5648500 # number of ReadReq miss cycles
444 system.cpu2.icache.ReadReq_miss_latency::total 5648500 # number of ReadReq miss cycles
445 system.cpu2.icache.demand_miss_latency::cpu2.inst 5648500 # number of demand (read+write) miss cycles
446 system.cpu2.icache.demand_miss_latency::total 5648500 # number of demand (read+write) miss cycles
447 system.cpu2.icache.overall_miss_latency::cpu2.inst 5648500 # number of overall miss cycles
448 system.cpu2.icache.overall_miss_latency::total 5648500 # number of overall miss cycles
449 system.cpu2.icache.ReadReq_accesses::cpu2.inst 165532 # number of ReadReq accesses(hits+misses)
450 system.cpu2.icache.ReadReq_accesses::total 165532 # number of ReadReq accesses(hits+misses)
451 system.cpu2.icache.demand_accesses::cpu2.inst 165532 # number of demand (read+write) accesses
452 system.cpu2.icache.demand_accesses::total 165532 # number of demand (read+write) accesses
453 system.cpu2.icache.overall_accesses::cpu2.inst 165532 # number of overall (read+write) accesses
454 system.cpu2.icache.overall_accesses::total 165532 # number of overall (read+write) accesses
455 system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002211 # miss rate for ReadReq accesses
456 system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002211 # miss rate for demand accesses
457 system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002211 # miss rate for overall accesses
458 system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 15433.060109 # average ReadReq miss latency
459 system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 15433.060109 # average overall miss latency
460 system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 15433.060109 # average overall miss latency
461 system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
462 system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
463 system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked
464 system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked
465 system.cpu2.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
466 system.cpu2.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
467 system.cpu2.icache.fast_writes 0 # number of fast writes performed
468 system.cpu2.icache.cache_copies 0 # number of cache copies performed
469 system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 366 # number of ReadReq MSHR misses
470 system.cpu2.icache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses
471 system.cpu2.icache.demand_mshr_misses::cpu2.inst 366 # number of demand (read+write) MSHR misses
472 system.cpu2.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses
473 system.cpu2.icache.overall_mshr_misses::cpu2.inst 366 # number of overall MSHR misses
474 system.cpu2.icache.overall_mshr_misses::total 366 # number of overall MSHR misses
475 system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 4550500 # number of ReadReq MSHR miss cycles
476 system.cpu2.icache.ReadReq_mshr_miss_latency::total 4550500 # number of ReadReq MSHR miss cycles
477 system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 4550500 # number of demand (read+write) MSHR miss cycles
478 system.cpu2.icache.demand_mshr_miss_latency::total 4550500 # number of demand (read+write) MSHR miss cycles
479 system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 4550500 # number of overall MSHR miss cycles
480 system.cpu2.icache.overall_mshr_miss_latency::total 4550500 # number of overall MSHR miss cycles
481 system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.002211 # mshr miss rate for ReadReq accesses
482 system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.002211 # mshr miss rate for demand accesses
483 system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.002211 # mshr miss rate for overall accesses
484 system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12433.060109 # average ReadReq mshr miss latency
485 system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 12433.060109 # average overall mshr miss latency
486 system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 12433.060109 # average overall mshr miss latency
487 system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate
488 system.cpu2.dcache.replacements 2 # number of replacements
489 system.cpu2.dcache.tagsinuse 24.943438 # Cycle average of tags in use
490 system.cpu2.dcache.total_refs 34578 # Total number of references to valid blocks.
491 system.cpu2.dcache.sampled_refs 31 # Sample count of references to valid blocks.
492 system.cpu2.dcache.avg_refs 1115.419355 # Average number of references to valid blocks.
493 system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
494 system.cpu2.dcache.occ_blocks::cpu2.data 24.943438 # Average occupied blocks per requestor
495 system.cpu2.dcache.occ_percent::cpu2.data 0.048718 # Average percentage of cache occupancy
496 system.cpu2.dcache.occ_percent::total 0.048718 # Average percentage of cache occupancy
497 system.cpu2.dcache.ReadReq_hits::cpu2.data 41688 # number of ReadReq hits
498 system.cpu2.dcache.ReadReq_hits::total 41688 # number of ReadReq hits
499 system.cpu2.dcache.WriteReq_hits::cpu2.data 15916 # number of WriteReq hits
500 system.cpu2.dcache.WriteReq_hits::total 15916 # number of WriteReq hits
501 system.cpu2.dcache.SwapReq_hits::cpu2.data 11 # number of SwapReq hits
502 system.cpu2.dcache.SwapReq_hits::total 11 # number of SwapReq hits
503 system.cpu2.dcache.demand_hits::cpu2.data 57604 # number of demand (read+write) hits
504 system.cpu2.dcache.demand_hits::total 57604 # number of demand (read+write) hits
505 system.cpu2.dcache.overall_hits::cpu2.data 57604 # number of overall hits
506 system.cpu2.dcache.overall_hits::total 57604 # number of overall hits
507 system.cpu2.dcache.ReadReq_misses::cpu2.data 156 # number of ReadReq misses
508 system.cpu2.dcache.ReadReq_misses::total 156 # number of ReadReq misses
509 system.cpu2.dcache.WriteReq_misses::cpu2.data 109 # number of WriteReq misses
510 system.cpu2.dcache.WriteReq_misses::total 109 # number of WriteReq misses
511 system.cpu2.dcache.SwapReq_misses::cpu2.data 51 # number of SwapReq misses
512 system.cpu2.dcache.SwapReq_misses::total 51 # number of SwapReq misses
513 system.cpu2.dcache.demand_misses::cpu2.data 265 # number of demand (read+write) misses
514 system.cpu2.dcache.demand_misses::total 265 # number of demand (read+write) misses
515 system.cpu2.dcache.overall_misses::cpu2.data 265 # number of overall misses
516 system.cpu2.dcache.overall_misses::total 265 # number of overall misses
517 system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 2527000 # number of ReadReq miss cycles
518 system.cpu2.dcache.ReadReq_miss_latency::total 2527000 # number of ReadReq miss cycles
519 system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2084000 # number of WriteReq miss cycles
520 system.cpu2.dcache.WriteReq_miss_latency::total 2084000 # number of WriteReq miss cycles
521 system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 305000 # number of SwapReq miss cycles
522 system.cpu2.dcache.SwapReq_miss_latency::total 305000 # number of SwapReq miss cycles
523 system.cpu2.dcache.demand_miss_latency::cpu2.data 4611000 # number of demand (read+write) miss cycles
524 system.cpu2.dcache.demand_miss_latency::total 4611000 # number of demand (read+write) miss cycles
525 system.cpu2.dcache.overall_miss_latency::cpu2.data 4611000 # number of overall miss cycles
526 system.cpu2.dcache.overall_miss_latency::total 4611000 # number of overall miss cycles
527 system.cpu2.dcache.ReadReq_accesses::cpu2.data 41844 # number of ReadReq accesses(hits+misses)
528 system.cpu2.dcache.ReadReq_accesses::total 41844 # number of ReadReq accesses(hits+misses)
529 system.cpu2.dcache.WriteReq_accesses::cpu2.data 16025 # number of WriteReq accesses(hits+misses)
530 system.cpu2.dcache.WriteReq_accesses::total 16025 # number of WriteReq accesses(hits+misses)
531 system.cpu2.dcache.SwapReq_accesses::cpu2.data 62 # number of SwapReq accesses(hits+misses)
532 system.cpu2.dcache.SwapReq_accesses::total 62 # number of SwapReq accesses(hits+misses)
533 system.cpu2.dcache.demand_accesses::cpu2.data 57869 # number of demand (read+write) accesses
534 system.cpu2.dcache.demand_accesses::total 57869 # number of demand (read+write) accesses
535 system.cpu2.dcache.overall_accesses::cpu2.data 57869 # number of overall (read+write) accesses
536 system.cpu2.dcache.overall_accesses::total 57869 # number of overall (read+write) accesses
537 system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003728 # miss rate for ReadReq accesses
538 system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.006802 # miss rate for WriteReq accesses
539 system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.822581 # miss rate for SwapReq accesses
540 system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004579 # miss rate for demand accesses
541 system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004579 # miss rate for overall accesses
542 system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 16198.717949 # average ReadReq miss latency
543 system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 19119.266055 # average WriteReq miss latency
544 system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 5980.392157 # average SwapReq miss latency
545 system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 17400 # average overall miss latency
546 system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 17400 # average overall miss latency
547 system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
548 system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
549 system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
550 system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked
551 system.cpu2.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
552 system.cpu2.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
553 system.cpu2.dcache.fast_writes 0 # number of fast writes performed
554 system.cpu2.dcache.cache_copies 0 # number of cache copies performed
555 system.cpu2.dcache.writebacks::writebacks 1 # number of writebacks
556 system.cpu2.dcache.writebacks::total 1 # number of writebacks
557 system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 156 # number of ReadReq MSHR misses
558 system.cpu2.dcache.ReadReq_mshr_misses::total 156 # number of ReadReq MSHR misses
559 system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 109 # number of WriteReq MSHR misses
560 system.cpu2.dcache.WriteReq_mshr_misses::total 109 # number of WriteReq MSHR misses
561 system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 51 # number of SwapReq MSHR misses
562 system.cpu2.dcache.SwapReq_mshr_misses::total 51 # number of SwapReq MSHR misses
563 system.cpu2.dcache.demand_mshr_misses::cpu2.data 265 # number of demand (read+write) MSHR misses
564 system.cpu2.dcache.demand_mshr_misses::total 265 # number of demand (read+write) MSHR misses
565 system.cpu2.dcache.overall_mshr_misses::cpu2.data 265 # number of overall MSHR misses
566 system.cpu2.dcache.overall_mshr_misses::total 265 # number of overall MSHR misses
567 system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 2059000 # number of ReadReq MSHR miss cycles
568 system.cpu2.dcache.ReadReq_mshr_miss_latency::total 2059000 # number of ReadReq MSHR miss cycles
569 system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1757000 # number of WriteReq MSHR miss cycles
570 system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1757000 # number of WriteReq MSHR miss cycles
571 system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 152000 # number of SwapReq MSHR miss cycles
572 system.cpu2.dcache.SwapReq_mshr_miss_latency::total 152000 # number of SwapReq MSHR miss cycles
573 system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3816000 # number of demand (read+write) MSHR miss cycles
574 system.cpu2.dcache.demand_mshr_miss_latency::total 3816000 # number of demand (read+write) MSHR miss cycles
575 system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3816000 # number of overall MSHR miss cycles
576 system.cpu2.dcache.overall_mshr_miss_latency::total 3816000 # number of overall MSHR miss cycles
577 system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003728 # mshr miss rate for ReadReq accesses
578 system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.006802 # mshr miss rate for WriteReq accesses
579 system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.822581 # mshr miss rate for SwapReq accesses
580 system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004579 # mshr miss rate for demand accesses
581 system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004579 # mshr miss rate for overall accesses
582 system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13198.717949 # average ReadReq mshr miss latency
583 system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 16119.266055 # average WriteReq mshr miss latency
584 system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 2980.392157 # average SwapReq mshr miss latency
585 system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 14400 # average overall mshr miss latency
586 system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 14400 # average overall mshr miss latency
587 system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
588 system.cpu3.numCycles 524596 # number of cpu cycles simulated
589 system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
590 system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed
591 system.cpu3.committedInsts 166130 # Number of instructions committed
592 system.cpu3.committedOps 166130 # Number of ops (including micro ops) committed
593 system.cpu3.num_int_alu_accesses 112098 # Number of integer alu accesses
594 system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses
595 system.cpu3.num_func_calls 637 # number of times a function call or return occured
596 system.cpu3.num_conditional_control_insts 31024 # number of instructions that are conditional controls
597 system.cpu3.num_int_insts 112098 # number of integer instructions
598 system.cpu3.num_fp_insts 0 # number of float instructions
599 system.cpu3.num_int_register_reads 286475 # number of times the integer registers were read
600 system.cpu3.num_int_register_writes 109360 # number of times the integer registers were written
601 system.cpu3.num_fp_register_reads 0 # number of times the floating registers were read
602 system.cpu3.num_fp_register_writes 0 # number of times the floating registers were written
603 system.cpu3.num_mem_refs 57243 # number of memory refs
604 system.cpu3.num_load_insts 41720 # Number of load instructions
605 system.cpu3.num_store_insts 15523 # Number of store instructions
606 system.cpu3.num_idle_cycles 69090.001737 # Number of idle cycles
607 system.cpu3.num_busy_cycles 455505.998263 # Number of busy cycles
608 system.cpu3.not_idle_fraction 0.868299 # Percentage of non-idle cycles
609 system.cpu3.idle_fraction 0.131701 # Percentage of idle cycles
610 system.cpu3.icache.replacements 281 # number of replacements
611 system.cpu3.icache.tagsinuse 67.737646 # Cycle average of tags in use
612 system.cpu3.icache.total_refs 165796 # Total number of references to valid blocks.
613 system.cpu3.icache.sampled_refs 367 # Sample count of references to valid blocks.
614 system.cpu3.icache.avg_refs 451.760218 # Average number of references to valid blocks.
615 system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
616 system.cpu3.icache.occ_blocks::cpu3.inst 67.737646 # Average occupied blocks per requestor
617 system.cpu3.icache.occ_percent::cpu3.inst 0.132300 # Average percentage of cache occupancy
618 system.cpu3.icache.occ_percent::total 0.132300 # Average percentage of cache occupancy
619 system.cpu3.icache.ReadReq_hits::cpu3.inst 165796 # number of ReadReq hits
620 system.cpu3.icache.ReadReq_hits::total 165796 # number of ReadReq hits
621 system.cpu3.icache.demand_hits::cpu3.inst 165796 # number of demand (read+write) hits
622 system.cpu3.icache.demand_hits::total 165796 # number of demand (read+write) hits
623 system.cpu3.icache.overall_hits::cpu3.inst 165796 # number of overall hits
624 system.cpu3.icache.overall_hits::total 165796 # number of overall hits
625 system.cpu3.icache.ReadReq_misses::cpu3.inst 367 # number of ReadReq misses
626 system.cpu3.icache.ReadReq_misses::total 367 # number of ReadReq misses
627 system.cpu3.icache.demand_misses::cpu3.inst 367 # number of demand (read+write) misses
628 system.cpu3.icache.demand_misses::total 367 # number of demand (read+write) misses
629 system.cpu3.icache.overall_misses::cpu3.inst 367 # number of overall misses
630 system.cpu3.icache.overall_misses::total 367 # number of overall misses
631 system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 5531500 # number of ReadReq miss cycles
632 system.cpu3.icache.ReadReq_miss_latency::total 5531500 # number of ReadReq miss cycles
633 system.cpu3.icache.demand_miss_latency::cpu3.inst 5531500 # number of demand (read+write) miss cycles
634 system.cpu3.icache.demand_miss_latency::total 5531500 # number of demand (read+write) miss cycles
635 system.cpu3.icache.overall_miss_latency::cpu3.inst 5531500 # number of overall miss cycles
636 system.cpu3.icache.overall_miss_latency::total 5531500 # number of overall miss cycles
637 system.cpu3.icache.ReadReq_accesses::cpu3.inst 166163 # number of ReadReq accesses(hits+misses)
638 system.cpu3.icache.ReadReq_accesses::total 166163 # number of ReadReq accesses(hits+misses)
639 system.cpu3.icache.demand_accesses::cpu3.inst 166163 # number of demand (read+write) accesses
640 system.cpu3.icache.demand_accesses::total 166163 # number of demand (read+write) accesses
641 system.cpu3.icache.overall_accesses::cpu3.inst 166163 # number of overall (read+write) accesses
642 system.cpu3.icache.overall_accesses::total 166163 # number of overall (read+write) accesses
643 system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002209 # miss rate for ReadReq accesses
644 system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002209 # miss rate for demand accesses
645 system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002209 # miss rate for overall accesses
646 system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 15072.207084 # average ReadReq miss latency
647 system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 15072.207084 # average overall miss latency
648 system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 15072.207084 # average overall miss latency
649 system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
650 system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
651 system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked
652 system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked
653 system.cpu3.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
654 system.cpu3.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
655 system.cpu3.icache.fast_writes 0 # number of fast writes performed
656 system.cpu3.icache.cache_copies 0 # number of cache copies performed
657 system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 367 # number of ReadReq MSHR misses
658 system.cpu3.icache.ReadReq_mshr_misses::total 367 # number of ReadReq MSHR misses
659 system.cpu3.icache.demand_mshr_misses::cpu3.inst 367 # number of demand (read+write) MSHR misses
660 system.cpu3.icache.demand_mshr_misses::total 367 # number of demand (read+write) MSHR misses
661 system.cpu3.icache.overall_mshr_misses::cpu3.inst 367 # number of overall MSHR misses
662 system.cpu3.icache.overall_mshr_misses::total 367 # number of overall MSHR misses
663 system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 4430500 # number of ReadReq MSHR miss cycles
664 system.cpu3.icache.ReadReq_mshr_miss_latency::total 4430500 # number of ReadReq MSHR miss cycles
665 system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 4430500 # number of demand (read+write) MSHR miss cycles
666 system.cpu3.icache.demand_mshr_miss_latency::total 4430500 # number of demand (read+write) MSHR miss cycles
667 system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 4430500 # number of overall MSHR miss cycles
668 system.cpu3.icache.overall_mshr_miss_latency::total 4430500 # number of overall MSHR miss cycles
669 system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.002209 # mshr miss rate for ReadReq accesses
670 system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.002209 # mshr miss rate for demand accesses
671 system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.002209 # mshr miss rate for overall accesses
672 system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12072.207084 # average ReadReq mshr miss latency
673 system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12072.207084 # average overall mshr miss latency
674 system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12072.207084 # average overall mshr miss latency
675 system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate
676 system.cpu3.dcache.replacements 2 # number of replacements
677 system.cpu3.dcache.tagsinuse 25.684916 # Cycle average of tags in use
678 system.cpu3.dcache.total_refs 33474 # Total number of references to valid blocks.
679 system.cpu3.dcache.sampled_refs 32 # Sample count of references to valid blocks.
680 system.cpu3.dcache.avg_refs 1046.062500 # Average number of references to valid blocks.
681 system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
682 system.cpu3.dcache.occ_blocks::cpu3.data 25.684916 # Average occupied blocks per requestor
683 system.cpu3.dcache.occ_percent::cpu3.data 0.050166 # Average percentage of cache occupancy
684 system.cpu3.dcache.occ_percent::total 0.050166 # Average percentage of cache occupancy
685 system.cpu3.dcache.ReadReq_hits::cpu3.data 41555 # number of ReadReq hits
686 system.cpu3.dcache.ReadReq_hits::total 41555 # number of ReadReq hits
687 system.cpu3.dcache.WriteReq_hits::cpu3.data 15348 # number of WriteReq hits
688 system.cpu3.dcache.WriteReq_hits::total 15348 # number of WriteReq hits
689 system.cpu3.dcache.SwapReq_hits::cpu3.data 11 # number of SwapReq hits
690 system.cpu3.dcache.SwapReq_hits::total 11 # number of SwapReq hits
691 system.cpu3.dcache.demand_hits::cpu3.data 56903 # number of demand (read+write) hits
692 system.cpu3.dcache.demand_hits::total 56903 # number of demand (read+write) hits
693 system.cpu3.dcache.overall_hits::cpu3.data 56903 # number of overall hits
694 system.cpu3.dcache.overall_hits::total 56903 # number of overall hits
695 system.cpu3.dcache.ReadReq_misses::cpu3.data 157 # number of ReadReq misses
696 system.cpu3.dcache.ReadReq_misses::total 157 # number of ReadReq misses
697 system.cpu3.dcache.WriteReq_misses::cpu3.data 108 # number of WriteReq misses
698 system.cpu3.dcache.WriteReq_misses::total 108 # number of WriteReq misses
699 system.cpu3.dcache.SwapReq_misses::cpu3.data 54 # number of SwapReq misses
700 system.cpu3.dcache.SwapReq_misses::total 54 # number of SwapReq misses
701 system.cpu3.dcache.demand_misses::cpu3.data 265 # number of demand (read+write) misses
702 system.cpu3.dcache.demand_misses::total 265 # number of demand (read+write) misses
703 system.cpu3.dcache.overall_misses::cpu3.data 265 # number of overall misses
704 system.cpu3.dcache.overall_misses::total 265 # number of overall misses
705 system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 2569000 # number of ReadReq miss cycles
706 system.cpu3.dcache.ReadReq_miss_latency::total 2569000 # number of ReadReq miss cycles
707 system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 2080000 # number of WriteReq miss cycles
708 system.cpu3.dcache.WriteReq_miss_latency::total 2080000 # number of WriteReq miss cycles
709 system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 326000 # number of SwapReq miss cycles
710 system.cpu3.dcache.SwapReq_miss_latency::total 326000 # number of SwapReq miss cycles
711 system.cpu3.dcache.demand_miss_latency::cpu3.data 4649000 # number of demand (read+write) miss cycles
712 system.cpu3.dcache.demand_miss_latency::total 4649000 # number of demand (read+write) miss cycles
713 system.cpu3.dcache.overall_miss_latency::cpu3.data 4649000 # number of overall miss cycles
714 system.cpu3.dcache.overall_miss_latency::total 4649000 # number of overall miss cycles
715 system.cpu3.dcache.ReadReq_accesses::cpu3.data 41712 # number of ReadReq accesses(hits+misses)
716 system.cpu3.dcache.ReadReq_accesses::total 41712 # number of ReadReq accesses(hits+misses)
717 system.cpu3.dcache.WriteReq_accesses::cpu3.data 15456 # number of WriteReq accesses(hits+misses)
718 system.cpu3.dcache.WriteReq_accesses::total 15456 # number of WriteReq accesses(hits+misses)
719 system.cpu3.dcache.SwapReq_accesses::cpu3.data 65 # number of SwapReq accesses(hits+misses)
720 system.cpu3.dcache.SwapReq_accesses::total 65 # number of SwapReq accesses(hits+misses)
721 system.cpu3.dcache.demand_accesses::cpu3.data 57168 # number of demand (read+write) accesses
722 system.cpu3.dcache.demand_accesses::total 57168 # number of demand (read+write) accesses
723 system.cpu3.dcache.overall_accesses::cpu3.data 57168 # number of overall (read+write) accesses
724 system.cpu3.dcache.overall_accesses::total 57168 # number of overall (read+write) accesses
725 system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.003764 # miss rate for ReadReq accesses
726 system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.006988 # miss rate for WriteReq accesses
727 system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.830769 # miss rate for SwapReq accesses
728 system.cpu3.dcache.demand_miss_rate::cpu3.data 0.004635 # miss rate for demand accesses
729 system.cpu3.dcache.overall_miss_rate::cpu3.data 0.004635 # miss rate for overall accesses
730 system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 16363.057325 # average ReadReq miss latency
731 system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 19259.259259 # average WriteReq miss latency
732 system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 6037.037037 # average SwapReq miss latency
733 system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 17543.396226 # average overall miss latency
734 system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 17543.396226 # average overall miss latency
735 system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
736 system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
737 system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
738 system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked
739 system.cpu3.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
740 system.cpu3.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
741 system.cpu3.dcache.fast_writes 0 # number of fast writes performed
742 system.cpu3.dcache.cache_copies 0 # number of cache copies performed
743 system.cpu3.dcache.writebacks::writebacks 1 # number of writebacks
744 system.cpu3.dcache.writebacks::total 1 # number of writebacks
745 system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 157 # number of ReadReq MSHR misses
746 system.cpu3.dcache.ReadReq_mshr_misses::total 157 # number of ReadReq MSHR misses
747 system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 108 # number of WriteReq MSHR misses
748 system.cpu3.dcache.WriteReq_mshr_misses::total 108 # number of WriteReq MSHR misses
749 system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 54 # number of SwapReq MSHR misses
750 system.cpu3.dcache.SwapReq_mshr_misses::total 54 # number of SwapReq MSHR misses
751 system.cpu3.dcache.demand_mshr_misses::cpu3.data 265 # number of demand (read+write) MSHR misses
752 system.cpu3.dcache.demand_mshr_misses::total 265 # number of demand (read+write) MSHR misses
753 system.cpu3.dcache.overall_mshr_misses::cpu3.data 265 # number of overall MSHR misses
754 system.cpu3.dcache.overall_mshr_misses::total 265 # number of overall MSHR misses
755 system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 2098000 # number of ReadReq MSHR miss cycles
756 system.cpu3.dcache.ReadReq_mshr_miss_latency::total 2098000 # number of ReadReq MSHR miss cycles
757 system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1756000 # number of WriteReq MSHR miss cycles
758 system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1756000 # number of WriteReq MSHR miss cycles
759 system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 164000 # number of SwapReq MSHR miss cycles
760 system.cpu3.dcache.SwapReq_mshr_miss_latency::total 164000 # number of SwapReq MSHR miss cycles
761 system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 3854000 # number of demand (read+write) MSHR miss cycles
762 system.cpu3.dcache.demand_mshr_miss_latency::total 3854000 # number of demand (read+write) MSHR miss cycles
763 system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 3854000 # number of overall MSHR miss cycles
764 system.cpu3.dcache.overall_mshr_miss_latency::total 3854000 # number of overall MSHR miss cycles
765 system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003764 # mshr miss rate for ReadReq accesses
766 system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.006988 # mshr miss rate for WriteReq accesses
767 system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.830769 # mshr miss rate for SwapReq accesses
768 system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.004635 # mshr miss rate for demand accesses
769 system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.004635 # mshr miss rate for overall accesses
770 system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 13363.057325 # average ReadReq mshr miss latency
771 system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 16259.259259 # average WriteReq mshr miss latency
772 system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 3037.037037 # average SwapReq mshr miss latency
773 system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 14543.396226 # average overall mshr miss latency
774 system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 14543.396226 # average overall mshr miss latency
775 system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
776 system.l2c.replacements 0 # number of replacements
777 system.l2c.tagsinuse 353.886259 # Cycle average of tags in use
778 system.l2c.total_refs 1223 # Total number of references to valid blocks.
779 system.l2c.sampled_refs 434 # Sample count of references to valid blocks.
780 system.l2c.avg_refs 2.817972 # Average number of references to valid blocks.
781 system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
782 system.l2c.occ_blocks::writebacks 5.597896 # Average occupied blocks per requestor
783 system.l2c.occ_blocks::cpu0.inst 231.859183 # Average occupied blocks per requestor
784 system.l2c.occ_blocks::cpu0.data 54.220360 # Average occupied blocks per requestor
785 system.l2c.occ_blocks::cpu1.inst 51.601293 # Average occupied blocks per requestor
786 system.l2c.occ_blocks::cpu1.data 6.129067 # Average occupied blocks per requestor
787 system.l2c.occ_blocks::cpu2.inst 1.914986 # Average occupied blocks per requestor
788 system.l2c.occ_blocks::cpu2.data 0.831600 # Average occupied blocks per requestor
789 system.l2c.occ_blocks::cpu3.inst 0.887228 # Average occupied blocks per requestor
790 system.l2c.occ_blocks::cpu3.data 0.844646 # Average occupied blocks per requestor
791 system.l2c.occ_percent::writebacks 0.000085 # Average percentage of cache occupancy
792 system.l2c.occ_percent::cpu0.inst 0.003538 # Average percentage of cache occupancy
793 system.l2c.occ_percent::cpu0.data 0.000827 # Average percentage of cache occupancy
794 system.l2c.occ_percent::cpu1.inst 0.000787 # Average percentage of cache occupancy
795 system.l2c.occ_percent::cpu1.data 0.000094 # Average percentage of cache occupancy
796 system.l2c.occ_percent::cpu2.inst 0.000029 # Average percentage of cache occupancy
797 system.l2c.occ_percent::cpu2.data 0.000013 # Average percentage of cache occupancy
798 system.l2c.occ_percent::cpu3.inst 0.000014 # Average percentage of cache occupancy
799 system.l2c.occ_percent::cpu3.data 0.000013 # Average percentage of cache occupancy
800 system.l2c.occ_percent::total 0.005400 # Average percentage of cache occupancy
801 system.l2c.ReadReq_hits::cpu0.inst 182 # number of ReadReq hits
802 system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits
803 system.l2c.ReadReq_hits::cpu1.inst 300 # number of ReadReq hits
804 system.l2c.ReadReq_hits::cpu1.data 5 # number of ReadReq hits
805 system.l2c.ReadReq_hits::cpu2.inst 354 # number of ReadReq hits
806 system.l2c.ReadReq_hits::cpu2.data 11 # number of ReadReq hits
807 system.l2c.ReadReq_hits::cpu3.inst 358 # number of ReadReq hits
808 system.l2c.ReadReq_hits::cpu3.data 11 # number of ReadReq hits
809 system.l2c.ReadReq_hits::total 1226 # number of ReadReq hits
810 system.l2c.Writeback_hits::writebacks 9 # number of Writeback hits
811 system.l2c.Writeback_hits::total 9 # number of Writeback hits
812 system.l2c.UpgradeReq_hits::cpu0.data 2 # number of UpgradeReq hits
813 system.l2c.UpgradeReq_hits::total 2 # number of UpgradeReq hits
814 system.l2c.demand_hits::cpu0.inst 182 # number of demand (read+write) hits
815 system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits
816 system.l2c.demand_hits::cpu1.inst 300 # number of demand (read+write) hits
817 system.l2c.demand_hits::cpu1.data 5 # number of demand (read+write) hits
818 system.l2c.demand_hits::cpu2.inst 354 # number of demand (read+write) hits
819 system.l2c.demand_hits::cpu2.data 11 # number of demand (read+write) hits
820 system.l2c.demand_hits::cpu3.inst 358 # number of demand (read+write) hits
821 system.l2c.demand_hits::cpu3.data 11 # number of demand (read+write) hits
822 system.l2c.demand_hits::total 1226 # number of demand (read+write) hits
823 system.l2c.overall_hits::cpu0.inst 182 # number of overall hits
824 system.l2c.overall_hits::cpu0.data 5 # number of overall hits
825 system.l2c.overall_hits::cpu1.inst 300 # number of overall hits
826 system.l2c.overall_hits::cpu1.data 5 # number of overall hits
827 system.l2c.overall_hits::cpu2.inst 354 # number of overall hits
828 system.l2c.overall_hits::cpu2.data 11 # number of overall hits
829 system.l2c.overall_hits::cpu3.inst 358 # number of overall hits
830 system.l2c.overall_hits::cpu3.data 11 # number of overall hits
831 system.l2c.overall_hits::total 1226 # number of overall hits
832 system.l2c.ReadReq_misses::cpu0.inst 285 # number of ReadReq misses
833 system.l2c.ReadReq_misses::cpu0.data 66 # number of ReadReq misses
834 system.l2c.ReadReq_misses::cpu1.inst 66 # number of ReadReq misses
835 system.l2c.ReadReq_misses::cpu1.data 8 # number of ReadReq misses
836 system.l2c.ReadReq_misses::cpu2.inst 12 # number of ReadReq misses
837 system.l2c.ReadReq_misses::cpu2.data 2 # number of ReadReq misses
838 system.l2c.ReadReq_misses::cpu3.inst 9 # number of ReadReq misses
839 system.l2c.ReadReq_misses::cpu3.data 2 # number of ReadReq misses
840 system.l2c.ReadReq_misses::total 450 # number of ReadReq misses
841 system.l2c.UpgradeReq_misses::cpu0.data 28 # number of UpgradeReq misses
842 system.l2c.UpgradeReq_misses::cpu1.data 12 # number of UpgradeReq misses
843 system.l2c.UpgradeReq_misses::cpu2.data 16 # number of UpgradeReq misses
844 system.l2c.UpgradeReq_misses::cpu3.data 16 # number of UpgradeReq misses
845 system.l2c.UpgradeReq_misses::total 72 # number of UpgradeReq misses
846 system.l2c.ReadExReq_misses::cpu0.data 99 # number of ReadExReq misses
847 system.l2c.ReadExReq_misses::cpu1.data 15 # number of ReadExReq misses
848 system.l2c.ReadExReq_misses::cpu2.data 14 # number of ReadExReq misses
849 system.l2c.ReadExReq_misses::cpu3.data 14 # number of ReadExReq misses
850 system.l2c.ReadExReq_misses::total 142 # number of ReadExReq misses
851 system.l2c.demand_misses::cpu0.inst 285 # number of demand (read+write) misses
852 system.l2c.demand_misses::cpu0.data 165 # number of demand (read+write) misses
853 system.l2c.demand_misses::cpu1.inst 66 # number of demand (read+write) misses
854 system.l2c.demand_misses::cpu1.data 23 # number of demand (read+write) misses
855 system.l2c.demand_misses::cpu2.inst 12 # number of demand (read+write) misses
856 system.l2c.demand_misses::cpu2.data 16 # number of demand (read+write) misses
857 system.l2c.demand_misses::cpu3.inst 9 # number of demand (read+write) misses
858 system.l2c.demand_misses::cpu3.data 16 # number of demand (read+write) misses
859 system.l2c.demand_misses::total 592 # number of demand (read+write) misses
860 system.l2c.overall_misses::cpu0.inst 285 # number of overall misses
861 system.l2c.overall_misses::cpu0.data 165 # number of overall misses
862 system.l2c.overall_misses::cpu1.inst 66 # number of overall misses
863 system.l2c.overall_misses::cpu1.data 23 # number of overall misses
864 system.l2c.overall_misses::cpu2.inst 12 # number of overall misses
865 system.l2c.overall_misses::cpu2.data 16 # number of overall misses
866 system.l2c.overall_misses::cpu3.inst 9 # number of overall misses
867 system.l2c.overall_misses::cpu3.data 16 # number of overall misses
868 system.l2c.overall_misses::total 592 # number of overall misses
869 system.l2c.ReadReq_miss_latency::cpu0.inst 14822000 # number of ReadReq miss cycles
870 system.l2c.ReadReq_miss_latency::cpu0.data 3432000 # number of ReadReq miss cycles
871 system.l2c.ReadReq_miss_latency::cpu1.inst 3416000 # number of ReadReq miss cycles
872 system.l2c.ReadReq_miss_latency::cpu1.data 413000 # number of ReadReq miss cycles
873 system.l2c.ReadReq_miss_latency::cpu2.inst 615000 # number of ReadReq miss cycles
874 system.l2c.ReadReq_miss_latency::cpu2.data 104000 # number of ReadReq miss cycles
875 system.l2c.ReadReq_miss_latency::cpu3.inst 429000 # number of ReadReq miss cycles
876 system.l2c.ReadReq_miss_latency::cpu3.data 99000 # number of ReadReq miss cycles
877 system.l2c.ReadReq_miss_latency::total 23330000 # number of ReadReq miss cycles
878 system.l2c.UpgradeReq_miss_latency::cpu1.data 52000 # number of UpgradeReq miss cycles
879 system.l2c.UpgradeReq_miss_latency::cpu2.data 52000 # number of UpgradeReq miss cycles
880 system.l2c.UpgradeReq_miss_latency::cpu3.data 52000 # number of UpgradeReq miss cycles
881 system.l2c.UpgradeReq_miss_latency::total 156000 # number of UpgradeReq miss cycles
882 system.l2c.ReadExReq_miss_latency::cpu0.data 5148000 # number of ReadExReq miss cycles
883 system.l2c.ReadExReq_miss_latency::cpu1.data 781000 # number of ReadExReq miss cycles
884 system.l2c.ReadExReq_miss_latency::cpu2.data 728000 # number of ReadExReq miss cycles
885 system.l2c.ReadExReq_miss_latency::cpu3.data 728000 # number of ReadExReq miss cycles
886 system.l2c.ReadExReq_miss_latency::total 7385000 # number of ReadExReq miss cycles
887 system.l2c.demand_miss_latency::cpu0.inst 14822000 # number of demand (read+write) miss cycles
888 system.l2c.demand_miss_latency::cpu0.data 8580000 # number of demand (read+write) miss cycles
889 system.l2c.demand_miss_latency::cpu1.inst 3416000 # number of demand (read+write) miss cycles
890 system.l2c.demand_miss_latency::cpu1.data 1194000 # number of demand (read+write) miss cycles
891 system.l2c.demand_miss_latency::cpu2.inst 615000 # number of demand (read+write) miss cycles
892 system.l2c.demand_miss_latency::cpu2.data 832000 # number of demand (read+write) miss cycles
893 system.l2c.demand_miss_latency::cpu3.inst 429000 # number of demand (read+write) miss cycles
894 system.l2c.demand_miss_latency::cpu3.data 827000 # number of demand (read+write) miss cycles
895 system.l2c.demand_miss_latency::total 30715000 # number of demand (read+write) miss cycles
896 system.l2c.overall_miss_latency::cpu0.inst 14822000 # number of overall miss cycles
897 system.l2c.overall_miss_latency::cpu0.data 8580000 # number of overall miss cycles
898 system.l2c.overall_miss_latency::cpu1.inst 3416000 # number of overall miss cycles
899 system.l2c.overall_miss_latency::cpu1.data 1194000 # number of overall miss cycles
900 system.l2c.overall_miss_latency::cpu2.inst 615000 # number of overall miss cycles
901 system.l2c.overall_miss_latency::cpu2.data 832000 # number of overall miss cycles
902 system.l2c.overall_miss_latency::cpu3.inst 429000 # number of overall miss cycles
903 system.l2c.overall_miss_latency::cpu3.data 827000 # number of overall miss cycles
904 system.l2c.overall_miss_latency::total 30715000 # number of overall miss cycles
905 system.l2c.ReadReq_accesses::cpu0.inst 467 # number of ReadReq accesses(hits+misses)
906 system.l2c.ReadReq_accesses::cpu0.data 71 # number of ReadReq accesses(hits+misses)
907 system.l2c.ReadReq_accesses::cpu1.inst 366 # number of ReadReq accesses(hits+misses)
908 system.l2c.ReadReq_accesses::cpu1.data 13 # number of ReadReq accesses(hits+misses)
909 system.l2c.ReadReq_accesses::cpu2.inst 366 # number of ReadReq accesses(hits+misses)
910 system.l2c.ReadReq_accesses::cpu2.data 13 # number of ReadReq accesses(hits+misses)
911 system.l2c.ReadReq_accesses::cpu3.inst 367 # number of ReadReq accesses(hits+misses)
912 system.l2c.ReadReq_accesses::cpu3.data 13 # number of ReadReq accesses(hits+misses)
913 system.l2c.ReadReq_accesses::total 1676 # number of ReadReq accesses(hits+misses)
914 system.l2c.Writeback_accesses::writebacks 9 # number of Writeback accesses(hits+misses)
915 system.l2c.Writeback_accesses::total 9 # number of Writeback accesses(hits+misses)
916 system.l2c.UpgradeReq_accesses::cpu0.data 30 # number of UpgradeReq accesses(hits+misses)
917 system.l2c.UpgradeReq_accesses::cpu1.data 12 # number of UpgradeReq accesses(hits+misses)
918 system.l2c.UpgradeReq_accesses::cpu2.data 16 # number of UpgradeReq accesses(hits+misses)
919 system.l2c.UpgradeReq_accesses::cpu3.data 16 # number of UpgradeReq accesses(hits+misses)
920 system.l2c.UpgradeReq_accesses::total 74 # number of UpgradeReq accesses(hits+misses)
921 system.l2c.ReadExReq_accesses::cpu0.data 99 # number of ReadExReq accesses(hits+misses)
922 system.l2c.ReadExReq_accesses::cpu1.data 15 # number of ReadExReq accesses(hits+misses)
923 system.l2c.ReadExReq_accesses::cpu2.data 14 # number of ReadExReq accesses(hits+misses)
924 system.l2c.ReadExReq_accesses::cpu3.data 14 # number of ReadExReq accesses(hits+misses)
925 system.l2c.ReadExReq_accesses::total 142 # number of ReadExReq accesses(hits+misses)
926 system.l2c.demand_accesses::cpu0.inst 467 # number of demand (read+write) accesses
927 system.l2c.demand_accesses::cpu0.data 170 # number of demand (read+write) accesses
928 system.l2c.demand_accesses::cpu1.inst 366 # number of demand (read+write) accesses
929 system.l2c.demand_accesses::cpu1.data 28 # number of demand (read+write) accesses
930 system.l2c.demand_accesses::cpu2.inst 366 # number of demand (read+write) accesses
931 system.l2c.demand_accesses::cpu2.data 27 # number of demand (read+write) accesses
932 system.l2c.demand_accesses::cpu3.inst 367 # number of demand (read+write) accesses
933 system.l2c.demand_accesses::cpu3.data 27 # number of demand (read+write) accesses
934 system.l2c.demand_accesses::total 1818 # number of demand (read+write) accesses
935 system.l2c.overall_accesses::cpu0.inst 467 # number of overall (read+write) accesses
936 system.l2c.overall_accesses::cpu0.data 170 # number of overall (read+write) accesses
937 system.l2c.overall_accesses::cpu1.inst 366 # number of overall (read+write) accesses
938 system.l2c.overall_accesses::cpu1.data 28 # number of overall (read+write) accesses
939 system.l2c.overall_accesses::cpu2.inst 366 # number of overall (read+write) accesses
940 system.l2c.overall_accesses::cpu2.data 27 # number of overall (read+write) accesses
941 system.l2c.overall_accesses::cpu3.inst 367 # number of overall (read+write) accesses
942 system.l2c.overall_accesses::cpu3.data 27 # number of overall (read+write) accesses
943 system.l2c.overall_accesses::total 1818 # number of overall (read+write) accesses
944 system.l2c.ReadReq_miss_rate::cpu0.inst 0.610278 # miss rate for ReadReq accesses
945 system.l2c.ReadReq_miss_rate::cpu0.data 0.929577 # miss rate for ReadReq accesses
946 system.l2c.ReadReq_miss_rate::cpu1.inst 0.180328 # miss rate for ReadReq accesses
947 system.l2c.ReadReq_miss_rate::cpu1.data 0.615385 # miss rate for ReadReq accesses
948 system.l2c.ReadReq_miss_rate::cpu2.inst 0.032787 # miss rate for ReadReq accesses
949 system.l2c.ReadReq_miss_rate::cpu2.data 0.153846 # miss rate for ReadReq accesses
950 system.l2c.ReadReq_miss_rate::cpu3.inst 0.024523 # miss rate for ReadReq accesses
951 system.l2c.ReadReq_miss_rate::cpu3.data 0.153846 # miss rate for ReadReq accesses
952 system.l2c.UpgradeReq_miss_rate::cpu0.data 0.933333 # miss rate for UpgradeReq accesses
953 system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses
954 system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses
955 system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses
956 system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses
957 system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses
958 system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses
959 system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses
960 system.l2c.demand_miss_rate::cpu0.inst 0.610278 # miss rate for demand accesses
961 system.l2c.demand_miss_rate::cpu0.data 0.970588 # miss rate for demand accesses
962 system.l2c.demand_miss_rate::cpu1.inst 0.180328 # miss rate for demand accesses
963 system.l2c.demand_miss_rate::cpu1.data 0.821429 # miss rate for demand accesses
964 system.l2c.demand_miss_rate::cpu2.inst 0.032787 # miss rate for demand accesses
965 system.l2c.demand_miss_rate::cpu2.data 0.592593 # miss rate for demand accesses
966 system.l2c.demand_miss_rate::cpu3.inst 0.024523 # miss rate for demand accesses
967 system.l2c.demand_miss_rate::cpu3.data 0.592593 # miss rate for demand accesses
968 system.l2c.overall_miss_rate::cpu0.inst 0.610278 # miss rate for overall accesses
969 system.l2c.overall_miss_rate::cpu0.data 0.970588 # miss rate for overall accesses
970 system.l2c.overall_miss_rate::cpu1.inst 0.180328 # miss rate for overall accesses
971 system.l2c.overall_miss_rate::cpu1.data 0.821429 # miss rate for overall accesses
972 system.l2c.overall_miss_rate::cpu2.inst 0.032787 # miss rate for overall accesses
973 system.l2c.overall_miss_rate::cpu2.data 0.592593 # miss rate for overall accesses
974 system.l2c.overall_miss_rate::cpu3.inst 0.024523 # miss rate for overall accesses
975 system.l2c.overall_miss_rate::cpu3.data 0.592593 # miss rate for overall accesses
976 system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52007.017544 # average ReadReq miss latency
977 system.l2c.ReadReq_avg_miss_latency::cpu0.data 52000 # average ReadReq miss latency
978 system.l2c.ReadReq_avg_miss_latency::cpu1.inst 51757.575758 # average ReadReq miss latency
979 system.l2c.ReadReq_avg_miss_latency::cpu1.data 51625 # average ReadReq miss latency
980 system.l2c.ReadReq_avg_miss_latency::cpu2.inst 51250 # average ReadReq miss latency
981 system.l2c.ReadReq_avg_miss_latency::cpu2.data 52000 # average ReadReq miss latency
982 system.l2c.ReadReq_avg_miss_latency::cpu3.inst 47666.666667 # average ReadReq miss latency
983 system.l2c.ReadReq_avg_miss_latency::cpu3.data 49500 # average ReadReq miss latency
984 system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 4333.333333 # average UpgradeReq miss latency
985 system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 3250 # average UpgradeReq miss latency
986 system.l2c.UpgradeReq_avg_miss_latency::cpu3.data 3250 # average UpgradeReq miss latency
987 system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52000 # average ReadExReq miss latency
988 system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52066.666667 # average ReadExReq miss latency
989 system.l2c.ReadExReq_avg_miss_latency::cpu2.data 52000 # average ReadExReq miss latency
990 system.l2c.ReadExReq_avg_miss_latency::cpu3.data 52000 # average ReadExReq miss latency
991 system.l2c.demand_avg_miss_latency::cpu0.inst 52007.017544 # average overall miss latency
992 system.l2c.demand_avg_miss_latency::cpu0.data 52000 # average overall miss latency
993 system.l2c.demand_avg_miss_latency::cpu1.inst 51757.575758 # average overall miss latency
994 system.l2c.demand_avg_miss_latency::cpu1.data 51913.043478 # average overall miss latency
995 system.l2c.demand_avg_miss_latency::cpu2.inst 51250 # average overall miss latency
996 system.l2c.demand_avg_miss_latency::cpu2.data 52000 # average overall miss latency
997 system.l2c.demand_avg_miss_latency::cpu3.inst 47666.666667 # average overall miss latency
998 system.l2c.demand_avg_miss_latency::cpu3.data 51687.500000 # average overall miss latency
999 system.l2c.overall_avg_miss_latency::cpu0.inst 52007.017544 # average overall miss latency
1000 system.l2c.overall_avg_miss_latency::cpu0.data 52000 # average overall miss latency
1001 system.l2c.overall_avg_miss_latency::cpu1.inst 51757.575758 # average overall miss latency
1002 system.l2c.overall_avg_miss_latency::cpu1.data 51913.043478 # average overall miss latency
1003 system.l2c.overall_avg_miss_latency::cpu2.inst 51250 # average overall miss latency
1004 system.l2c.overall_avg_miss_latency::cpu2.data 52000 # average overall miss latency
1005 system.l2c.overall_avg_miss_latency::cpu3.inst 47666.666667 # average overall miss latency
1006 system.l2c.overall_avg_miss_latency::cpu3.data 51687.500000 # average overall miss latency
1007 system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1008 system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
1009 system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
1010 system.l2c.blocked::no_targets 0 # number of cycles access was blocked
1011 system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
1012 system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
1013 system.l2c.fast_writes 0 # number of fast writes performed
1014 system.l2c.cache_copies 0 # number of cache copies performed
1015 system.l2c.ReadReq_mshr_hits::cpu1.inst 7 # number of ReadReq MSHR hits
1016 system.l2c.ReadReq_mshr_hits::cpu1.data 1 # number of ReadReq MSHR hits
1017 system.l2c.ReadReq_mshr_hits::cpu2.inst 3 # number of ReadReq MSHR hits
1018 system.l2c.ReadReq_mshr_hits::cpu3.inst 8 # number of ReadReq MSHR hits
1019 system.l2c.ReadReq_mshr_hits::cpu3.data 1 # number of ReadReq MSHR hits
1020 system.l2c.ReadReq_mshr_hits::total 20 # number of ReadReq MSHR hits
1021 system.l2c.demand_mshr_hits::cpu1.inst 7 # number of demand (read+write) MSHR hits
1022 system.l2c.demand_mshr_hits::cpu1.data 1 # number of demand (read+write) MSHR hits
1023 system.l2c.demand_mshr_hits::cpu2.inst 3 # number of demand (read+write) MSHR hits
1024 system.l2c.demand_mshr_hits::cpu3.inst 8 # number of demand (read+write) MSHR hits
1025 system.l2c.demand_mshr_hits::cpu3.data 1 # number of demand (read+write) MSHR hits
1026 system.l2c.demand_mshr_hits::total 20 # number of demand (read+write) MSHR hits
1027 system.l2c.overall_mshr_hits::cpu1.inst 7 # number of overall MSHR hits
1028 system.l2c.overall_mshr_hits::cpu1.data 1 # number of overall MSHR hits
1029 system.l2c.overall_mshr_hits::cpu2.inst 3 # number of overall MSHR hits
1030 system.l2c.overall_mshr_hits::cpu3.inst 8 # number of overall MSHR hits
1031 system.l2c.overall_mshr_hits::cpu3.data 1 # number of overall MSHR hits
1032 system.l2c.overall_mshr_hits::total 20 # number of overall MSHR hits
1033 system.l2c.ReadReq_mshr_misses::cpu0.inst 285 # number of ReadReq MSHR misses
1034 system.l2c.ReadReq_mshr_misses::cpu0.data 66 # number of ReadReq MSHR misses
1035 system.l2c.ReadReq_mshr_misses::cpu1.inst 59 # number of ReadReq MSHR misses
1036 system.l2c.ReadReq_mshr_misses::cpu1.data 7 # number of ReadReq MSHR misses
1037 system.l2c.ReadReq_mshr_misses::cpu2.inst 9 # number of ReadReq MSHR misses
1038 system.l2c.ReadReq_mshr_misses::cpu2.data 2 # number of ReadReq MSHR misses
1039 system.l2c.ReadReq_mshr_misses::cpu3.inst 1 # number of ReadReq MSHR misses
1040 system.l2c.ReadReq_mshr_misses::cpu3.data 1 # number of ReadReq MSHR misses
1041 system.l2c.ReadReq_mshr_misses::total 430 # number of ReadReq MSHR misses
1042 system.l2c.UpgradeReq_mshr_misses::cpu0.data 28 # number of UpgradeReq MSHR misses
1043 system.l2c.UpgradeReq_mshr_misses::cpu1.data 12 # number of UpgradeReq MSHR misses
1044 system.l2c.UpgradeReq_mshr_misses::cpu2.data 16 # number of UpgradeReq MSHR misses
1045 system.l2c.UpgradeReq_mshr_misses::cpu3.data 16 # number of UpgradeReq MSHR misses
1046 system.l2c.UpgradeReq_mshr_misses::total 72 # number of UpgradeReq MSHR misses
1047 system.l2c.ReadExReq_mshr_misses::cpu0.data 99 # number of ReadExReq MSHR misses
1048 system.l2c.ReadExReq_mshr_misses::cpu1.data 15 # number of ReadExReq MSHR misses
1049 system.l2c.ReadExReq_mshr_misses::cpu2.data 14 # number of ReadExReq MSHR misses
1050 system.l2c.ReadExReq_mshr_misses::cpu3.data 14 # number of ReadExReq MSHR misses
1051 system.l2c.ReadExReq_mshr_misses::total 142 # number of ReadExReq MSHR misses
1052 system.l2c.demand_mshr_misses::cpu0.inst 285 # number of demand (read+write) MSHR misses
1053 system.l2c.demand_mshr_misses::cpu0.data 165 # number of demand (read+write) MSHR misses
1054 system.l2c.demand_mshr_misses::cpu1.inst 59 # number of demand (read+write) MSHR misses
1055 system.l2c.demand_mshr_misses::cpu1.data 22 # number of demand (read+write) MSHR misses
1056 system.l2c.demand_mshr_misses::cpu2.inst 9 # number of demand (read+write) MSHR misses
1057 system.l2c.demand_mshr_misses::cpu2.data 16 # number of demand (read+write) MSHR misses
1058 system.l2c.demand_mshr_misses::cpu3.inst 1 # number of demand (read+write) MSHR misses
1059 system.l2c.demand_mshr_misses::cpu3.data 15 # number of demand (read+write) MSHR misses
1060 system.l2c.demand_mshr_misses::total 572 # number of demand (read+write) MSHR misses
1061 system.l2c.overall_mshr_misses::cpu0.inst 285 # number of overall MSHR misses
1062 system.l2c.overall_mshr_misses::cpu0.data 165 # number of overall MSHR misses
1063 system.l2c.overall_mshr_misses::cpu1.inst 59 # number of overall MSHR misses
1064 system.l2c.overall_mshr_misses::cpu1.data 22 # number of overall MSHR misses
1065 system.l2c.overall_mshr_misses::cpu2.inst 9 # number of overall MSHR misses
1066 system.l2c.overall_mshr_misses::cpu2.data 16 # number of overall MSHR misses
1067 system.l2c.overall_mshr_misses::cpu3.inst 1 # number of overall MSHR misses
1068 system.l2c.overall_mshr_misses::cpu3.data 15 # number of overall MSHR misses
1069 system.l2c.overall_mshr_misses::total 572 # number of overall MSHR misses
1070 system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 11402000 # number of ReadReq MSHR miss cycles
1071 system.l2c.ReadReq_mshr_miss_latency::cpu0.data 2640000 # number of ReadReq MSHR miss cycles
1072 system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 2360000 # number of ReadReq MSHR miss cycles
1073 system.l2c.ReadReq_mshr_miss_latency::cpu1.data 280000 # number of ReadReq MSHR miss cycles
1074 system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 361000 # number of ReadReq MSHR miss cycles
1075 system.l2c.ReadReq_mshr_miss_latency::cpu2.data 80000 # number of ReadReq MSHR miss cycles
1076 system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 40000 # number of ReadReq MSHR miss cycles
1077 system.l2c.ReadReq_mshr_miss_latency::cpu3.data 40000 # number of ReadReq MSHR miss cycles
1078 system.l2c.ReadReq_mshr_miss_latency::total 17203000 # number of ReadReq MSHR miss cycles
1079 system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 1120000 # number of UpgradeReq MSHR miss cycles
1080 system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 480000 # number of UpgradeReq MSHR miss cycles
1081 system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 640000 # number of UpgradeReq MSHR miss cycles
1082 system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 640000 # number of UpgradeReq MSHR miss cycles
1083 system.l2c.UpgradeReq_mshr_miss_latency::total 2880000 # number of UpgradeReq MSHR miss cycles
1084 system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3960000 # number of ReadExReq MSHR miss cycles
1085 system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 601000 # number of ReadExReq MSHR miss cycles
1086 system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 560000 # number of ReadExReq MSHR miss cycles
1087 system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 560000 # number of ReadExReq MSHR miss cycles
1088 system.l2c.ReadExReq_mshr_miss_latency::total 5681000 # number of ReadExReq MSHR miss cycles
1089 system.l2c.demand_mshr_miss_latency::cpu0.inst 11402000 # number of demand (read+write) MSHR miss cycles
1090 system.l2c.demand_mshr_miss_latency::cpu0.data 6600000 # number of demand (read+write) MSHR miss cycles
1091 system.l2c.demand_mshr_miss_latency::cpu1.inst 2360000 # number of demand (read+write) MSHR miss cycles
1092 system.l2c.demand_mshr_miss_latency::cpu1.data 881000 # number of demand (read+write) MSHR miss cycles
1093 system.l2c.demand_mshr_miss_latency::cpu2.inst 361000 # number of demand (read+write) MSHR miss cycles
1094 system.l2c.demand_mshr_miss_latency::cpu2.data 640000 # number of demand (read+write) MSHR miss cycles
1095 system.l2c.demand_mshr_miss_latency::cpu3.inst 40000 # number of demand (read+write) MSHR miss cycles
1096 system.l2c.demand_mshr_miss_latency::cpu3.data 600000 # number of demand (read+write) MSHR miss cycles
1097 system.l2c.demand_mshr_miss_latency::total 22884000 # number of demand (read+write) MSHR miss cycles
1098 system.l2c.overall_mshr_miss_latency::cpu0.inst 11402000 # number of overall MSHR miss cycles
1099 system.l2c.overall_mshr_miss_latency::cpu0.data 6600000 # number of overall MSHR miss cycles
1100 system.l2c.overall_mshr_miss_latency::cpu1.inst 2360000 # number of overall MSHR miss cycles
1101 system.l2c.overall_mshr_miss_latency::cpu1.data 881000 # number of overall MSHR miss cycles
1102 system.l2c.overall_mshr_miss_latency::cpu2.inst 361000 # number of overall MSHR miss cycles
1103 system.l2c.overall_mshr_miss_latency::cpu2.data 640000 # number of overall MSHR miss cycles
1104 system.l2c.overall_mshr_miss_latency::cpu3.inst 40000 # number of overall MSHR miss cycles
1105 system.l2c.overall_mshr_miss_latency::cpu3.data 600000 # number of overall MSHR miss cycles
1106 system.l2c.overall_mshr_miss_latency::total 22884000 # number of overall MSHR miss cycles
1107 system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for ReadReq accesses
1108 system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.929577 # mshr miss rate for ReadReq accesses
1109 system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.161202 # mshr miss rate for ReadReq accesses
1110 system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.538462 # mshr miss rate for ReadReq accesses
1111 system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.024590 # mshr miss rate for ReadReq accesses
1112 system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.153846 # mshr miss rate for ReadReq accesses
1113 system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.002725 # mshr miss rate for ReadReq accesses
1114 system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.076923 # mshr miss rate for ReadReq accesses
1115 system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.933333 # mshr miss rate for UpgradeReq accesses
1116 system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses
1117 system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses
1118 system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses
1119 system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses
1120 system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses
1121 system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses
1122 system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses
1123 system.l2c.demand_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for demand accesses
1124 system.l2c.demand_mshr_miss_rate::cpu0.data 0.970588 # mshr miss rate for demand accesses
1125 system.l2c.demand_mshr_miss_rate::cpu1.inst 0.161202 # mshr miss rate for demand accesses
1126 system.l2c.demand_mshr_miss_rate::cpu1.data 0.785714 # mshr miss rate for demand accesses
1127 system.l2c.demand_mshr_miss_rate::cpu2.inst 0.024590 # mshr miss rate for demand accesses
1128 system.l2c.demand_mshr_miss_rate::cpu2.data 0.592593 # mshr miss rate for demand accesses
1129 system.l2c.demand_mshr_miss_rate::cpu3.inst 0.002725 # mshr miss rate for demand accesses
1130 system.l2c.demand_mshr_miss_rate::cpu3.data 0.555556 # mshr miss rate for demand accesses
1131 system.l2c.overall_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for overall accesses
1132 system.l2c.overall_mshr_miss_rate::cpu0.data 0.970588 # mshr miss rate for overall accesses
1133 system.l2c.overall_mshr_miss_rate::cpu1.inst 0.161202 # mshr miss rate for overall accesses
1134 system.l2c.overall_mshr_miss_rate::cpu1.data 0.785714 # mshr miss rate for overall accesses
1135 system.l2c.overall_mshr_miss_rate::cpu2.inst 0.024590 # mshr miss rate for overall accesses
1136 system.l2c.overall_mshr_miss_rate::cpu2.data 0.592593 # mshr miss rate for overall accesses
1137 system.l2c.overall_mshr_miss_rate::cpu3.inst 0.002725 # mshr miss rate for overall accesses
1138 system.l2c.overall_mshr_miss_rate::cpu3.data 0.555556 # mshr miss rate for overall accesses
1139 system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40007.017544 # average ReadReq mshr miss latency
1140 system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40000 # average ReadReq mshr miss latency
1141 system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40000 # average ReadReq mshr miss latency
1142 system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40000 # average ReadReq mshr miss latency
1143 system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 40111.111111 # average ReadReq mshr miss latency
1144 system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 40000 # average ReadReq mshr miss latency
1145 system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 40000 # average ReadReq mshr miss latency
1146 system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 40000 # average ReadReq mshr miss latency
1147 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40000 # average UpgradeReq mshr miss latency
1148 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40000 # average UpgradeReq mshr miss latency
1149 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 40000 # average UpgradeReq mshr miss latency
1150 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 40000 # average UpgradeReq mshr miss latency
1151 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40000 # average ReadExReq mshr miss latency
1152 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40066.666667 # average ReadExReq mshr miss latency
1153 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 40000 # average ReadExReq mshr miss latency
1154 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 40000 # average ReadExReq mshr miss latency
1155 system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40007.017544 # average overall mshr miss latency
1156 system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40000 # average overall mshr miss latency
1157 system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40000 # average overall mshr miss latency
1158 system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40045.454545 # average overall mshr miss latency
1159 system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40111.111111 # average overall mshr miss latency
1160 system.l2c.demand_avg_mshr_miss_latency::cpu2.data 40000 # average overall mshr miss latency
1161 system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency
1162 system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40000 # average overall mshr miss latency
1163 system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40007.017544 # average overall mshr miss latency
1164 system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40000 # average overall mshr miss latency
1165 system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40000 # average overall mshr miss latency
1166 system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40045.454545 # average overall mshr miss latency
1167 system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40111.111111 # average overall mshr miss latency
1168 system.l2c.overall_avg_mshr_miss_latency::cpu2.data 40000 # average overall mshr miss latency
1169 system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency
1170 system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40000 # average overall mshr miss latency
1171 system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
1173 ---------- End Simulation Statistics ----------
projects / gem5.git / blob