tests: Migrated 40.m5threads-test-atomic scons tests to testlib
[gem5.git] / tests / quick / se / 40.m5threads-test-atomic / ref / sparc / linux / simple-timing-mp-ruby / config.ini
1 [root]
2 type=Root
3 children=system
4 dummy=0
5
6 [system]
7 type=System
8 children=cpu0 cpu1 cpu2 cpu3 membus physmem
9 mem_mode=timing
10 physmem=system.physmem
11
12 [system.cpu0]
13 type=TimingSimpleCPU
14 children=dtb itb tracer workload
15 checker=Null
16 clock=500
17 cpu_id=0
18 defer_registration=false
19 do_checkpoint_insts=true
20 do_statistics_insts=true
21 dtb=system.cpu0.dtb
22 function_trace=false
23 function_trace_start=0
24 itb=system.cpu0.itb
25 max_insts_all_threads=0
26 max_insts_any_thread=0
27 max_loads_all_threads=0
28 max_loads_any_thread=0
29 numThreads=1
30 phase=0
31 progress_interval=0
32 system=system
33 tracer=system.cpu0.tracer
34 workload=system.cpu0.workload
35 dcache_port=system.membus.port[1]
36 icache_port=system.membus.port[0]
37
38 [system.cpu0.dtb]
39 type=SparcTLB
40 size=64
41
42 [system.cpu0.itb]
43 type=SparcTLB
44 size=64
45
46 [system.cpu0.tracer]
47 type=ExeTracer
48
49 [system.cpu0.workload]
50 type=LiveProcess
51 cmd=test_atomic 4
52 cwd=
53 egid=100
54 env=
55 errout=cerr
56 euid=100
57 executable=/dist/m5/regression/test-progs/m5threads/bin/sparc/linux/test_atomic
58 gid=100
59 input=cin
60 max_stack_size=67108864
61 output=cout
62 pid=100
63 ppid=99
64 simpoint=0
65 system=system
66 uid=100
67
68 [system.cpu1]
69 type=TimingSimpleCPU
70 children=dtb itb tracer
71 checker=Null
72 clock=500
73 cpu_id=1
74 defer_registration=false
75 do_checkpoint_insts=true
76 do_statistics_insts=true
77 dtb=system.cpu1.dtb
78 function_trace=false
79 function_trace_start=0
80 itb=system.cpu1.itb
81 max_insts_all_threads=0
82 max_insts_any_thread=0
83 max_loads_all_threads=0
84 max_loads_any_thread=0
85 numThreads=1
86 phase=0
87 progress_interval=0
88 system=system
89 tracer=system.cpu1.tracer
90 workload=system.cpu0.workload
91 dcache_port=system.membus.port[3]
92 icache_port=system.membus.port[2]
93
94 [system.cpu1.dtb]
95 type=SparcTLB
96 size=64
97
98 [system.cpu1.itb]
99 type=SparcTLB
100 size=64
101
102 [system.cpu1.tracer]
103 type=ExeTracer
104
105 [system.cpu2]
106 type=TimingSimpleCPU
107 children=dtb itb tracer
108 checker=Null
109 clock=500
110 cpu_id=2
111 defer_registration=false
112 do_checkpoint_insts=true
113 do_statistics_insts=true
114 dtb=system.cpu2.dtb
115 function_trace=false
116 function_trace_start=0
117 itb=system.cpu2.itb
118 max_insts_all_threads=0
119 max_insts_any_thread=0
120 max_loads_all_threads=0
121 max_loads_any_thread=0
122 numThreads=1
123 phase=0
124 progress_interval=0
125 system=system
126 tracer=system.cpu2.tracer
127 workload=system.cpu0.workload
128 dcache_port=system.membus.port[5]
129 icache_port=system.membus.port[4]
130
131 [system.cpu2.dtb]
132 type=SparcTLB
133 size=64
134
135 [system.cpu2.itb]
136 type=SparcTLB
137 size=64
138
139 [system.cpu2.tracer]
140 type=ExeTracer
141
142 [system.cpu3]
143 type=TimingSimpleCPU
144 children=dtb itb tracer
145 checker=Null
146 clock=500
147 cpu_id=3
148 defer_registration=false
149 do_checkpoint_insts=true
150 do_statistics_insts=true
151 dtb=system.cpu3.dtb
152 function_trace=false
153 function_trace_start=0
154 itb=system.cpu3.itb
155 max_insts_all_threads=0
156 max_insts_any_thread=0
157 max_loads_all_threads=0
158 max_loads_any_thread=0
159 numThreads=1
160 phase=0
161 progress_interval=0
162 system=system
163 tracer=system.cpu3.tracer
164 workload=system.cpu0.workload
165 dcache_port=system.membus.port[7]
166 icache_port=system.membus.port[6]
167
168 [system.cpu3.dtb]
169 type=SparcTLB
170 size=64
171
172 [system.cpu3.itb]
173 type=SparcTLB
174 size=64
175
176 [system.cpu3.tracer]
177 type=ExeTracer
178
179 [system.membus]
180 type=Bus
181 block_size=64
182 bus_id=0
183 clock=1000
184 header_cycles=1
185 use_default_range=false
186 width=64
187 port=system.cpu0.icache_port system.cpu0.dcache_port system.cpu1.icache_port system.cpu1.dcache_port system.cpu2.icache_port system.cpu2.dcache_port system.cpu3.icache_port system.cpu3.dcache_port system.physmem.port[0]
188
189 [system.physmem]
190 type=RubyMemory
191 clock=1
192 config_file=
193 config_options=
194 debug=false
195 debug_file=
196 file=
197 latency=30000
198 latency_var=0
199 null=false
200 num_cpus=4
201 phase=0
202 range=0:134217727
203 stats_file=ruby.stats
204 zero=false
205 port=system.membus.port[8]
206