tests/quick/se/50.memtest/ref/null/none/memtest/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 eventq_index=0
   5 full_system=false
   6 sim_quantum=0
   7 time_sync_enable=false
   8 time_sync_period=100000000000
   9 time_sync_spin_threshold=100000000
  10
  11 [system]
  12 type=System
  13 children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 cpu_clk_domain dvfs_handler funcbus funcmem l2c membus physmem toL2Bus voltage_domain
  14 boot_osflags=a
  15 cache_line_size=64
  16 clk_domain=system.clk_domain
  17 eventq_index=0
  18 init_param=0
  19 kernel=
  20 kernel_addr_check=true
  21 load_addr_mask=1099511627775
  22 load_offset=0
  23 mem_mode=timing
  24 mem_ranges=
  25 memories=system.funcmem system.physmem
  26 num_work_ids=16
  27 readfile=
  28 symbolfile=
  29 work_begin_ckpt_count=0
  30 work_begin_cpu_id_exit=-1
  31 work_begin_exit_count=0
  32 work_cpus_ckpt_count=0
  33 work_end_ckpt_count=0
  34 work_end_exit_count=0
  35 work_item_id=-1
  36 system_port=system.membus.slave[1]
  37
  38 [system.clk_domain]
  39 type=SrcClockDomain
  40 clock=1000
  41 domain_id=-1
  42 eventq_index=0
  43 init_perf_level=0
  44 voltage_domain=system.voltage_domain
  45
  46 [system.cpu0]
  47 type=MemTest
  48 children=l1c
  49 atomic=false
  50 clk_domain=system.cpu_clk_domain
  51 eventq_index=0
  52 issue_dmas=false
  53 max_loads=100000
  54 memory_size=65536
  55 percent_dest_unaligned=50
  56 percent_functional=50
  57 percent_reads=65
  58 percent_source_unaligned=50
  59 percent_uncacheable=10
  60 progress_interval=10000
  61 suppress_func_warnings=false
  62 sys=system
  63 trace_addr=0
  64 functional=system.funcbus.slave[0]
  65 test=system.cpu0.l1c.cpu_side
  66
  67 [system.cpu0.l1c]
  68 type=BaseCache
  69 children=tags
  70 addr_ranges=0:18446744073709551615
  71 assoc=4
  72 clk_domain=system.cpu_clk_domain
  73 eventq_index=0
  74 forward_snoops=true
  75 hit_latency=2
  76 is_top_level=true
  77 max_miss_count=0
  78 mshrs=4
  79 prefetch_on_access=false
  80 prefetcher=Null
  81 response_latency=2
  82 sequential_access=false
  83 size=32768
  84 system=system
  85 tags=system.cpu0.l1c.tags
  86 tgts_per_mshr=20
  87 two_queue=false
  88 write_buffers=8
  89 cpu_side=system.cpu0.test
  90 mem_side=system.toL2Bus.slave[0]
  91
  92 [system.cpu0.l1c.tags]
  93 type=LRU
  94 assoc=4
  95 block_size=64
  96 clk_domain=system.cpu_clk_domain
  97 eventq_index=0
  98 hit_latency=2
  99 sequential_access=false
 100 size=32768
 101
 102 [system.cpu1]
 103 type=MemTest
 104 children=l1c
 105 atomic=false
 106 clk_domain=system.cpu_clk_domain
 107 eventq_index=0
 108 issue_dmas=false
 109 max_loads=100000
 110 memory_size=65536
 111 percent_dest_unaligned=50
 112 percent_functional=50
 113 percent_reads=65
 114 percent_source_unaligned=50
 115 percent_uncacheable=10
 116 progress_interval=10000
 117 suppress_func_warnings=false
 118 sys=system
 119 trace_addr=0
 120 functional=system.funcbus.slave[1]
 121 test=system.cpu1.l1c.cpu_side
 122
 123 [system.cpu1.l1c]
 124 type=BaseCache
 125 children=tags
 126 addr_ranges=0:18446744073709551615
 127 assoc=4
 128 clk_domain=system.cpu_clk_domain
 129 eventq_index=0
 130 forward_snoops=true
 131 hit_latency=2
 132 is_top_level=true
 133 max_miss_count=0
 134 mshrs=4
 135 prefetch_on_access=false
 136 prefetcher=Null
 137 response_latency=2
 138 sequential_access=false
 139 size=32768
 140 system=system
 141 tags=system.cpu1.l1c.tags
 142 tgts_per_mshr=20
 143 two_queue=false
 144 write_buffers=8
 145 cpu_side=system.cpu1.test
 146 mem_side=system.toL2Bus.slave[1]
 147
 148 [system.cpu1.l1c.tags]
 149 type=LRU
 150 assoc=4
 151 block_size=64
 152 clk_domain=system.cpu_clk_domain
 153 eventq_index=0
 154 hit_latency=2
 155 sequential_access=false
 156 size=32768
 157
 158 [system.cpu2]
 159 type=MemTest
 160 children=l1c
 161 atomic=false
 162 clk_domain=system.cpu_clk_domain
 163 eventq_index=0
 164 issue_dmas=false
 165 max_loads=100000
 166 memory_size=65536
 167 percent_dest_unaligned=50
 168 percent_functional=50
 169 percent_reads=65
 170 percent_source_unaligned=50
 171 percent_uncacheable=10
 172 progress_interval=10000
 173 suppress_func_warnings=false
 174 sys=system
 175 trace_addr=0
 176 functional=system.funcbus.slave[2]
 177 test=system.cpu2.l1c.cpu_side
 178
 179 [system.cpu2.l1c]
 180 type=BaseCache
 181 children=tags
 182 addr_ranges=0:18446744073709551615
 183 assoc=4
 184 clk_domain=system.cpu_clk_domain
 185 eventq_index=0
 186 forward_snoops=true
 187 hit_latency=2
 188 is_top_level=true
 189 max_miss_count=0
 190 mshrs=4
 191 prefetch_on_access=false
 192 prefetcher=Null
 193 response_latency=2
 194 sequential_access=false
 195 size=32768
 196 system=system
 197 tags=system.cpu2.l1c.tags
 198 tgts_per_mshr=20
 199 two_queue=false
 200 write_buffers=8
 201 cpu_side=system.cpu2.test
 202 mem_side=system.toL2Bus.slave[2]
 203
 204 [system.cpu2.l1c.tags]
 205 type=LRU
 206 assoc=4
 207 block_size=64
 208 clk_domain=system.cpu_clk_domain
 209 eventq_index=0
 210 hit_latency=2
 211 sequential_access=false
 212 size=32768
 213
 214 [system.cpu3]
 215 type=MemTest
 216 children=l1c
 217 atomic=false
 218 clk_domain=system.cpu_clk_domain
 219 eventq_index=0
 220 issue_dmas=false
 221 max_loads=100000
 222 memory_size=65536
 223 percent_dest_unaligned=50
 224 percent_functional=50
 225 percent_reads=65
 226 percent_source_unaligned=50
 227 percent_uncacheable=10
 228 progress_interval=10000
 229 suppress_func_warnings=false
 230 sys=system
 231 trace_addr=0
 232 functional=system.funcbus.slave[3]
 233 test=system.cpu3.l1c.cpu_side
 234
 235 [system.cpu3.l1c]
 236 type=BaseCache
 237 children=tags
 238 addr_ranges=0:18446744073709551615
 239 assoc=4
 240 clk_domain=system.cpu_clk_domain
 241 eventq_index=0
 242 forward_snoops=true
 243 hit_latency=2
 244 is_top_level=true
 245 max_miss_count=0
 246 mshrs=4
 247 prefetch_on_access=false
 248 prefetcher=Null
 249 response_latency=2
 250 sequential_access=false
 251 size=32768
 252 system=system
 253 tags=system.cpu3.l1c.tags
 254 tgts_per_mshr=20
 255 two_queue=false
 256 write_buffers=8
 257 cpu_side=system.cpu3.test
 258 mem_side=system.toL2Bus.slave[3]
 259
 260 [system.cpu3.l1c.tags]
 261 type=LRU
 262 assoc=4
 263 block_size=64
 264 clk_domain=system.cpu_clk_domain
 265 eventq_index=0
 266 hit_latency=2
 267 sequential_access=false
 268 size=32768
 269
 270 [system.cpu4]
 271 type=MemTest
 272 children=l1c
 273 atomic=false
 274 clk_domain=system.cpu_clk_domain
 275 eventq_index=0
 276 issue_dmas=false
 277 max_loads=100000
 278 memory_size=65536
 279 percent_dest_unaligned=50
 280 percent_functional=50
 281 percent_reads=65
 282 percent_source_unaligned=50
 283 percent_uncacheable=10
 284 progress_interval=10000
 285 suppress_func_warnings=false
 286 sys=system
 287 trace_addr=0
 288 functional=system.funcbus.slave[4]
 289 test=system.cpu4.l1c.cpu_side
 290
 291 [system.cpu4.l1c]
 292 type=BaseCache
 293 children=tags
 294 addr_ranges=0:18446744073709551615
 295 assoc=4
 296 clk_domain=system.cpu_clk_domain
 297 eventq_index=0
 298 forward_snoops=true
 299 hit_latency=2
 300 is_top_level=true
 301 max_miss_count=0
 302 mshrs=4
 303 prefetch_on_access=false
 304 prefetcher=Null
 305 response_latency=2
 306 sequential_access=false
 307 size=32768
 308 system=system
 309 tags=system.cpu4.l1c.tags
 310 tgts_per_mshr=20
 311 two_queue=false
 312 write_buffers=8
 313 cpu_side=system.cpu4.test
 314 mem_side=system.toL2Bus.slave[4]
 315
 316 [system.cpu4.l1c.tags]
 317 type=LRU
 318 assoc=4
 319 block_size=64
 320 clk_domain=system.cpu_clk_domain
 321 eventq_index=0
 322 hit_latency=2
 323 sequential_access=false
 324 size=32768
 325
 326 [system.cpu5]
 327 type=MemTest
 328 children=l1c
 329 atomic=false
 330 clk_domain=system.cpu_clk_domain
 331 eventq_index=0
 332 issue_dmas=false
 333 max_loads=100000
 334 memory_size=65536
 335 percent_dest_unaligned=50
 336 percent_functional=50
 337 percent_reads=65
 338 percent_source_unaligned=50
 339 percent_uncacheable=10
 340 progress_interval=10000
 341 suppress_func_warnings=false
 342 sys=system
 343 trace_addr=0
 344 functional=system.funcbus.slave[5]
 345 test=system.cpu5.l1c.cpu_side
 346
 347 [system.cpu5.l1c]
 348 type=BaseCache
 349 children=tags
 350 addr_ranges=0:18446744073709551615
 351 assoc=4
 352 clk_domain=system.cpu_clk_domain
 353 eventq_index=0
 354 forward_snoops=true
 355 hit_latency=2
 356 is_top_level=true
 357 max_miss_count=0
 358 mshrs=4
 359 prefetch_on_access=false
 360 prefetcher=Null
 361 response_latency=2
 362 sequential_access=false
 363 size=32768
 364 system=system
 365 tags=system.cpu5.l1c.tags
 366 tgts_per_mshr=20
 367 two_queue=false
 368 write_buffers=8
 369 cpu_side=system.cpu5.test
 370 mem_side=system.toL2Bus.slave[5]
 371
 372 [system.cpu5.l1c.tags]
 373 type=LRU
 374 assoc=4
 375 block_size=64
 376 clk_domain=system.cpu_clk_domain
 377 eventq_index=0
 378 hit_latency=2
 379 sequential_access=false
 380 size=32768
 381
 382 [system.cpu6]
 383 type=MemTest
 384 children=l1c
 385 atomic=false
 386 clk_domain=system.cpu_clk_domain
 387 eventq_index=0
 388 issue_dmas=false
 389 max_loads=100000
 390 memory_size=65536
 391 percent_dest_unaligned=50
 392 percent_functional=50
 393 percent_reads=65
 394 percent_source_unaligned=50
 395 percent_uncacheable=10
 396 progress_interval=10000
 397 suppress_func_warnings=false
 398 sys=system
 399 trace_addr=0
 400 functional=system.funcbus.slave[6]
 401 test=system.cpu6.l1c.cpu_side
 402
 403 [system.cpu6.l1c]
 404 type=BaseCache
 405 children=tags
 406 addr_ranges=0:18446744073709551615
 407 assoc=4
 408 clk_domain=system.cpu_clk_domain
 409 eventq_index=0
 410 forward_snoops=true
 411 hit_latency=2
 412 is_top_level=true
 413 max_miss_count=0
 414 mshrs=4
 415 prefetch_on_access=false
 416 prefetcher=Null
 417 response_latency=2
 418 sequential_access=false
 419 size=32768
 420 system=system
 421 tags=system.cpu6.l1c.tags
 422 tgts_per_mshr=20
 423 two_queue=false
 424 write_buffers=8
 425 cpu_side=system.cpu6.test
 426 mem_side=system.toL2Bus.slave[6]
 427
 428 [system.cpu6.l1c.tags]
 429 type=LRU
 430 assoc=4
 431 block_size=64
 432 clk_domain=system.cpu_clk_domain
 433 eventq_index=0
 434 hit_latency=2
 435 sequential_access=false
 436 size=32768
 437
 438 [system.cpu7]
 439 type=MemTest
 440 children=l1c
 441 atomic=false
 442 clk_domain=system.cpu_clk_domain
 443 eventq_index=0
 444 issue_dmas=false
 445 max_loads=100000
 446 memory_size=65536
 447 percent_dest_unaligned=50
 448 percent_functional=50
 449 percent_reads=65
 450 percent_source_unaligned=50
 451 percent_uncacheable=10
 452 progress_interval=10000
 453 suppress_func_warnings=false
 454 sys=system
 455 trace_addr=0
 456 functional=system.funcbus.slave[7]
 457 test=system.cpu7.l1c.cpu_side
 458
 459 [system.cpu7.l1c]
 460 type=BaseCache
 461 children=tags
 462 addr_ranges=0:18446744073709551615
 463 assoc=4
 464 clk_domain=system.cpu_clk_domain
 465 eventq_index=0
 466 forward_snoops=true
 467 hit_latency=2
 468 is_top_level=true
 469 max_miss_count=0
 470 mshrs=4
 471 prefetch_on_access=false
 472 prefetcher=Null
 473 response_latency=2
 474 sequential_access=false
 475 size=32768
 476 system=system
 477 tags=system.cpu7.l1c.tags
 478 tgts_per_mshr=20
 479 two_queue=false
 480 write_buffers=8
 481 cpu_side=system.cpu7.test
 482 mem_side=system.toL2Bus.slave[7]
 483
 484 [system.cpu7.l1c.tags]
 485 type=LRU
 486 assoc=4
 487 block_size=64
 488 clk_domain=system.cpu_clk_domain
 489 eventq_index=0
 490 hit_latency=2
 491 sequential_access=false
 492 size=32768
 493
 494 [system.cpu_clk_domain]
 495 type=SrcClockDomain
 496 clock=500
 497 domain_id=-1
 498 eventq_index=0
 499 init_perf_level=0
 500 voltage_domain=system.voltage_domain
 501
 502 [system.dvfs_handler]
 503 type=DVFSHandler
 504 domains=
 505 enable=false
 506 eventq_index=0
 507 sys_clk_domain=system.clk_domain
 508 transition_latency=100000000
 509
 510 [system.funcbus]
 511 type=NoncoherentBus
 512 clk_domain=system.clk_domain
 513 eventq_index=0
 514 header_cycles=1
 515 use_default_range=false
 516 width=8
 517 master=system.funcmem.port
 518 slave=system.cpu0.functional system.cpu1.functional system.cpu2.functional system.cpu3.functional system.cpu4.functional system.cpu5.functional system.cpu6.functional system.cpu7.functional
 519
 520 [system.funcmem]
 521 type=SimpleMemory
 522 bandwidth=73.000000
 523 clk_domain=system.clk_domain
 524 conf_table_reported=true
 525 eventq_index=0
 526 in_addr_map=false
 527 latency=30000
 528 latency_var=0
 529 null=false
 530 range=0:134217727
 531 port=system.funcbus.master[0]
 532
 533 [system.l2c]
 534 type=BaseCache
 535 children=tags
 536 addr_ranges=0:18446744073709551615
 537 assoc=8
 538 clk_domain=system.cpu_clk_domain
 539 eventq_index=0
 540 forward_snoops=true
 541 hit_latency=20
 542 is_top_level=false
 543 max_miss_count=0
 544 mshrs=20
 545 prefetch_on_access=false
 546 prefetcher=Null
 547 response_latency=20
 548 sequential_access=false
 549 size=65536
 550 system=system
 551 tags=system.l2c.tags
 552 tgts_per_mshr=12
 553 two_queue=false
 554 write_buffers=8
 555 cpu_side=system.toL2Bus.master[0]
 556 mem_side=system.membus.slave[0]
 557
 558 [system.l2c.tags]
 559 type=LRU
 560 assoc=8
 561 block_size=64
 562 clk_domain=system.cpu_clk_domain
 563 eventq_index=0
 564 hit_latency=20
 565 sequential_access=false
 566 size=65536
 567
 568 [system.membus]
 569 type=CoherentBus
 570 clk_domain=system.clk_domain
 571 eventq_index=0
 572 header_cycles=1
 573 system=system
 574 use_default_range=false
 575 width=16
 576 master=system.physmem.port
 577 slave=system.l2c.mem_side system.system_port
 578
 579 [system.physmem]
 580 type=SimpleMemory
 581 bandwidth=73.000000
 582 clk_domain=system.clk_domain
 583 conf_table_reported=true
 584 eventq_index=0
 585 in_addr_map=true
 586 latency=30000
 587 latency_var=0
 588 null=false
 589 range=0:134217727
 590 port=system.membus.master[0]
 591
 592 [system.toL2Bus]
 593 type=CoherentBus
 594 clk_domain=system.cpu_clk_domain
 595 eventq_index=0
 596 header_cycles=1
 597 system=system
 598 use_default_range=false
 599 width=16
 600 master=system.l2c.cpu_side
 601 slave=system.cpu0.l1c.mem_side system.cpu1.l1c.mem_side system.cpu2.l1c.mem_side system.cpu3.l1c.mem_side system.cpu4.l1c.mem_side system.cpu5.l1c.mem_side system.cpu6.l1c.mem_side system.cpu7.l1c.mem_side
 602
 603 [system.voltage_domain]
 604 type=VoltageDomain
 605 eventq_index=0
 606 voltage=1.000000
 607