tests/quick/se/50.memtest/ref/null/none/memtest-filter/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 eventq_index=0
   5 full_system=false
   6 sim_quantum=0
   7 time_sync_enable=false
   8 time_sync_period=100000000000
   9 time_sync_spin_threshold=100000000
  10
  11 [system]
  12 type=System
  13 children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 cpu_clk_domain dvfs_handler l2c membus physmem toL2Bus voltage_domain
  14 boot_osflags=a
  15 cache_line_size=64
  16 clk_domain=system.clk_domain
  17 eventq_index=0
  18 init_param=0
  19 kernel=
  20 kernel_addr_check=true
  21 load_addr_mask=1099511627775
  22 load_offset=0
  23 mem_mode=timing
  24 mem_ranges=
  25 memories=system.physmem
  26 mmap_using_noreserve=false
  27 num_work_ids=16
  28 readfile=
  29 symbolfile=
  30 work_begin_ckpt_count=0
  31 work_begin_cpu_id_exit=-1
  32 work_begin_exit_count=0
  33 work_cpus_ckpt_count=0
  34 work_end_ckpt_count=0
  35 work_end_exit_count=0
  36 work_item_id=-1
  37 system_port=system.membus.slave[1]
  38
  39 [system.clk_domain]
  40 type=SrcClockDomain
  41 clock=1000
  42 domain_id=-1
  43 eventq_index=0
  44 init_perf_level=0
  45 voltage_domain=system.voltage_domain
  46
  47 [system.cpu0]
  48 type=MemTest
  49 children=l1c
  50 clk_domain=system.cpu_clk_domain
  51 eventq_index=0
  52 interval=1
  53 max_loads=100000
  54 percent_functional=50
  55 percent_reads=65
  56 percent_uncacheable=10
  57 progress_check=5000000
  58 progress_interval=10000
  59 size=65536
  60 suppress_func_warnings=false
  61 system=system
  62 port=system.cpu0.l1c.cpu_side
  63
  64 [system.cpu0.l1c]
  65 type=BaseCache
  66 children=tags
  67 addr_ranges=0:18446744073709551615
  68 assoc=4
  69 clk_domain=system.cpu_clk_domain
  70 demand_mshr_reserve=1
  71 eventq_index=0
  72 forward_snoops=true
  73 hit_latency=2
  74 is_read_only=false
  75 max_miss_count=0
  76 mshrs=4
  77 prefetch_on_access=false
  78 prefetcher=Null
  79 response_latency=2
  80 sequential_access=false
  81 size=32768
  82 system=system
  83 tags=system.cpu0.l1c.tags
  84 tgts_per_mshr=20
  85 write_buffers=8
  86 cpu_side=system.cpu0.port
  87 mem_side=system.toL2Bus.slave[0]
  88
  89 [system.cpu0.l1c.tags]
  90 type=LRU
  91 assoc=4
  92 block_size=64
  93 clk_domain=system.cpu_clk_domain
  94 eventq_index=0
  95 hit_latency=2
  96 sequential_access=false
  97 size=32768
  98
  99 [system.cpu1]
 100 type=MemTest
 101 children=l1c
 102 clk_domain=system.cpu_clk_domain
 103 eventq_index=0
 104 interval=1
 105 max_loads=100000
 106 percent_functional=50
 107 percent_reads=65
 108 percent_uncacheable=10
 109 progress_check=5000000
 110 progress_interval=10000
 111 size=65536
 112 suppress_func_warnings=false
 113 system=system
 114 port=system.cpu1.l1c.cpu_side
 115
 116 [system.cpu1.l1c]
 117 type=BaseCache
 118 children=tags
 119 addr_ranges=0:18446744073709551615
 120 assoc=4
 121 clk_domain=system.cpu_clk_domain
 122 demand_mshr_reserve=1
 123 eventq_index=0
 124 forward_snoops=true
 125 hit_latency=2
 126 is_read_only=false
 127 max_miss_count=0
 128 mshrs=4
 129 prefetch_on_access=false
 130 prefetcher=Null
 131 response_latency=2
 132 sequential_access=false
 133 size=32768
 134 system=system
 135 tags=system.cpu1.l1c.tags
 136 tgts_per_mshr=20
 137 write_buffers=8
 138 cpu_side=system.cpu1.port
 139 mem_side=system.toL2Bus.slave[1]
 140
 141 [system.cpu1.l1c.tags]
 142 type=LRU
 143 assoc=4
 144 block_size=64
 145 clk_domain=system.cpu_clk_domain
 146 eventq_index=0
 147 hit_latency=2
 148 sequential_access=false
 149 size=32768
 150
 151 [system.cpu2]
 152 type=MemTest
 153 children=l1c
 154 clk_domain=system.cpu_clk_domain
 155 eventq_index=0
 156 interval=1
 157 max_loads=100000
 158 percent_functional=50
 159 percent_reads=65
 160 percent_uncacheable=10
 161 progress_check=5000000
 162 progress_interval=10000
 163 size=65536
 164 suppress_func_warnings=false
 165 system=system
 166 port=system.cpu2.l1c.cpu_side
 167
 168 [system.cpu2.l1c]
 169 type=BaseCache
 170 children=tags
 171 addr_ranges=0:18446744073709551615
 172 assoc=4
 173 clk_domain=system.cpu_clk_domain
 174 demand_mshr_reserve=1
 175 eventq_index=0
 176 forward_snoops=true
 177 hit_latency=2
 178 is_read_only=false
 179 max_miss_count=0
 180 mshrs=4
 181 prefetch_on_access=false
 182 prefetcher=Null
 183 response_latency=2
 184 sequential_access=false
 185 size=32768
 186 system=system
 187 tags=system.cpu2.l1c.tags
 188 tgts_per_mshr=20
 189 write_buffers=8
 190 cpu_side=system.cpu2.port
 191 mem_side=system.toL2Bus.slave[2]
 192
 193 [system.cpu2.l1c.tags]
 194 type=LRU
 195 assoc=4
 196 block_size=64
 197 clk_domain=system.cpu_clk_domain
 198 eventq_index=0
 199 hit_latency=2
 200 sequential_access=false
 201 size=32768
 202
 203 [system.cpu3]
 204 type=MemTest
 205 children=l1c
 206 clk_domain=system.cpu_clk_domain
 207 eventq_index=0
 208 interval=1
 209 max_loads=100000
 210 percent_functional=50
 211 percent_reads=65
 212 percent_uncacheable=10
 213 progress_check=5000000
 214 progress_interval=10000
 215 size=65536
 216 suppress_func_warnings=false
 217 system=system
 218 port=system.cpu3.l1c.cpu_side
 219
 220 [system.cpu3.l1c]
 221 type=BaseCache
 222 children=tags
 223 addr_ranges=0:18446744073709551615
 224 assoc=4
 225 clk_domain=system.cpu_clk_domain
 226 demand_mshr_reserve=1
 227 eventq_index=0
 228 forward_snoops=true
 229 hit_latency=2
 230 is_read_only=false
 231 max_miss_count=0
 232 mshrs=4
 233 prefetch_on_access=false
 234 prefetcher=Null
 235 response_latency=2
 236 sequential_access=false
 237 size=32768
 238 system=system
 239 tags=system.cpu3.l1c.tags
 240 tgts_per_mshr=20
 241 write_buffers=8
 242 cpu_side=system.cpu3.port
 243 mem_side=system.toL2Bus.slave[3]
 244
 245 [system.cpu3.l1c.tags]
 246 type=LRU
 247 assoc=4
 248 block_size=64
 249 clk_domain=system.cpu_clk_domain
 250 eventq_index=0
 251 hit_latency=2
 252 sequential_access=false
 253 size=32768
 254
 255 [system.cpu4]
 256 type=MemTest
 257 children=l1c
 258 clk_domain=system.cpu_clk_domain
 259 eventq_index=0
 260 interval=1
 261 max_loads=100000
 262 percent_functional=50
 263 percent_reads=65
 264 percent_uncacheable=10
 265 progress_check=5000000
 266 progress_interval=10000
 267 size=65536
 268 suppress_func_warnings=false
 269 system=system
 270 port=system.cpu4.l1c.cpu_side
 271
 272 [system.cpu4.l1c]
 273 type=BaseCache
 274 children=tags
 275 addr_ranges=0:18446744073709551615
 276 assoc=4
 277 clk_domain=system.cpu_clk_domain
 278 demand_mshr_reserve=1
 279 eventq_index=0
 280 forward_snoops=true
 281 hit_latency=2
 282 is_read_only=false
 283 max_miss_count=0
 284 mshrs=4
 285 prefetch_on_access=false
 286 prefetcher=Null
 287 response_latency=2
 288 sequential_access=false
 289 size=32768
 290 system=system
 291 tags=system.cpu4.l1c.tags
 292 tgts_per_mshr=20
 293 write_buffers=8
 294 cpu_side=system.cpu4.port
 295 mem_side=system.toL2Bus.slave[4]
 296
 297 [system.cpu4.l1c.tags]
 298 type=LRU
 299 assoc=4
 300 block_size=64
 301 clk_domain=system.cpu_clk_domain
 302 eventq_index=0
 303 hit_latency=2
 304 sequential_access=false
 305 size=32768
 306
 307 [system.cpu5]
 308 type=MemTest
 309 children=l1c
 310 clk_domain=system.cpu_clk_domain
 311 eventq_index=0
 312 interval=1
 313 max_loads=100000
 314 percent_functional=50
 315 percent_reads=65
 316 percent_uncacheable=10
 317 progress_check=5000000
 318 progress_interval=10000
 319 size=65536
 320 suppress_func_warnings=false
 321 system=system
 322 port=system.cpu5.l1c.cpu_side
 323
 324 [system.cpu5.l1c]
 325 type=BaseCache
 326 children=tags
 327 addr_ranges=0:18446744073709551615
 328 assoc=4
 329 clk_domain=system.cpu_clk_domain
 330 demand_mshr_reserve=1
 331 eventq_index=0
 332 forward_snoops=true
 333 hit_latency=2
 334 is_read_only=false
 335 max_miss_count=0
 336 mshrs=4
 337 prefetch_on_access=false
 338 prefetcher=Null
 339 response_latency=2
 340 sequential_access=false
 341 size=32768
 342 system=system
 343 tags=system.cpu5.l1c.tags
 344 tgts_per_mshr=20
 345 write_buffers=8
 346 cpu_side=system.cpu5.port
 347 mem_side=system.toL2Bus.slave[5]
 348
 349 [system.cpu5.l1c.tags]
 350 type=LRU
 351 assoc=4
 352 block_size=64
 353 clk_domain=system.cpu_clk_domain
 354 eventq_index=0
 355 hit_latency=2
 356 sequential_access=false
 357 size=32768
 358
 359 [system.cpu6]
 360 type=MemTest
 361 children=l1c
 362 clk_domain=system.cpu_clk_domain
 363 eventq_index=0
 364 interval=1
 365 max_loads=100000
 366 percent_functional=50
 367 percent_reads=65
 368 percent_uncacheable=10
 369 progress_check=5000000
 370 progress_interval=10000
 371 size=65536
 372 suppress_func_warnings=false
 373 system=system
 374 port=system.cpu6.l1c.cpu_side
 375
 376 [system.cpu6.l1c]
 377 type=BaseCache
 378 children=tags
 379 addr_ranges=0:18446744073709551615
 380 assoc=4
 381 clk_domain=system.cpu_clk_domain
 382 demand_mshr_reserve=1
 383 eventq_index=0
 384 forward_snoops=true
 385 hit_latency=2
 386 is_read_only=false
 387 max_miss_count=0
 388 mshrs=4
 389 prefetch_on_access=false
 390 prefetcher=Null
 391 response_latency=2
 392 sequential_access=false
 393 size=32768
 394 system=system
 395 tags=system.cpu6.l1c.tags
 396 tgts_per_mshr=20
 397 write_buffers=8
 398 cpu_side=system.cpu6.port
 399 mem_side=system.toL2Bus.slave[6]
 400
 401 [system.cpu6.l1c.tags]
 402 type=LRU
 403 assoc=4
 404 block_size=64
 405 clk_domain=system.cpu_clk_domain
 406 eventq_index=0
 407 hit_latency=2
 408 sequential_access=false
 409 size=32768
 410
 411 [system.cpu7]
 412 type=MemTest
 413 children=l1c
 414 clk_domain=system.cpu_clk_domain
 415 eventq_index=0
 416 interval=1
 417 max_loads=100000
 418 percent_functional=50
 419 percent_reads=65
 420 percent_uncacheable=10
 421 progress_check=5000000
 422 progress_interval=10000
 423 size=65536
 424 suppress_func_warnings=false
 425 system=system
 426 port=system.cpu7.l1c.cpu_side
 427
 428 [system.cpu7.l1c]
 429 type=BaseCache
 430 children=tags
 431 addr_ranges=0:18446744073709551615
 432 assoc=4
 433 clk_domain=system.cpu_clk_domain
 434 demand_mshr_reserve=1
 435 eventq_index=0
 436 forward_snoops=true
 437 hit_latency=2
 438 is_read_only=false
 439 max_miss_count=0
 440 mshrs=4
 441 prefetch_on_access=false
 442 prefetcher=Null
 443 response_latency=2
 444 sequential_access=false
 445 size=32768
 446 system=system
 447 tags=system.cpu7.l1c.tags
 448 tgts_per_mshr=20
 449 write_buffers=8
 450 cpu_side=system.cpu7.port
 451 mem_side=system.toL2Bus.slave[7]
 452
 453 [system.cpu7.l1c.tags]
 454 type=LRU
 455 assoc=4
 456 block_size=64
 457 clk_domain=system.cpu_clk_domain
 458 eventq_index=0
 459 hit_latency=2
 460 sequential_access=false
 461 size=32768
 462
 463 [system.cpu_clk_domain]
 464 type=SrcClockDomain
 465 clock=500
 466 domain_id=-1
 467 eventq_index=0
 468 init_perf_level=0
 469 voltage_domain=system.voltage_domain
 470
 471 [system.dvfs_handler]
 472 type=DVFSHandler
 473 domains=
 474 enable=false
 475 eventq_index=0
 476 sys_clk_domain=system.clk_domain
 477 transition_latency=100000000
 478
 479 [system.l2c]
 480 type=BaseCache
 481 children=tags
 482 addr_ranges=0:18446744073709551615
 483 assoc=8
 484 clk_domain=system.cpu_clk_domain
 485 demand_mshr_reserve=1
 486 eventq_index=0
 487 forward_snoops=true
 488 hit_latency=20
 489 is_read_only=false
 490 max_miss_count=0
 491 mshrs=20
 492 prefetch_on_access=false
 493 prefetcher=Null
 494 response_latency=20
 495 sequential_access=false
 496 size=65536
 497 system=system
 498 tags=system.l2c.tags
 499 tgts_per_mshr=12
 500 write_buffers=8
 501 cpu_side=system.toL2Bus.master[0]
 502 mem_side=system.membus.slave[0]
 503
 504 [system.l2c.tags]
 505 type=LRU
 506 assoc=8
 507 block_size=64
 508 clk_domain=system.cpu_clk_domain
 509 eventq_index=0
 510 hit_latency=20
 511 sequential_access=false
 512 size=65536
 513
 514 [system.membus]
 515 type=CoherentXBar
 516 children=snoop_filter
 517 clk_domain=system.clk_domain
 518 eventq_index=0
 519 forward_latency=4
 520 frontend_latency=3
 521 response_latency=2
 522 snoop_filter=system.membus.snoop_filter
 523 snoop_response_latency=4
 524 system=system
 525 use_default_range=false
 526 width=16
 527 master=system.physmem.port
 528 slave=system.l2c.mem_side system.system_port
 529
 530 [system.membus.snoop_filter]
 531 type=SnoopFilter
 532 eventq_index=0
 533 lookup_latency=1
 534 system=system
 535
 536 [system.physmem]
 537 type=SimpleMemory
 538 bandwidth=73.000000
 539 clk_domain=system.clk_domain
 540 conf_table_reported=true
 541 eventq_index=0
 542 in_addr_map=true
 543 latency=30000
 544 latency_var=0
 545 null=false
 546 range=0:134217727
 547 port=system.membus.master[0]
 548
 549 [system.toL2Bus]
 550 type=CoherentXBar
 551 children=snoop_filter
 552 clk_domain=system.cpu_clk_domain
 553 eventq_index=0
 554 forward_latency=0
 555 frontend_latency=1
 556 response_latency=1
 557 snoop_filter=system.toL2Bus.snoop_filter
 558 snoop_response_latency=1
 559 system=system
 560 use_default_range=false
 561 width=32
 562 master=system.l2c.cpu_side
 563 slave=system.cpu0.l1c.mem_side system.cpu1.l1c.mem_side system.cpu2.l1c.mem_side system.cpu3.l1c.mem_side system.cpu4.l1c.mem_side system.cpu5.l1c.mem_side system.cpu6.l1c.mem_side system.cpu7.l1c.mem_side
 564
 565 [system.toL2Bus.snoop_filter]
 566 type=SnoopFilter
 567 eventq_index=0
 568 lookup_latency=1
 569 system=system
 570
 571 [system.voltage_domain]
 572 type=VoltageDomain
 573 eventq_index=0
 574 voltage=1.000000
 575