2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.000541 # Number of seconds simulated
4 sim_ticks 540820000 # Number of ticks simulated
5 final_tick 540820000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_tick_rate 45415693 # Simulator tick rate (ticks/s)
8 host_mem_usage 216096 # Number of bytes of host memory used
9 host_seconds 11.91 # Real time elapsed on the host
10 system.voltage_domain.voltage 1 # Voltage in Volts
11 system.clk_domain.clock 1000 # Clock period in ticks
12 system.physmem.bytes_read::cpu0 88157 # Number of bytes read from this memory
13 system.physmem.bytes_read::cpu1 82701 # Number of bytes read from this memory
14 system.physmem.bytes_read::cpu2 84142 # Number of bytes read from this memory
15 system.physmem.bytes_read::cpu3 82645 # Number of bytes read from this memory
16 system.physmem.bytes_read::cpu4 83993 # Number of bytes read from this memory
17 system.physmem.bytes_read::cpu5 79749 # Number of bytes read from this memory
18 system.physmem.bytes_read::cpu6 78765 # Number of bytes read from this memory
19 system.physmem.bytes_read::cpu7 84222 # Number of bytes read from this memory
20 system.physmem.bytes_read::total 664374 # Number of bytes read from this memory
21 system.physmem.bytes_written::writebacks 426368 # Number of bytes written to this memory
22 system.physmem.bytes_written::cpu0 5567 # Number of bytes written to this memory
23 system.physmem.bytes_written::cpu1 5462 # Number of bytes written to this memory
24 system.physmem.bytes_written::cpu2 5416 # Number of bytes written to this memory
25 system.physmem.bytes_written::cpu3 5447 # Number of bytes written to this memory
26 system.physmem.bytes_written::cpu4 5329 # Number of bytes written to this memory
27 system.physmem.bytes_written::cpu5 5472 # Number of bytes written to this memory
28 system.physmem.bytes_written::cpu6 5531 # Number of bytes written to this memory
29 system.physmem.bytes_written::cpu7 5421 # Number of bytes written to this memory
30 system.physmem.bytes_written::total 470013 # Number of bytes written to this memory
31 system.physmem.num_reads::cpu0 11108 # Number of read requests responded to by this memory
32 system.physmem.num_reads::cpu1 10881 # Number of read requests responded to by this memory
33 system.physmem.num_reads::cpu2 10936 # Number of read requests responded to by this memory
34 system.physmem.num_reads::cpu3 10951 # Number of read requests responded to by this memory
35 system.physmem.num_reads::cpu4 11102 # Number of read requests responded to by this memory
36 system.physmem.num_reads::cpu5 10890 # Number of read requests responded to by this memory
37 system.physmem.num_reads::cpu6 10914 # Number of read requests responded to by this memory
38 system.physmem.num_reads::cpu7 11079 # Number of read requests responded to by this memory
39 system.physmem.num_reads::total 87861 # Number of read requests responded to by this memory
40 system.physmem.num_writes::writebacks 6662 # Number of write requests responded to by this memory
41 system.physmem.num_writes::cpu0 5567 # Number of write requests responded to by this memory
42 system.physmem.num_writes::cpu1 5462 # Number of write requests responded to by this memory
43 system.physmem.num_writes::cpu2 5416 # Number of write requests responded to by this memory
44 system.physmem.num_writes::cpu3 5447 # Number of write requests responded to by this memory
45 system.physmem.num_writes::cpu4 5329 # Number of write requests responded to by this memory
46 system.physmem.num_writes::cpu5 5472 # Number of write requests responded to by this memory
47 system.physmem.num_writes::cpu6 5531 # Number of write requests responded to by this memory
48 system.physmem.num_writes::cpu7 5421 # Number of write requests responded to by this memory
49 system.physmem.num_writes::total 50307 # Number of write requests responded to by this memory
50 system.physmem.bw_read::cpu0 163006176 # Total read bandwidth from this memory (bytes/s)
51 system.physmem.bw_read::cpu1 152917792 # Total read bandwidth from this memory (bytes/s)
52 system.physmem.bw_read::cpu2 155582264 # Total read bandwidth from this memory (bytes/s)
53 system.physmem.bw_read::cpu3 152814245 # Total read bandwidth from this memory (bytes/s)
54 system.physmem.bw_read::cpu4 155306756 # Total read bandwidth from this memory (bytes/s)
55 system.physmem.bw_read::cpu5 147459413 # Total read bandwidth from this memory (bytes/s)
56 system.physmem.bw_read::cpu6 145639954 # Total read bandwidth from this memory (bytes/s)
57 system.physmem.bw_read::cpu7 155730187 # Total read bandwidth from this memory (bytes/s)
58 system.physmem.bw_read::total 1228456788 # Total read bandwidth from this memory (bytes/s)
59 system.physmem.bw_write::writebacks 788373211 # Write bandwidth from this memory (bytes/s)
60 system.physmem.bw_write::cpu0 10293628 # Write bandwidth from this memory (bytes/s)
61 system.physmem.bw_write::cpu1 10099479 # Write bandwidth from this memory (bytes/s)
62 system.physmem.bw_write::cpu2 10014423 # Write bandwidth from this memory (bytes/s)
63 system.physmem.bw_write::cpu3 10071743 # Write bandwidth from this memory (bytes/s)
64 system.physmem.bw_write::cpu4 9853556 # Write bandwidth from this memory (bytes/s)
65 system.physmem.bw_write::cpu5 10117969 # Write bandwidth from this memory (bytes/s)
66 system.physmem.bw_write::cpu6 10227063 # Write bandwidth from this memory (bytes/s)
67 system.physmem.bw_write::cpu7 10023668 # Write bandwidth from this memory (bytes/s)
68 system.physmem.bw_write::total 869074738 # Write bandwidth from this memory (bytes/s)
69 system.physmem.bw_total::writebacks 788373211 # Total bandwidth to/from this memory (bytes/s)
70 system.physmem.bw_total::cpu0 173299804 # Total bandwidth to/from this memory (bytes/s)
71 system.physmem.bw_total::cpu1 163017270 # Total bandwidth to/from this memory (bytes/s)
72 system.physmem.bw_total::cpu2 165596687 # Total bandwidth to/from this memory (bytes/s)
73 system.physmem.bw_total::cpu3 162885988 # Total bandwidth to/from this memory (bytes/s)
74 system.physmem.bw_total::cpu4 165160312 # Total bandwidth to/from this memory (bytes/s)
75 system.physmem.bw_total::cpu5 157577382 # Total bandwidth to/from this memory (bytes/s)
76 system.physmem.bw_total::cpu6 155867017 # Total bandwidth to/from this memory (bytes/s)
77 system.physmem.bw_total::cpu7 165753855 # Total bandwidth to/from this memory (bytes/s)
78 system.physmem.bw_total::total 2097531526 # Total bandwidth to/from this memory (bytes/s)
79 system.cpu_clk_domain.clock 500 # Clock period in ticks
80 system.cpu0.num_reads 99596 # number of read accesses completed
81 system.cpu0.num_writes 55268 # number of write accesses completed
82 system.cpu0.l1c.tags.replacements 22066 # number of replacements
83 system.cpu0.l1c.tags.tagsinuse 391.486377 # Cycle average of tags in use
84 system.cpu0.l1c.tags.total_refs 13717 # Total number of references to valid blocks.
85 system.cpu0.l1c.tags.sampled_refs 22459 # Sample count of references to valid blocks.
86 system.cpu0.l1c.tags.avg_refs 0.610757 # Average number of references to valid blocks.
87 system.cpu0.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
88 system.cpu0.l1c.tags.occ_blocks::cpu0 391.486377 # Average occupied blocks per requestor
89 system.cpu0.l1c.tags.occ_percent::cpu0 0.764622 # Average percentage of cache occupancy
90 system.cpu0.l1c.tags.occ_percent::total 0.764622 # Average percentage of cache occupancy
91 system.cpu0.l1c.tags.occ_task_id_blocks::1024 393 # Occupied blocks per task id
92 system.cpu0.l1c.tags.age_task_id_blocks_1024::0 384 # Occupied blocks per task id
93 system.cpu0.l1c.tags.age_task_id_blocks_1024::1 9 # Occupied blocks per task id
94 system.cpu0.l1c.tags.occ_task_id_percent::1024 0.767578 # Percentage of cache occupancy per task id
95 system.cpu0.l1c.tags.tag_accesses 338295 # Number of tag accesses
96 system.cpu0.l1c.tags.data_accesses 338295 # Number of data accesses
97 system.cpu0.l1c.ReadReq_hits::cpu0 8878 # number of ReadReq hits
98 system.cpu0.l1c.ReadReq_hits::total 8878 # number of ReadReq hits
99 system.cpu0.l1c.WriteReq_hits::cpu0 1162 # number of WriteReq hits
100 system.cpu0.l1c.WriteReq_hits::total 1162 # number of WriteReq hits
101 system.cpu0.l1c.demand_hits::cpu0 10040 # number of demand (read+write) hits
102 system.cpu0.l1c.demand_hits::total 10040 # number of demand (read+write) hits
103 system.cpu0.l1c.overall_hits::cpu0 10040 # number of overall hits
104 system.cpu0.l1c.overall_hits::total 10040 # number of overall hits
105 system.cpu0.l1c.ReadReq_misses::cpu0 36478 # number of ReadReq misses
106 system.cpu0.l1c.ReadReq_misses::total 36478 # number of ReadReq misses
107 system.cpu0.l1c.WriteReq_misses::cpu0 23899 # number of WriteReq misses
108 system.cpu0.l1c.WriteReq_misses::total 23899 # number of WriteReq misses
109 system.cpu0.l1c.demand_misses::cpu0 60377 # number of demand (read+write) misses
110 system.cpu0.l1c.demand_misses::total 60377 # number of demand (read+write) misses
111 system.cpu0.l1c.overall_misses::cpu0 60377 # number of overall misses
112 system.cpu0.l1c.overall_misses::total 60377 # number of overall misses
113 system.cpu0.l1c.ReadReq_miss_latency::cpu0 603408975 # number of ReadReq miss cycles
114 system.cpu0.l1c.ReadReq_miss_latency::total 603408975 # number of ReadReq miss cycles
115 system.cpu0.l1c.WriteReq_miss_latency::cpu0 722750184 # number of WriteReq miss cycles
116 system.cpu0.l1c.WriteReq_miss_latency::total 722750184 # number of WriteReq miss cycles
117 system.cpu0.l1c.demand_miss_latency::cpu0 1326159159 # number of demand (read+write) miss cycles
118 system.cpu0.l1c.demand_miss_latency::total 1326159159 # number of demand (read+write) miss cycles
119 system.cpu0.l1c.overall_miss_latency::cpu0 1326159159 # number of overall miss cycles
120 system.cpu0.l1c.overall_miss_latency::total 1326159159 # number of overall miss cycles
121 system.cpu0.l1c.ReadReq_accesses::cpu0 45356 # number of ReadReq accesses(hits+misses)
122 system.cpu0.l1c.ReadReq_accesses::total 45356 # number of ReadReq accesses(hits+misses)
123 system.cpu0.l1c.WriteReq_accesses::cpu0 25061 # number of WriteReq accesses(hits+misses)
124 system.cpu0.l1c.WriteReq_accesses::total 25061 # number of WriteReq accesses(hits+misses)
125 system.cpu0.l1c.demand_accesses::cpu0 70417 # number of demand (read+write) accesses
126 system.cpu0.l1c.demand_accesses::total 70417 # number of demand (read+write) accesses
127 system.cpu0.l1c.overall_accesses::cpu0 70417 # number of overall (read+write) accesses
128 system.cpu0.l1c.overall_accesses::total 70417 # number of overall (read+write) accesses
129 system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.804260 # miss rate for ReadReq accesses
130 system.cpu0.l1c.ReadReq_miss_rate::total 0.804260 # miss rate for ReadReq accesses
131 system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.953633 # miss rate for WriteReq accesses
132 system.cpu0.l1c.WriteReq_miss_rate::total 0.953633 # miss rate for WriteReq accesses
133 system.cpu0.l1c.demand_miss_rate::cpu0 0.857421 # miss rate for demand accesses
134 system.cpu0.l1c.demand_miss_rate::total 0.857421 # miss rate for demand accesses
135 system.cpu0.l1c.overall_miss_rate::cpu0 0.857421 # miss rate for overall accesses
136 system.cpu0.l1c.overall_miss_rate::total 0.857421 # miss rate for overall accesses
137 system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 16541.723093 # average ReadReq miss latency
138 system.cpu0.l1c.ReadReq_avg_miss_latency::total 16541.723093 # average ReadReq miss latency
139 system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 30241.858823 # average WriteReq miss latency
140 system.cpu0.l1c.WriteReq_avg_miss_latency::total 30241.858823 # average WriteReq miss latency
141 system.cpu0.l1c.demand_avg_miss_latency::cpu0 21964.641486 # average overall miss latency
142 system.cpu0.l1c.demand_avg_miss_latency::total 21964.641486 # average overall miss latency
143 system.cpu0.l1c.overall_avg_miss_latency::cpu0 21964.641486 # average overall miss latency
144 system.cpu0.l1c.overall_avg_miss_latency::total 21964.641486 # average overall miss latency
145 system.cpu0.l1c.blocked_cycles::no_mshrs 828428 # number of cycles access was blocked
146 system.cpu0.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
147 system.cpu0.l1c.blocked::no_mshrs 62795 # number of cycles access was blocked
148 system.cpu0.l1c.blocked::no_targets 0 # number of cycles access was blocked
149 system.cpu0.l1c.avg_blocked_cycles::no_mshrs 13.192579 # average number of cycles each access was blocked
150 system.cpu0.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
151 system.cpu0.l1c.fast_writes 0 # number of fast writes performed
152 system.cpu0.l1c.cache_copies 0 # number of cache copies performed
153 system.cpu0.l1c.writebacks::writebacks 9669 # number of writebacks
154 system.cpu0.l1c.writebacks::total 9669 # number of writebacks
155 system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36478 # number of ReadReq MSHR misses
156 system.cpu0.l1c.ReadReq_mshr_misses::total 36478 # number of ReadReq MSHR misses
157 system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23899 # number of WriteReq MSHR misses
158 system.cpu0.l1c.WriteReq_mshr_misses::total 23899 # number of WriteReq MSHR misses
159 system.cpu0.l1c.demand_mshr_misses::cpu0 60377 # number of demand (read+write) MSHR misses
160 system.cpu0.l1c.demand_mshr_misses::total 60377 # number of demand (read+write) MSHR misses
161 system.cpu0.l1c.overall_mshr_misses::cpu0 60377 # number of overall MSHR misses
162 system.cpu0.l1c.overall_mshr_misses::total 60377 # number of overall MSHR misses
163 system.cpu0.l1c.ReadReq_mshr_uncacheable::cpu0 9885 # number of ReadReq MSHR uncacheable
164 system.cpu0.l1c.ReadReq_mshr_uncacheable::total 9885 # number of ReadReq MSHR uncacheable
165 system.cpu0.l1c.WriteReq_mshr_uncacheable::cpu0 5567 # number of WriteReq MSHR uncacheable
166 system.cpu0.l1c.WriteReq_mshr_uncacheable::total 5567 # number of WriteReq MSHR uncacheable
167 system.cpu0.l1c.overall_mshr_uncacheable_misses::cpu0 15452 # number of overall MSHR uncacheable misses
168 system.cpu0.l1c.overall_mshr_uncacheable_misses::total 15452 # number of overall MSHR uncacheable misses
169 system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 566933975 # number of ReadReq MSHR miss cycles
170 system.cpu0.l1c.ReadReq_mshr_miss_latency::total 566933975 # number of ReadReq MSHR miss cycles
171 system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 698852184 # number of WriteReq MSHR miss cycles
172 system.cpu0.l1c.WriteReq_mshr_miss_latency::total 698852184 # number of WriteReq MSHR miss cycles
173 system.cpu0.l1c.demand_mshr_miss_latency::cpu0 1265786159 # number of demand (read+write) MSHR miss cycles
174 system.cpu0.l1c.demand_mshr_miss_latency::total 1265786159 # number of demand (read+write) MSHR miss cycles
175 system.cpu0.l1c.overall_mshr_miss_latency::cpu0 1265786159 # number of overall MSHR miss cycles
176 system.cpu0.l1c.overall_mshr_miss_latency::total 1265786159 # number of overall MSHR miss cycles
177 system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 722511018 # number of ReadReq MSHR uncacheable cycles
178 system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 722511018 # number of ReadReq MSHR uncacheable cycles
179 system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 853790554 # number of WriteReq MSHR uncacheable cycles
180 system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 853790554 # number of WriteReq MSHR uncacheable cycles
181 system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 1576301572 # number of overall MSHR uncacheable cycles
182 system.cpu0.l1c.overall_mshr_uncacheable_latency::total 1576301572 # number of overall MSHR uncacheable cycles
183 system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.804260 # mshr miss rate for ReadReq accesses
184 system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.804260 # mshr miss rate for ReadReq accesses
185 system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.953633 # mshr miss rate for WriteReq accesses
186 system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.953633 # mshr miss rate for WriteReq accesses
187 system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.857421 # mshr miss rate for demand accesses
188 system.cpu0.l1c.demand_mshr_miss_rate::total 0.857421 # mshr miss rate for demand accesses
189 system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.857421 # mshr miss rate for overall accesses
190 system.cpu0.l1c.overall_mshr_miss_rate::total 0.857421 # mshr miss rate for overall accesses
191 system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 15541.805335 # average ReadReq mshr miss latency
192 system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 15541.805335 # average ReadReq mshr miss latency
193 system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 29241.900665 # average WriteReq mshr miss latency
194 system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 29241.900665 # average WriteReq mshr miss latency
195 system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 20964.707736 # average overall mshr miss latency
196 system.cpu0.l1c.demand_avg_mshr_miss_latency::total 20964.707736 # average overall mshr miss latency
197 system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 20964.707736 # average overall mshr miss latency
198 system.cpu0.l1c.overall_avg_mshr_miss_latency::total 20964.707736 # average overall mshr miss latency
199 system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 73091.655842 # average ReadReq mshr uncacheable latency
200 system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total 73091.655842 # average ReadReq mshr uncacheable latency
201 system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 153366.365008 # average WriteReq mshr uncacheable latency
202 system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total 153366.365008 # average WriteReq mshr uncacheable latency
203 system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 102012.786177 # average overall mshr uncacheable latency
204 system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total 102012.786177 # average overall mshr uncacheable latency
205 system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
206 system.cpu1.num_reads 98929 # number of read accesses completed
207 system.cpu1.num_writes 55238 # number of write accesses completed
208 system.cpu1.l1c.tags.replacements 22532 # number of replacements
209 system.cpu1.l1c.tags.tagsinuse 392.132482 # Cycle average of tags in use
210 system.cpu1.l1c.tags.total_refs 13440 # Total number of references to valid blocks.
211 system.cpu1.l1c.tags.sampled_refs 22931 # Sample count of references to valid blocks.
212 system.cpu1.l1c.tags.avg_refs 0.586106 # Average number of references to valid blocks.
213 system.cpu1.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
214 system.cpu1.l1c.tags.occ_blocks::cpu1 392.132482 # Average occupied blocks per requestor
215 system.cpu1.l1c.tags.occ_percent::cpu1 0.765884 # Average percentage of cache occupancy
216 system.cpu1.l1c.tags.occ_percent::total 0.765884 # Average percentage of cache occupancy
217 system.cpu1.l1c.tags.occ_task_id_blocks::1024 399 # Occupied blocks per task id
218 system.cpu1.l1c.tags.age_task_id_blocks_1024::0 387 # Occupied blocks per task id
219 system.cpu1.l1c.tags.age_task_id_blocks_1024::1 12 # Occupied blocks per task id
220 system.cpu1.l1c.tags.occ_task_id_percent::1024 0.779297 # Percentage of cache occupancy per task id
221 system.cpu1.l1c.tags.tag_accesses 338385 # Number of tag accesses
222 system.cpu1.l1c.tags.data_accesses 338385 # Number of data accesses
223 system.cpu1.l1c.ReadReq_hits::cpu1 8754 # number of ReadReq hits
224 system.cpu1.l1c.ReadReq_hits::total 8754 # number of ReadReq hits
225 system.cpu1.l1c.WriteReq_hits::cpu1 1152 # number of WriteReq hits
226 system.cpu1.l1c.WriteReq_hits::total 1152 # number of WriteReq hits
227 system.cpu1.l1c.demand_hits::cpu1 9906 # number of demand (read+write) hits
228 system.cpu1.l1c.demand_hits::total 9906 # number of demand (read+write) hits
229 system.cpu1.l1c.overall_hits::cpu1 9906 # number of overall hits
230 system.cpu1.l1c.overall_hits::total 9906 # number of overall hits
231 system.cpu1.l1c.ReadReq_misses::cpu1 36277 # number of ReadReq misses
232 system.cpu1.l1c.ReadReq_misses::total 36277 # number of ReadReq misses
233 system.cpu1.l1c.WriteReq_misses::cpu1 24198 # number of WriteReq misses
234 system.cpu1.l1c.WriteReq_misses::total 24198 # number of WriteReq misses
235 system.cpu1.l1c.demand_misses::cpu1 60475 # number of demand (read+write) misses
236 system.cpu1.l1c.demand_misses::total 60475 # number of demand (read+write) misses
237 system.cpu1.l1c.overall_misses::cpu1 60475 # number of overall misses
238 system.cpu1.l1c.overall_misses::total 60475 # number of overall misses
239 system.cpu1.l1c.ReadReq_miss_latency::cpu1 602891984 # number of ReadReq miss cycles
240 system.cpu1.l1c.ReadReq_miss_latency::total 602891984 # number of ReadReq miss cycles
241 system.cpu1.l1c.WriteReq_miss_latency::cpu1 733995398 # number of WriteReq miss cycles
242 system.cpu1.l1c.WriteReq_miss_latency::total 733995398 # number of WriteReq miss cycles
243 system.cpu1.l1c.demand_miss_latency::cpu1 1336887382 # number of demand (read+write) miss cycles
244 system.cpu1.l1c.demand_miss_latency::total 1336887382 # number of demand (read+write) miss cycles
245 system.cpu1.l1c.overall_miss_latency::cpu1 1336887382 # number of overall miss cycles
246 system.cpu1.l1c.overall_miss_latency::total 1336887382 # number of overall miss cycles
247 system.cpu1.l1c.ReadReq_accesses::cpu1 45031 # number of ReadReq accesses(hits+misses)
248 system.cpu1.l1c.ReadReq_accesses::total 45031 # number of ReadReq accesses(hits+misses)
249 system.cpu1.l1c.WriteReq_accesses::cpu1 25350 # number of WriteReq accesses(hits+misses)
250 system.cpu1.l1c.WriteReq_accesses::total 25350 # number of WriteReq accesses(hits+misses)
251 system.cpu1.l1c.demand_accesses::cpu1 70381 # number of demand (read+write) accesses
252 system.cpu1.l1c.demand_accesses::total 70381 # number of demand (read+write) accesses
253 system.cpu1.l1c.overall_accesses::cpu1 70381 # number of overall (read+write) accesses
254 system.cpu1.l1c.overall_accesses::total 70381 # number of overall (read+write) accesses
255 system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.805601 # miss rate for ReadReq accesses
256 system.cpu1.l1c.ReadReq_miss_rate::total 0.805601 # miss rate for ReadReq accesses
257 system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.954556 # miss rate for WriteReq accesses
258 system.cpu1.l1c.WriteReq_miss_rate::total 0.954556 # miss rate for WriteReq accesses
259 system.cpu1.l1c.demand_miss_rate::cpu1 0.859252 # miss rate for demand accesses
260 system.cpu1.l1c.demand_miss_rate::total 0.859252 # miss rate for demand accesses
261 system.cpu1.l1c.overall_miss_rate::cpu1 0.859252 # miss rate for overall accesses
262 system.cpu1.l1c.overall_miss_rate::total 0.859252 # miss rate for overall accesses
263 system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 16619.124624 # average ReadReq miss latency
264 system.cpu1.l1c.ReadReq_avg_miss_latency::total 16619.124624 # average ReadReq miss latency
265 system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 30332.895198 # average WriteReq miss latency
266 system.cpu1.l1c.WriteReq_avg_miss_latency::total 30332.895198 # average WriteReq miss latency
267 system.cpu1.l1c.demand_avg_miss_latency::cpu1 22106.446995 # average overall miss latency
268 system.cpu1.l1c.demand_avg_miss_latency::total 22106.446995 # average overall miss latency
269 system.cpu1.l1c.overall_avg_miss_latency::cpu1 22106.446995 # average overall miss latency
270 system.cpu1.l1c.overall_avg_miss_latency::total 22106.446995 # average overall miss latency
271 system.cpu1.l1c.blocked_cycles::no_mshrs 828861 # number of cycles access was blocked
272 system.cpu1.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
273 system.cpu1.l1c.blocked::no_mshrs 62856 # number of cycles access was blocked
274 system.cpu1.l1c.blocked::no_targets 0 # number of cycles access was blocked
275 system.cpu1.l1c.avg_blocked_cycles::no_mshrs 13.186665 # average number of cycles each access was blocked
276 system.cpu1.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
277 system.cpu1.l1c.fast_writes 0 # number of fast writes performed
278 system.cpu1.l1c.cache_copies 0 # number of cache copies performed
279 system.cpu1.l1c.writebacks::writebacks 9918 # number of writebacks
280 system.cpu1.l1c.writebacks::total 9918 # number of writebacks
281 system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36277 # number of ReadReq MSHR misses
282 system.cpu1.l1c.ReadReq_mshr_misses::total 36277 # number of ReadReq MSHR misses
283 system.cpu1.l1c.WriteReq_mshr_misses::cpu1 24198 # number of WriteReq MSHR misses
284 system.cpu1.l1c.WriteReq_mshr_misses::total 24198 # number of WriteReq MSHR misses
285 system.cpu1.l1c.demand_mshr_misses::cpu1 60475 # number of demand (read+write) MSHR misses
286 system.cpu1.l1c.demand_mshr_misses::total 60475 # number of demand (read+write) MSHR misses
287 system.cpu1.l1c.overall_mshr_misses::cpu1 60475 # number of overall MSHR misses
288 system.cpu1.l1c.overall_mshr_misses::total 60475 # number of overall MSHR misses
289 system.cpu1.l1c.ReadReq_mshr_uncacheable::cpu1 9741 # number of ReadReq MSHR uncacheable
290 system.cpu1.l1c.ReadReq_mshr_uncacheable::total 9741 # number of ReadReq MSHR uncacheable
291 system.cpu1.l1c.WriteReq_mshr_uncacheable::cpu1 5463 # number of WriteReq MSHR uncacheable
292 system.cpu1.l1c.WriteReq_mshr_uncacheable::total 5463 # number of WriteReq MSHR uncacheable
293 system.cpu1.l1c.overall_mshr_uncacheable_misses::cpu1 15204 # number of overall MSHR uncacheable misses
294 system.cpu1.l1c.overall_mshr_uncacheable_misses::total 15204 # number of overall MSHR uncacheable misses
295 system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 566614984 # number of ReadReq MSHR miss cycles
296 system.cpu1.l1c.ReadReq_mshr_miss_latency::total 566614984 # number of ReadReq MSHR miss cycles
297 system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 709800398 # number of WriteReq MSHR miss cycles
298 system.cpu1.l1c.WriteReq_mshr_miss_latency::total 709800398 # number of WriteReq MSHR miss cycles
299 system.cpu1.l1c.demand_mshr_miss_latency::cpu1 1276415382 # number of demand (read+write) MSHR miss cycles
300 system.cpu1.l1c.demand_mshr_miss_latency::total 1276415382 # number of demand (read+write) MSHR miss cycles
301 system.cpu1.l1c.overall_mshr_miss_latency::cpu1 1276415382 # number of overall MSHR miss cycles
302 system.cpu1.l1c.overall_mshr_miss_latency::total 1276415382 # number of overall MSHR miss cycles
303 system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 713705140 # number of ReadReq MSHR uncacheable cycles
304 system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 713705140 # number of ReadReq MSHR uncacheable cycles
305 system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 858653101 # number of WriteReq MSHR uncacheable cycles
306 system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 858653101 # number of WriteReq MSHR uncacheable cycles
307 system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 1572358241 # number of overall MSHR uncacheable cycles
308 system.cpu1.l1c.overall_mshr_uncacheable_latency::total 1572358241 # number of overall MSHR uncacheable cycles
309 system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.805601 # mshr miss rate for ReadReq accesses
310 system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.805601 # mshr miss rate for ReadReq accesses
311 system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.954556 # mshr miss rate for WriteReq accesses
312 system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.954556 # mshr miss rate for WriteReq accesses
313 system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.859252 # mshr miss rate for demand accesses
314 system.cpu1.l1c.demand_mshr_miss_rate::total 0.859252 # mshr miss rate for demand accesses
315 system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.859252 # mshr miss rate for overall accesses
316 system.cpu1.l1c.overall_mshr_miss_rate::total 0.859252 # mshr miss rate for overall accesses
317 system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 15619.124624 # average ReadReq mshr miss latency
318 system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 15619.124624 # average ReadReq mshr miss latency
319 system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 29333.019175 # average WriteReq mshr miss latency
320 system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 29333.019175 # average WriteReq mshr miss latency
321 system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 21106.496602 # average overall mshr miss latency
322 system.cpu1.l1c.demand_avg_mshr_miss_latency::total 21106.496602 # average overall mshr miss latency
323 system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 21106.496602 # average overall mshr miss latency
324 system.cpu1.l1c.overall_avg_mshr_miss_latency::total 21106.496602 # average overall mshr miss latency
325 system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 73268.159327 # average ReadReq mshr uncacheable latency
326 system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total 73268.159327 # average ReadReq mshr uncacheable latency
327 system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 157176.112209 # average WriteReq mshr uncacheable latency
328 system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total 157176.112209 # average WriteReq mshr uncacheable latency
329 system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 103417.406012 # average overall mshr uncacheable latency
330 system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total 103417.406012 # average overall mshr uncacheable latency
331 system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
332 system.cpu2.num_reads 99726 # number of read accesses completed
333 system.cpu2.num_writes 55227 # number of write accesses completed
334 system.cpu2.l1c.tags.replacements 22340 # number of replacements
335 system.cpu2.l1c.tags.tagsinuse 393.100704 # Cycle average of tags in use
336 system.cpu2.l1c.tags.total_refs 13463 # Total number of references to valid blocks.
337 system.cpu2.l1c.tags.sampled_refs 22750 # Sample count of references to valid blocks.
338 system.cpu2.l1c.tags.avg_refs 0.591780 # Average number of references to valid blocks.
339 system.cpu2.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
340 system.cpu2.l1c.tags.occ_blocks::cpu2 393.100704 # Average occupied blocks per requestor
341 system.cpu2.l1c.tags.occ_percent::cpu2 0.767775 # Average percentage of cache occupancy
342 system.cpu2.l1c.tags.occ_percent::total 0.767775 # Average percentage of cache occupancy
343 system.cpu2.l1c.tags.occ_task_id_blocks::1024 410 # Occupied blocks per task id
344 system.cpu2.l1c.tags.age_task_id_blocks_1024::0 400 # Occupied blocks per task id
345 system.cpu2.l1c.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id
346 system.cpu2.l1c.tags.occ_task_id_percent::1024 0.800781 # Percentage of cache occupancy per task id
347 system.cpu2.l1c.tags.tag_accesses 338035 # Number of tag accesses
348 system.cpu2.l1c.tags.data_accesses 338035 # Number of data accesses
349 system.cpu2.l1c.ReadReq_hits::cpu2 8657 # number of ReadReq hits
350 system.cpu2.l1c.ReadReq_hits::total 8657 # number of ReadReq hits
351 system.cpu2.l1c.WriteReq_hits::cpu2 1109 # number of WriteReq hits
352 system.cpu2.l1c.WriteReq_hits::total 1109 # number of WriteReq hits
353 system.cpu2.l1c.demand_hits::cpu2 9766 # number of demand (read+write) hits
354 system.cpu2.l1c.demand_hits::total 9766 # number of demand (read+write) hits
355 system.cpu2.l1c.overall_hits::cpu2 9766 # number of overall hits
356 system.cpu2.l1c.overall_hits::total 9766 # number of overall hits
357 system.cpu2.l1c.ReadReq_misses::cpu2 36622 # number of ReadReq misses
358 system.cpu2.l1c.ReadReq_misses::total 36622 # number of ReadReq misses
359 system.cpu2.l1c.WriteReq_misses::cpu2 23922 # number of WriteReq misses
360 system.cpu2.l1c.WriteReq_misses::total 23922 # number of WriteReq misses
361 system.cpu2.l1c.demand_misses::cpu2 60544 # number of demand (read+write) misses
362 system.cpu2.l1c.demand_misses::total 60544 # number of demand (read+write) misses
363 system.cpu2.l1c.overall_misses::cpu2 60544 # number of overall misses
364 system.cpu2.l1c.overall_misses::total 60544 # number of overall misses
365 system.cpu2.l1c.ReadReq_miss_latency::cpu2 606579368 # number of ReadReq miss cycles
366 system.cpu2.l1c.ReadReq_miss_latency::total 606579368 # number of ReadReq miss cycles
367 system.cpu2.l1c.WriteReq_miss_latency::cpu2 739451035 # number of WriteReq miss cycles
368 system.cpu2.l1c.WriteReq_miss_latency::total 739451035 # number of WriteReq miss cycles
369 system.cpu2.l1c.demand_miss_latency::cpu2 1346030403 # number of demand (read+write) miss cycles
370 system.cpu2.l1c.demand_miss_latency::total 1346030403 # number of demand (read+write) miss cycles
371 system.cpu2.l1c.overall_miss_latency::cpu2 1346030403 # number of overall miss cycles
372 system.cpu2.l1c.overall_miss_latency::total 1346030403 # number of overall miss cycles
373 system.cpu2.l1c.ReadReq_accesses::cpu2 45279 # number of ReadReq accesses(hits+misses)
374 system.cpu2.l1c.ReadReq_accesses::total 45279 # number of ReadReq accesses(hits+misses)
375 system.cpu2.l1c.WriteReq_accesses::cpu2 25031 # number of WriteReq accesses(hits+misses)
376 system.cpu2.l1c.WriteReq_accesses::total 25031 # number of WriteReq accesses(hits+misses)
377 system.cpu2.l1c.demand_accesses::cpu2 70310 # number of demand (read+write) accesses
378 system.cpu2.l1c.demand_accesses::total 70310 # number of demand (read+write) accesses
379 system.cpu2.l1c.overall_accesses::cpu2 70310 # number of overall (read+write) accesses
380 system.cpu2.l1c.overall_accesses::total 70310 # number of overall (read+write) accesses
381 system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.808808 # miss rate for ReadReq accesses
382 system.cpu2.l1c.ReadReq_miss_rate::total 0.808808 # miss rate for ReadReq accesses
383 system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.955695 # miss rate for WriteReq accesses
384 system.cpu2.l1c.WriteReq_miss_rate::total 0.955695 # miss rate for WriteReq accesses
385 system.cpu2.l1c.demand_miss_rate::cpu2 0.861101 # miss rate for demand accesses
386 system.cpu2.l1c.demand_miss_rate::total 0.861101 # miss rate for demand accesses
387 system.cpu2.l1c.overall_miss_rate::cpu2 0.861101 # miss rate for overall accesses
388 system.cpu2.l1c.overall_miss_rate::total 0.861101 # miss rate for overall accesses
389 system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 16563.250724 # average ReadReq miss latency
390 system.cpu2.l1c.ReadReq_avg_miss_latency::total 16563.250724 # average ReadReq miss latency
391 system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 30910.920283 # average WriteReq miss latency
392 system.cpu2.l1c.WriteReq_avg_miss_latency::total 30910.920283 # average WriteReq miss latency
393 system.cpu2.l1c.demand_avg_miss_latency::cpu2 22232.267491 # average overall miss latency
394 system.cpu2.l1c.demand_avg_miss_latency::total 22232.267491 # average overall miss latency
395 system.cpu2.l1c.overall_avg_miss_latency::cpu2 22232.267491 # average overall miss latency
396 system.cpu2.l1c.overall_avg_miss_latency::total 22232.267491 # average overall miss latency
397 system.cpu2.l1c.blocked_cycles::no_mshrs 834628 # number of cycles access was blocked
398 system.cpu2.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
399 system.cpu2.l1c.blocked::no_mshrs 63193 # number of cycles access was blocked
400 system.cpu2.l1c.blocked::no_targets 0 # number of cycles access was blocked
401 system.cpu2.l1c.avg_blocked_cycles::no_mshrs 13.207602 # average number of cycles each access was blocked
402 system.cpu2.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
403 system.cpu2.l1c.fast_writes 0 # number of fast writes performed
404 system.cpu2.l1c.cache_copies 0 # number of cache copies performed
405 system.cpu2.l1c.writebacks::writebacks 9768 # number of writebacks
406 system.cpu2.l1c.writebacks::total 9768 # number of writebacks
407 system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36622 # number of ReadReq MSHR misses
408 system.cpu2.l1c.ReadReq_mshr_misses::total 36622 # number of ReadReq MSHR misses
409 system.cpu2.l1c.WriteReq_mshr_misses::cpu2 23922 # number of WriteReq MSHR misses
410 system.cpu2.l1c.WriteReq_mshr_misses::total 23922 # number of WriteReq MSHR misses
411 system.cpu2.l1c.demand_mshr_misses::cpu2 60544 # number of demand (read+write) MSHR misses
412 system.cpu2.l1c.demand_mshr_misses::total 60544 # number of demand (read+write) MSHR misses
413 system.cpu2.l1c.overall_mshr_misses::cpu2 60544 # number of overall MSHR misses
414 system.cpu2.l1c.overall_mshr_misses::total 60544 # number of overall MSHR misses
415 system.cpu2.l1c.ReadReq_mshr_uncacheable::cpu2 9774 # number of ReadReq MSHR uncacheable
416 system.cpu2.l1c.ReadReq_mshr_uncacheable::total 9774 # number of ReadReq MSHR uncacheable
417 system.cpu2.l1c.WriteReq_mshr_uncacheable::cpu2 5417 # number of WriteReq MSHR uncacheable
418 system.cpu2.l1c.WriteReq_mshr_uncacheable::total 5417 # number of WriteReq MSHR uncacheable
419 system.cpu2.l1c.overall_mshr_uncacheable_misses::cpu2 15191 # number of overall MSHR uncacheable misses
420 system.cpu2.l1c.overall_mshr_uncacheable_misses::total 15191 # number of overall MSHR uncacheable misses
421 system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 569957368 # number of ReadReq MSHR miss cycles
422 system.cpu2.l1c.ReadReq_mshr_miss_latency::total 569957368 # number of ReadReq MSHR miss cycles
423 system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 715531035 # number of WriteReq MSHR miss cycles
424 system.cpu2.l1c.WriteReq_mshr_miss_latency::total 715531035 # number of WriteReq MSHR miss cycles
425 system.cpu2.l1c.demand_mshr_miss_latency::cpu2 1285488403 # number of demand (read+write) MSHR miss cycles
426 system.cpu2.l1c.demand_mshr_miss_latency::total 1285488403 # number of demand (read+write) MSHR miss cycles
427 system.cpu2.l1c.overall_mshr_miss_latency::cpu2 1285488403 # number of overall MSHR miss cycles
428 system.cpu2.l1c.overall_mshr_miss_latency::total 1285488403 # number of overall MSHR miss cycles
429 system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 714145091 # number of ReadReq MSHR uncacheable cycles
430 system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 714145091 # number of ReadReq MSHR uncacheable cycles
431 system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 834952155 # number of WriteReq MSHR uncacheable cycles
432 system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 834952155 # number of WriteReq MSHR uncacheable cycles
433 system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 1549097246 # number of overall MSHR uncacheable cycles
434 system.cpu2.l1c.overall_mshr_uncacheable_latency::total 1549097246 # number of overall MSHR uncacheable cycles
435 system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.808808 # mshr miss rate for ReadReq accesses
436 system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.808808 # mshr miss rate for ReadReq accesses
437 system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.955695 # mshr miss rate for WriteReq accesses
438 system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.955695 # mshr miss rate for WriteReq accesses
439 system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.861101 # mshr miss rate for demand accesses
440 system.cpu2.l1c.demand_mshr_miss_rate::total 0.861101 # mshr miss rate for demand accesses
441 system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.861101 # mshr miss rate for overall accesses
442 system.cpu2.l1c.overall_mshr_miss_rate::total 0.861101 # mshr miss rate for overall accesses
443 system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 15563.250724 # average ReadReq mshr miss latency
444 system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 15563.250724 # average ReadReq mshr miss latency
445 system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 29911.003888 # average WriteReq mshr miss latency
446 system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 29911.003888 # average WriteReq mshr miss latency
447 system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 21232.300525 # average overall mshr miss latency
448 system.cpu2.l1c.demand_avg_mshr_miss_latency::total 21232.300525 # average overall mshr miss latency
449 system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 21232.300525 # average overall mshr miss latency
450 system.cpu2.l1c.overall_avg_mshr_miss_latency::total 21232.300525 # average overall mshr miss latency
451 system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 73065.796092 # average ReadReq mshr uncacheable latency
452 system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total 73065.796092 # average ReadReq mshr uncacheable latency
453 system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 154135.527968 # average WriteReq mshr uncacheable latency
454 system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total 154135.527968 # average WriteReq mshr uncacheable latency
455 system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 101974.672240 # average overall mshr uncacheable latency
456 system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total 101974.672240 # average overall mshr uncacheable latency
457 system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
458 system.cpu3.num_reads 99494 # number of read accesses completed
459 system.cpu3.num_writes 54686 # number of write accesses completed
460 system.cpu3.l1c.tags.replacements 22431 # number of replacements
461 system.cpu3.l1c.tags.tagsinuse 392.658378 # Cycle average of tags in use
462 system.cpu3.l1c.tags.total_refs 13393 # Total number of references to valid blocks.
463 system.cpu3.l1c.tags.sampled_refs 22832 # Sample count of references to valid blocks.
464 system.cpu3.l1c.tags.avg_refs 0.586589 # Average number of references to valid blocks.
465 system.cpu3.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
466 system.cpu3.l1c.tags.occ_blocks::cpu3 392.658378 # Average occupied blocks per requestor
467 system.cpu3.l1c.tags.occ_percent::cpu3 0.766911 # Average percentage of cache occupancy
468 system.cpu3.l1c.tags.occ_percent::total 0.766911 # Average percentage of cache occupancy
469 system.cpu3.l1c.tags.occ_task_id_blocks::1024 401 # Occupied blocks per task id
470 system.cpu3.l1c.tags.age_task_id_blocks_1024::0 389 # Occupied blocks per task id
471 system.cpu3.l1c.tags.age_task_id_blocks_1024::1 12 # Occupied blocks per task id
472 system.cpu3.l1c.tags.occ_task_id_percent::1024 0.783203 # Percentage of cache occupancy per task id
473 system.cpu3.l1c.tags.tag_accesses 337999 # Number of tag accesses
474 system.cpu3.l1c.tags.data_accesses 337999 # Number of data accesses
475 system.cpu3.l1c.ReadReq_hits::cpu3 8615 # number of ReadReq hits
476 system.cpu3.l1c.ReadReq_hits::total 8615 # number of ReadReq hits
477 system.cpu3.l1c.WriteReq_hits::cpu3 1106 # number of WriteReq hits
478 system.cpu3.l1c.WriteReq_hits::total 1106 # number of WriteReq hits
479 system.cpu3.l1c.demand_hits::cpu3 9721 # number of demand (read+write) hits
480 system.cpu3.l1c.demand_hits::total 9721 # number of demand (read+write) hits
481 system.cpu3.l1c.overall_hits::cpu3 9721 # number of overall hits
482 system.cpu3.l1c.overall_hits::total 9721 # number of overall hits
483 system.cpu3.l1c.ReadReq_misses::cpu3 36594 # number of ReadReq misses
484 system.cpu3.l1c.ReadReq_misses::total 36594 # number of ReadReq misses
485 system.cpu3.l1c.WriteReq_misses::cpu3 23974 # number of WriteReq misses
486 system.cpu3.l1c.WriteReq_misses::total 23974 # number of WriteReq misses
487 system.cpu3.l1c.demand_misses::cpu3 60568 # number of demand (read+write) misses
488 system.cpu3.l1c.demand_misses::total 60568 # number of demand (read+write) misses
489 system.cpu3.l1c.overall_misses::cpu3 60568 # number of overall misses
490 system.cpu3.l1c.overall_misses::total 60568 # number of overall misses
491 system.cpu3.l1c.ReadReq_miss_latency::cpu3 607642440 # number of ReadReq miss cycles
492 system.cpu3.l1c.ReadReq_miss_latency::total 607642440 # number of ReadReq miss cycles
493 system.cpu3.l1c.WriteReq_miss_latency::cpu3 730577546 # number of WriteReq miss cycles
494 system.cpu3.l1c.WriteReq_miss_latency::total 730577546 # number of WriteReq miss cycles
495 system.cpu3.l1c.demand_miss_latency::cpu3 1338219986 # number of demand (read+write) miss cycles
496 system.cpu3.l1c.demand_miss_latency::total 1338219986 # number of demand (read+write) miss cycles
497 system.cpu3.l1c.overall_miss_latency::cpu3 1338219986 # number of overall miss cycles
498 system.cpu3.l1c.overall_miss_latency::total 1338219986 # number of overall miss cycles
499 system.cpu3.l1c.ReadReq_accesses::cpu3 45209 # number of ReadReq accesses(hits+misses)
500 system.cpu3.l1c.ReadReq_accesses::total 45209 # number of ReadReq accesses(hits+misses)
501 system.cpu3.l1c.WriteReq_accesses::cpu3 25080 # number of WriteReq accesses(hits+misses)
502 system.cpu3.l1c.WriteReq_accesses::total 25080 # number of WriteReq accesses(hits+misses)
503 system.cpu3.l1c.demand_accesses::cpu3 70289 # number of demand (read+write) accesses
504 system.cpu3.l1c.demand_accesses::total 70289 # number of demand (read+write) accesses
505 system.cpu3.l1c.overall_accesses::cpu3 70289 # number of overall (read+write) accesses
506 system.cpu3.l1c.overall_accesses::total 70289 # number of overall (read+write) accesses
507 system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.809441 # miss rate for ReadReq accesses
508 system.cpu3.l1c.ReadReq_miss_rate::total 0.809441 # miss rate for ReadReq accesses
509 system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.955901 # miss rate for WriteReq accesses
510 system.cpu3.l1c.WriteReq_miss_rate::total 0.955901 # miss rate for WriteReq accesses
511 system.cpu3.l1c.demand_miss_rate::cpu3 0.861700 # miss rate for demand accesses
512 system.cpu3.l1c.demand_miss_rate::total 0.861700 # miss rate for demand accesses
513 system.cpu3.l1c.overall_miss_rate::cpu3 0.861700 # miss rate for overall accesses
514 system.cpu3.l1c.overall_miss_rate::total 0.861700 # miss rate for overall accesses
515 system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 16604.974586 # average ReadReq miss latency
516 system.cpu3.l1c.ReadReq_avg_miss_latency::total 16604.974586 # average ReadReq miss latency
517 system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 30473.744306 # average WriteReq miss latency
518 system.cpu3.l1c.WriteReq_avg_miss_latency::total 30473.744306 # average WriteReq miss latency
519 system.cpu3.l1c.demand_avg_miss_latency::cpu3 22094.505118 # average overall miss latency
520 system.cpu3.l1c.demand_avg_miss_latency::total 22094.505118 # average overall miss latency
521 system.cpu3.l1c.overall_avg_miss_latency::cpu3 22094.505118 # average overall miss latency
522 system.cpu3.l1c.overall_avg_miss_latency::total 22094.505118 # average overall miss latency
523 system.cpu3.l1c.blocked_cycles::no_mshrs 833585 # number of cycles access was blocked
524 system.cpu3.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
525 system.cpu3.l1c.blocked::no_mshrs 63208 # number of cycles access was blocked
526 system.cpu3.l1c.blocked::no_targets 0 # number of cycles access was blocked
527 system.cpu3.l1c.avg_blocked_cycles::no_mshrs 13.187967 # average number of cycles each access was blocked
528 system.cpu3.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
529 system.cpu3.l1c.fast_writes 0 # number of fast writes performed
530 system.cpu3.l1c.cache_copies 0 # number of cache copies performed
531 system.cpu3.l1c.writebacks::writebacks 9871 # number of writebacks
532 system.cpu3.l1c.writebacks::total 9871 # number of writebacks
533 system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36594 # number of ReadReq MSHR misses
534 system.cpu3.l1c.ReadReq_mshr_misses::total 36594 # number of ReadReq MSHR misses
535 system.cpu3.l1c.WriteReq_mshr_misses::cpu3 23974 # number of WriteReq MSHR misses
536 system.cpu3.l1c.WriteReq_mshr_misses::total 23974 # number of WriteReq MSHR misses
537 system.cpu3.l1c.demand_mshr_misses::cpu3 60568 # number of demand (read+write) MSHR misses
538 system.cpu3.l1c.demand_mshr_misses::total 60568 # number of demand (read+write) MSHR misses
539 system.cpu3.l1c.overall_mshr_misses::cpu3 60568 # number of overall MSHR misses
540 system.cpu3.l1c.overall_mshr_misses::total 60568 # number of overall MSHR misses
541 system.cpu3.l1c.ReadReq_mshr_uncacheable::cpu3 9814 # number of ReadReq MSHR uncacheable
542 system.cpu3.l1c.ReadReq_mshr_uncacheable::total 9814 # number of ReadReq MSHR uncacheable
543 system.cpu3.l1c.WriteReq_mshr_uncacheable::cpu3 5449 # number of WriteReq MSHR uncacheable
544 system.cpu3.l1c.WriteReq_mshr_uncacheable::total 5449 # number of WriteReq MSHR uncacheable
545 system.cpu3.l1c.overall_mshr_uncacheable_misses::cpu3 15263 # number of overall MSHR uncacheable misses
546 system.cpu3.l1c.overall_mshr_uncacheable_misses::total 15263 # number of overall MSHR uncacheable misses
547 system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 571049440 # number of ReadReq MSHR miss cycles
548 system.cpu3.l1c.ReadReq_mshr_miss_latency::total 571049440 # number of ReadReq MSHR miss cycles
549 system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 706605546 # number of WriteReq MSHR miss cycles
550 system.cpu3.l1c.WriteReq_mshr_miss_latency::total 706605546 # number of WriteReq MSHR miss cycles
551 system.cpu3.l1c.demand_mshr_miss_latency::cpu3 1277654986 # number of demand (read+write) MSHR miss cycles
552 system.cpu3.l1c.demand_mshr_miss_latency::total 1277654986 # number of demand (read+write) MSHR miss cycles
553 system.cpu3.l1c.overall_mshr_miss_latency::cpu3 1277654986 # number of overall MSHR miss cycles
554 system.cpu3.l1c.overall_mshr_miss_latency::total 1277654986 # number of overall MSHR miss cycles
555 system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 718813002 # number of ReadReq MSHR uncacheable cycles
556 system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 718813002 # number of ReadReq MSHR uncacheable cycles
557 system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 842609106 # number of WriteReq MSHR uncacheable cycles
558 system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 842609106 # number of WriteReq MSHR uncacheable cycles
559 system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 1561422108 # number of overall MSHR uncacheable cycles
560 system.cpu3.l1c.overall_mshr_uncacheable_latency::total 1561422108 # number of overall MSHR uncacheable cycles
561 system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.809441 # mshr miss rate for ReadReq accesses
562 system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.809441 # mshr miss rate for ReadReq accesses
563 system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.955901 # mshr miss rate for WriteReq accesses
564 system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.955901 # mshr miss rate for WriteReq accesses
565 system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.861700 # mshr miss rate for demand accesses
566 system.cpu3.l1c.demand_mshr_miss_rate::total 0.861700 # mshr miss rate for demand accesses
567 system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.861700 # mshr miss rate for overall accesses
568 system.cpu3.l1c.overall_mshr_miss_rate::total 0.861700 # mshr miss rate for overall accesses
569 system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 15605.001913 # average ReadReq mshr miss latency
570 system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 15605.001913 # average ReadReq mshr miss latency
571 system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 29473.827730 # average WriteReq mshr miss latency
572 system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 29473.827730 # average WriteReq mshr miss latency
573 system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 21094.554649 # average overall mshr miss latency
574 system.cpu3.l1c.demand_avg_mshr_miss_latency::total 21094.554649 # average overall mshr miss latency
575 system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 21094.554649 # average overall mshr miss latency
576 system.cpu3.l1c.overall_avg_mshr_miss_latency::total 21094.554649 # average overall mshr miss latency
577 system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 73243.631751 # average ReadReq mshr uncacheable latency
578 system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total 73243.631751 # average ReadReq mshr uncacheable latency
579 system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 154635.548908 # average WriteReq mshr uncacheable latency
580 system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total 154635.548908 # average WriteReq mshr uncacheable latency
581 system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 102301.127432 # average overall mshr uncacheable latency
582 system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total 102301.127432 # average overall mshr uncacheable latency
583 system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
584 system.cpu4.num_reads 99490 # number of read accesses completed
585 system.cpu4.num_writes 54928 # number of write accesses completed
586 system.cpu4.l1c.tags.replacements 22277 # number of replacements
587 system.cpu4.l1c.tags.tagsinuse 391.439470 # Cycle average of tags in use
588 system.cpu4.l1c.tags.total_refs 13388 # Total number of references to valid blocks.
589 system.cpu4.l1c.tags.sampled_refs 22671 # Sample count of references to valid blocks.
590 system.cpu4.l1c.tags.avg_refs 0.590534 # Average number of references to valid blocks.
591 system.cpu4.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
592 system.cpu4.l1c.tags.occ_blocks::cpu4 391.439470 # Average occupied blocks per requestor
593 system.cpu4.l1c.tags.occ_percent::cpu4 0.764530 # Average percentage of cache occupancy
594 system.cpu4.l1c.tags.occ_percent::total 0.764530 # Average percentage of cache occupancy
595 system.cpu4.l1c.tags.occ_task_id_blocks::1024 394 # Occupied blocks per task id
596 system.cpu4.l1c.tags.age_task_id_blocks_1024::0 372 # Occupied blocks per task id
597 system.cpu4.l1c.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id
598 system.cpu4.l1c.tags.occ_task_id_percent::1024 0.769531 # Percentage of cache occupancy per task id
599 system.cpu4.l1c.tags.tag_accesses 337649 # Number of tag accesses
600 system.cpu4.l1c.tags.data_accesses 337649 # Number of data accesses
601 system.cpu4.l1c.ReadReq_hits::cpu4 8692 # number of ReadReq hits
602 system.cpu4.l1c.ReadReq_hits::total 8692 # number of ReadReq hits
603 system.cpu4.l1c.WriteReq_hits::cpu4 1145 # number of WriteReq hits
604 system.cpu4.l1c.WriteReq_hits::total 1145 # number of WriteReq hits
605 system.cpu4.l1c.demand_hits::cpu4 9837 # number of demand (read+write) hits
606 system.cpu4.l1c.demand_hits::total 9837 # number of demand (read+write) hits
607 system.cpu4.l1c.overall_hits::cpu4 9837 # number of overall hits
608 system.cpu4.l1c.overall_hits::total 9837 # number of overall hits
609 system.cpu4.l1c.ReadReq_misses::cpu4 36462 # number of ReadReq misses
610 system.cpu4.l1c.ReadReq_misses::total 36462 # number of ReadReq misses
611 system.cpu4.l1c.WriteReq_misses::cpu4 23928 # number of WriteReq misses
612 system.cpu4.l1c.WriteReq_misses::total 23928 # number of WriteReq misses
613 system.cpu4.l1c.demand_misses::cpu4 60390 # number of demand (read+write) misses
614 system.cpu4.l1c.demand_misses::total 60390 # number of demand (read+write) misses
615 system.cpu4.l1c.overall_misses::cpu4 60390 # number of overall misses
616 system.cpu4.l1c.overall_misses::total 60390 # number of overall misses
617 system.cpu4.l1c.ReadReq_miss_latency::cpu4 604688688 # number of ReadReq miss cycles
618 system.cpu4.l1c.ReadReq_miss_latency::total 604688688 # number of ReadReq miss cycles
619 system.cpu4.l1c.WriteReq_miss_latency::cpu4 724847511 # number of WriteReq miss cycles
620 system.cpu4.l1c.WriteReq_miss_latency::total 724847511 # number of WriteReq miss cycles
621 system.cpu4.l1c.demand_miss_latency::cpu4 1329536199 # number of demand (read+write) miss cycles
622 system.cpu4.l1c.demand_miss_latency::total 1329536199 # number of demand (read+write) miss cycles
623 system.cpu4.l1c.overall_miss_latency::cpu4 1329536199 # number of overall miss cycles
624 system.cpu4.l1c.overall_miss_latency::total 1329536199 # number of overall miss cycles
625 system.cpu4.l1c.ReadReq_accesses::cpu4 45154 # number of ReadReq accesses(hits+misses)
626 system.cpu4.l1c.ReadReq_accesses::total 45154 # number of ReadReq accesses(hits+misses)
627 system.cpu4.l1c.WriteReq_accesses::cpu4 25073 # number of WriteReq accesses(hits+misses)
628 system.cpu4.l1c.WriteReq_accesses::total 25073 # number of WriteReq accesses(hits+misses)
629 system.cpu4.l1c.demand_accesses::cpu4 70227 # number of demand (read+write) accesses
630 system.cpu4.l1c.demand_accesses::total 70227 # number of demand (read+write) accesses
631 system.cpu4.l1c.overall_accesses::cpu4 70227 # number of overall (read+write) accesses
632 system.cpu4.l1c.overall_accesses::total 70227 # number of overall (read+write) accesses
633 system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.807503 # miss rate for ReadReq accesses
634 system.cpu4.l1c.ReadReq_miss_rate::total 0.807503 # miss rate for ReadReq accesses
635 system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.954333 # miss rate for WriteReq accesses
636 system.cpu4.l1c.WriteReq_miss_rate::total 0.954333 # miss rate for WriteReq accesses
637 system.cpu4.l1c.demand_miss_rate::cpu4 0.859926 # miss rate for demand accesses
638 system.cpu4.l1c.demand_miss_rate::total 0.859926 # miss rate for demand accesses
639 system.cpu4.l1c.overall_miss_rate::cpu4 0.859926 # miss rate for overall accesses
640 system.cpu4.l1c.overall_miss_rate::total 0.859926 # miss rate for overall accesses
641 system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 16584.078986 # average ReadReq miss latency
642 system.cpu4.l1c.ReadReq_avg_miss_latency::total 16584.078986 # average ReadReq miss latency
643 system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 30292.858200 # average WriteReq miss latency
644 system.cpu4.l1c.WriteReq_avg_miss_latency::total 30292.858200 # average WriteReq miss latency
645 system.cpu4.l1c.demand_avg_miss_latency::cpu4 22015.833731 # average overall miss latency
646 system.cpu4.l1c.demand_avg_miss_latency::total 22015.833731 # average overall miss latency
647 system.cpu4.l1c.overall_avg_miss_latency::cpu4 22015.833731 # average overall miss latency
648 system.cpu4.l1c.overall_avg_miss_latency::total 22015.833731 # average overall miss latency
649 system.cpu4.l1c.blocked_cycles::no_mshrs 834109 # number of cycles access was blocked
650 system.cpu4.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
651 system.cpu4.l1c.blocked::no_mshrs 63123 # number of cycles access was blocked
652 system.cpu4.l1c.blocked::no_targets 0 # number of cycles access was blocked
653 system.cpu4.l1c.avg_blocked_cycles::no_mshrs 13.214027 # average number of cycles each access was blocked
654 system.cpu4.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
655 system.cpu4.l1c.fast_writes 0 # number of fast writes performed
656 system.cpu4.l1c.cache_copies 0 # number of cache copies performed
657 system.cpu4.l1c.writebacks::writebacks 9949 # number of writebacks
658 system.cpu4.l1c.writebacks::total 9949 # number of writebacks
659 system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36462 # number of ReadReq MSHR misses
660 system.cpu4.l1c.ReadReq_mshr_misses::total 36462 # number of ReadReq MSHR misses
661 system.cpu4.l1c.WriteReq_mshr_misses::cpu4 23928 # number of WriteReq MSHR misses
662 system.cpu4.l1c.WriteReq_mshr_misses::total 23928 # number of WriteReq MSHR misses
663 system.cpu4.l1c.demand_mshr_misses::cpu4 60390 # number of demand (read+write) MSHR misses
664 system.cpu4.l1c.demand_mshr_misses::total 60390 # number of demand (read+write) MSHR misses
665 system.cpu4.l1c.overall_mshr_misses::cpu4 60390 # number of overall MSHR misses
666 system.cpu4.l1c.overall_mshr_misses::total 60390 # number of overall MSHR misses
667 system.cpu4.l1c.ReadReq_mshr_uncacheable::cpu4 9946 # number of ReadReq MSHR uncacheable
668 system.cpu4.l1c.ReadReq_mshr_uncacheable::total 9946 # number of ReadReq MSHR uncacheable
669 system.cpu4.l1c.WriteReq_mshr_uncacheable::cpu4 5329 # number of WriteReq MSHR uncacheable
670 system.cpu4.l1c.WriteReq_mshr_uncacheable::total 5329 # number of WriteReq MSHR uncacheable
671 system.cpu4.l1c.overall_mshr_uncacheable_misses::cpu4 15275 # number of overall MSHR uncacheable misses
672 system.cpu4.l1c.overall_mshr_uncacheable_misses::total 15275 # number of overall MSHR uncacheable misses
673 system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 568228688 # number of ReadReq MSHR miss cycles
674 system.cpu4.l1c.ReadReq_mshr_miss_latency::total 568228688 # number of ReadReq MSHR miss cycles
675 system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 700919511 # number of WriteReq MSHR miss cycles
676 system.cpu4.l1c.WriteReq_mshr_miss_latency::total 700919511 # number of WriteReq MSHR miss cycles
677 system.cpu4.l1c.demand_mshr_miss_latency::cpu4 1269148199 # number of demand (read+write) MSHR miss cycles
678 system.cpu4.l1c.demand_mshr_miss_latency::total 1269148199 # number of demand (read+write) MSHR miss cycles
679 system.cpu4.l1c.overall_mshr_miss_latency::cpu4 1269148199 # number of overall MSHR miss cycles
680 system.cpu4.l1c.overall_mshr_miss_latency::total 1269148199 # number of overall MSHR miss cycles
681 system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 727166434 # number of ReadReq MSHR uncacheable cycles
682 system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 727166434 # number of ReadReq MSHR uncacheable cycles
683 system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 837934166 # number of WriteReq MSHR uncacheable cycles
684 system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 837934166 # number of WriteReq MSHR uncacheable cycles
685 system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 1565100600 # number of overall MSHR uncacheable cycles
686 system.cpu4.l1c.overall_mshr_uncacheable_latency::total 1565100600 # number of overall MSHR uncacheable cycles
687 system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.807503 # mshr miss rate for ReadReq accesses
688 system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.807503 # mshr miss rate for ReadReq accesses
689 system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.954333 # mshr miss rate for WriteReq accesses
690 system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.954333 # mshr miss rate for WriteReq accesses
691 system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.859926 # mshr miss rate for demand accesses
692 system.cpu4.l1c.demand_mshr_miss_rate::total 0.859926 # mshr miss rate for demand accesses
693 system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.859926 # mshr miss rate for overall accesses
694 system.cpu4.l1c.overall_mshr_miss_rate::total 0.859926 # mshr miss rate for overall accesses
695 system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 15584.133838 # average ReadReq mshr miss latency
696 system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 15584.133838 # average ReadReq mshr miss latency
697 system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 29292.858200 # average WriteReq mshr miss latency
698 system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 29292.858200 # average WriteReq mshr miss latency
699 system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 21015.866849 # average overall mshr miss latency
700 system.cpu4.l1c.demand_avg_mshr_miss_latency::total 21015.866849 # average overall mshr miss latency
701 system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 21015.866849 # average overall mshr miss latency
702 system.cpu4.l1c.overall_avg_mshr_miss_latency::total 21015.866849 # average overall mshr miss latency
703 system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 73111.445204 # average ReadReq mshr uncacheable latency
704 system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total 73111.445204 # average ReadReq mshr uncacheable latency
705 system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 157240.413961 # average WriteReq mshr uncacheable latency
706 system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total 157240.413961 # average WriteReq mshr uncacheable latency
707 system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 102461.577741 # average overall mshr uncacheable latency
708 system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total 102461.577741 # average overall mshr uncacheable latency
709 system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
710 system.cpu5.num_reads 99495 # number of read accesses completed
711 system.cpu5.num_writes 55318 # number of write accesses completed
712 system.cpu5.l1c.tags.replacements 22409 # number of replacements
713 system.cpu5.l1c.tags.tagsinuse 392.682039 # Cycle average of tags in use
714 system.cpu5.l1c.tags.total_refs 13393 # Total number of references to valid blocks.
715 system.cpu5.l1c.tags.sampled_refs 22790 # Sample count of references to valid blocks.
716 system.cpu5.l1c.tags.avg_refs 0.587670 # Average number of references to valid blocks.
717 system.cpu5.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
718 system.cpu5.l1c.tags.occ_blocks::cpu5 392.682039 # Average occupied blocks per requestor
719 system.cpu5.l1c.tags.occ_percent::cpu5 0.766957 # Average percentage of cache occupancy
720 system.cpu5.l1c.tags.occ_percent::total 0.766957 # Average percentage of cache occupancy
721 system.cpu5.l1c.tags.occ_task_id_blocks::1024 381 # Occupied blocks per task id
722 system.cpu5.l1c.tags.age_task_id_blocks_1024::0 370 # Occupied blocks per task id
723 system.cpu5.l1c.tags.age_task_id_blocks_1024::1 11 # Occupied blocks per task id
724 system.cpu5.l1c.tags.occ_task_id_percent::1024 0.744141 # Percentage of cache occupancy per task id
725 system.cpu5.l1c.tags.tag_accesses 337688 # Number of tag accesses
726 system.cpu5.l1c.tags.data_accesses 337688 # Number of data accesses
727 system.cpu5.l1c.ReadReq_hits::cpu5 8637 # number of ReadReq hits
728 system.cpu5.l1c.ReadReq_hits::total 8637 # number of ReadReq hits
729 system.cpu5.l1c.WriteReq_hits::cpu5 1146 # number of WriteReq hits
730 system.cpu5.l1c.WriteReq_hits::total 1146 # number of WriteReq hits
731 system.cpu5.l1c.demand_hits::cpu5 9783 # number of demand (read+write) hits
732 system.cpu5.l1c.demand_hits::total 9783 # number of demand (read+write) hits
733 system.cpu5.l1c.overall_hits::cpu5 9783 # number of overall hits
734 system.cpu5.l1c.overall_hits::total 9783 # number of overall hits
735 system.cpu5.l1c.ReadReq_misses::cpu5 36329 # number of ReadReq misses
736 system.cpu5.l1c.ReadReq_misses::total 36329 # number of ReadReq misses
737 system.cpu5.l1c.WriteReq_misses::cpu5 24118 # number of WriteReq misses
738 system.cpu5.l1c.WriteReq_misses::total 24118 # number of WriteReq misses
739 system.cpu5.l1c.demand_misses::cpu5 60447 # number of demand (read+write) misses
740 system.cpu5.l1c.demand_misses::total 60447 # number of demand (read+write) misses
741 system.cpu5.l1c.overall_misses::cpu5 60447 # number of overall misses
742 system.cpu5.l1c.overall_misses::total 60447 # number of overall misses
743 system.cpu5.l1c.ReadReq_miss_latency::cpu5 601479868 # number of ReadReq miss cycles
744 system.cpu5.l1c.ReadReq_miss_latency::total 601479868 # number of ReadReq miss cycles
745 system.cpu5.l1c.WriteReq_miss_latency::cpu5 729882091 # number of WriteReq miss cycles
746 system.cpu5.l1c.WriteReq_miss_latency::total 729882091 # number of WriteReq miss cycles
747 system.cpu5.l1c.demand_miss_latency::cpu5 1331361959 # number of demand (read+write) miss cycles
748 system.cpu5.l1c.demand_miss_latency::total 1331361959 # number of demand (read+write) miss cycles
749 system.cpu5.l1c.overall_miss_latency::cpu5 1331361959 # number of overall miss cycles
750 system.cpu5.l1c.overall_miss_latency::total 1331361959 # number of overall miss cycles
751 system.cpu5.l1c.ReadReq_accesses::cpu5 44966 # number of ReadReq accesses(hits+misses)
752 system.cpu5.l1c.ReadReq_accesses::total 44966 # number of ReadReq accesses(hits+misses)
753 system.cpu5.l1c.WriteReq_accesses::cpu5 25264 # number of WriteReq accesses(hits+misses)
754 system.cpu5.l1c.WriteReq_accesses::total 25264 # number of WriteReq accesses(hits+misses)
755 system.cpu5.l1c.demand_accesses::cpu5 70230 # number of demand (read+write) accesses
756 system.cpu5.l1c.demand_accesses::total 70230 # number of demand (read+write) accesses
757 system.cpu5.l1c.overall_accesses::cpu5 70230 # number of overall (read+write) accesses
758 system.cpu5.l1c.overall_accesses::total 70230 # number of overall (read+write) accesses
759 system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.807922 # miss rate for ReadReq accesses
760 system.cpu5.l1c.ReadReq_miss_rate::total 0.807922 # miss rate for ReadReq accesses
761 system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.954639 # miss rate for WriteReq accesses
762 system.cpu5.l1c.WriteReq_miss_rate::total 0.954639 # miss rate for WriteReq accesses
763 system.cpu5.l1c.demand_miss_rate::cpu5 0.860701 # miss rate for demand accesses
764 system.cpu5.l1c.demand_miss_rate::total 0.860701 # miss rate for demand accesses
765 system.cpu5.l1c.overall_miss_rate::cpu5 0.860701 # miss rate for overall accesses
766 system.cpu5.l1c.overall_miss_rate::total 0.860701 # miss rate for overall accesses
767 system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 16556.466404 # average ReadReq miss latency
768 system.cpu5.l1c.ReadReq_avg_miss_latency::total 16556.466404 # average ReadReq miss latency
769 system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 30262.960901 # average WriteReq miss latency
770 system.cpu5.l1c.WriteReq_avg_miss_latency::total 30262.960901 # average WriteReq miss latency
771 system.cpu5.l1c.demand_avg_miss_latency::cpu5 22025.277665 # average overall miss latency
772 system.cpu5.l1c.demand_avg_miss_latency::total 22025.277665 # average overall miss latency
773 system.cpu5.l1c.overall_avg_miss_latency::cpu5 22025.277665 # average overall miss latency
774 system.cpu5.l1c.overall_avg_miss_latency::total 22025.277665 # average overall miss latency
775 system.cpu5.l1c.blocked_cycles::no_mshrs 826632 # number of cycles access was blocked
776 system.cpu5.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
777 system.cpu5.l1c.blocked::no_mshrs 62727 # number of cycles access was blocked
778 system.cpu5.l1c.blocked::no_targets 0 # number of cycles access was blocked
779 system.cpu5.l1c.avg_blocked_cycles::no_mshrs 13.178249 # average number of cycles each access was blocked
780 system.cpu5.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
781 system.cpu5.l1c.fast_writes 0 # number of fast writes performed
782 system.cpu5.l1c.cache_copies 0 # number of cache copies performed
783 system.cpu5.l1c.writebacks::writebacks 9995 # number of writebacks
784 system.cpu5.l1c.writebacks::total 9995 # number of writebacks
785 system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36329 # number of ReadReq MSHR misses
786 system.cpu5.l1c.ReadReq_mshr_misses::total 36329 # number of ReadReq MSHR misses
787 system.cpu5.l1c.WriteReq_mshr_misses::cpu5 24118 # number of WriteReq MSHR misses
788 system.cpu5.l1c.WriteReq_mshr_misses::total 24118 # number of WriteReq MSHR misses
789 system.cpu5.l1c.demand_mshr_misses::cpu5 60447 # number of demand (read+write) MSHR misses
790 system.cpu5.l1c.demand_mshr_misses::total 60447 # number of demand (read+write) MSHR misses
791 system.cpu5.l1c.overall_mshr_misses::cpu5 60447 # number of overall MSHR misses
792 system.cpu5.l1c.overall_mshr_misses::total 60447 # number of overall MSHR misses
793 system.cpu5.l1c.ReadReq_mshr_uncacheable::cpu5 9798 # number of ReadReq MSHR uncacheable
794 system.cpu5.l1c.ReadReq_mshr_uncacheable::total 9798 # number of ReadReq MSHR uncacheable
795 system.cpu5.l1c.WriteReq_mshr_uncacheable::cpu5 5473 # number of WriteReq MSHR uncacheable
796 system.cpu5.l1c.WriteReq_mshr_uncacheable::total 5473 # number of WriteReq MSHR uncacheable
797 system.cpu5.l1c.overall_mshr_uncacheable_misses::cpu5 15271 # number of overall MSHR uncacheable misses
798 system.cpu5.l1c.overall_mshr_uncacheable_misses::total 15271 # number of overall MSHR uncacheable misses
799 system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 565152868 # number of ReadReq MSHR miss cycles
800 system.cpu5.l1c.ReadReq_mshr_miss_latency::total 565152868 # number of ReadReq MSHR miss cycles
801 system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 705764091 # number of WriteReq MSHR miss cycles
802 system.cpu5.l1c.WriteReq_mshr_miss_latency::total 705764091 # number of WriteReq MSHR miss cycles
803 system.cpu5.l1c.demand_mshr_miss_latency::cpu5 1270916959 # number of demand (read+write) MSHR miss cycles
804 system.cpu5.l1c.demand_mshr_miss_latency::total 1270916959 # number of demand (read+write) MSHR miss cycles
805 system.cpu5.l1c.overall_mshr_miss_latency::cpu5 1270916959 # number of overall MSHR miss cycles
806 system.cpu5.l1c.overall_mshr_miss_latency::total 1270916959 # number of overall MSHR miss cycles
807 system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 717311081 # number of ReadReq MSHR uncacheable cycles
808 system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 717311081 # number of ReadReq MSHR uncacheable cycles
809 system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 861132955 # number of WriteReq MSHR uncacheable cycles
810 system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 861132955 # number of WriteReq MSHR uncacheable cycles
811 system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 1578444036 # number of overall MSHR uncacheable cycles
812 system.cpu5.l1c.overall_mshr_uncacheable_latency::total 1578444036 # number of overall MSHR uncacheable cycles
813 system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.807922 # mshr miss rate for ReadReq accesses
814 system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.807922 # mshr miss rate for ReadReq accesses
815 system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.954639 # mshr miss rate for WriteReq accesses
816 system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.954639 # mshr miss rate for WriteReq accesses
817 system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.860701 # mshr miss rate for demand accesses
818 system.cpu5.l1c.demand_mshr_miss_rate::total 0.860701 # mshr miss rate for demand accesses
819 system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.860701 # mshr miss rate for overall accesses
820 system.cpu5.l1c.overall_mshr_miss_rate::total 0.860701 # mshr miss rate for overall accesses
821 system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 15556.521457 # average ReadReq mshr miss latency
822 system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 15556.521457 # average ReadReq mshr miss latency
823 system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 29262.960901 # average WriteReq mshr miss latency
824 system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 29262.960901 # average WriteReq mshr miss latency
825 system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 21025.310752 # average overall mshr miss latency
826 system.cpu5.l1c.demand_avg_mshr_miss_latency::total 21025.310752 # average overall mshr miss latency
827 system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 21025.310752 # average overall mshr miss latency
828 system.cpu5.l1c.overall_avg_mshr_miss_latency::total 21025.310752 # average overall mshr miss latency
829 system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 73209.949071 # average ReadReq mshr uncacheable latency
830 system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total 73209.949071 # average ReadReq mshr uncacheable latency
831 system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 157342.034533 # average WriteReq mshr uncacheable latency
832 system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total 157342.034533 # average WriteReq mshr uncacheable latency
833 system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 103362.192129 # average overall mshr uncacheable latency
834 system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total 103362.192129 # average overall mshr uncacheable latency
835 system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
836 system.cpu6.num_reads 100000 # number of read accesses completed
837 system.cpu6.num_writes 55059 # number of write accesses completed
838 system.cpu6.l1c.tags.replacements 22318 # number of replacements
839 system.cpu6.l1c.tags.tagsinuse 390.741535 # Cycle average of tags in use
840 system.cpu6.l1c.tags.total_refs 13451 # Total number of references to valid blocks.
841 system.cpu6.l1c.tags.sampled_refs 22720 # Sample count of references to valid blocks.
842 system.cpu6.l1c.tags.avg_refs 0.592033 # Average number of references to valid blocks.
843 system.cpu6.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
844 system.cpu6.l1c.tags.occ_blocks::cpu6 390.741535 # Average occupied blocks per requestor
845 system.cpu6.l1c.tags.occ_percent::cpu6 0.763167 # Average percentage of cache occupancy
846 system.cpu6.l1c.tags.occ_percent::total 0.763167 # Average percentage of cache occupancy
847 system.cpu6.l1c.tags.occ_task_id_blocks::1024 402 # Occupied blocks per task id
848 system.cpu6.l1c.tags.age_task_id_blocks_1024::0 388 # Occupied blocks per task id
849 system.cpu6.l1c.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id
850 system.cpu6.l1c.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id
851 system.cpu6.l1c.tags.tag_accesses 338536 # Number of tag accesses
852 system.cpu6.l1c.tags.data_accesses 338536 # Number of data accesses
853 system.cpu6.l1c.ReadReq_hits::cpu6 8731 # number of ReadReq hits
854 system.cpu6.l1c.ReadReq_hits::total 8731 # number of ReadReq hits
855 system.cpu6.l1c.WriteReq_hits::cpu6 1150 # number of WriteReq hits
856 system.cpu6.l1c.WriteReq_hits::total 1150 # number of WriteReq hits
857 system.cpu6.l1c.demand_hits::cpu6 9881 # number of demand (read+write) hits
858 system.cpu6.l1c.demand_hits::total 9881 # number of demand (read+write) hits
859 system.cpu6.l1c.overall_hits::cpu6 9881 # number of overall hits
860 system.cpu6.l1c.overall_hits::total 9881 # number of overall hits
861 system.cpu6.l1c.ReadReq_misses::cpu6 36733 # number of ReadReq misses
862 system.cpu6.l1c.ReadReq_misses::total 36733 # number of ReadReq misses
863 system.cpu6.l1c.WriteReq_misses::cpu6 23795 # number of WriteReq misses
864 system.cpu6.l1c.WriteReq_misses::total 23795 # number of WriteReq misses
865 system.cpu6.l1c.demand_misses::cpu6 60528 # number of demand (read+write) misses
866 system.cpu6.l1c.demand_misses::total 60528 # number of demand (read+write) misses
867 system.cpu6.l1c.overall_misses::cpu6 60528 # number of overall misses
868 system.cpu6.l1c.overall_misses::total 60528 # number of overall misses
869 system.cpu6.l1c.ReadReq_miss_latency::cpu6 609896687 # number of ReadReq miss cycles
870 system.cpu6.l1c.ReadReq_miss_latency::total 609896687 # number of ReadReq miss cycles
871 system.cpu6.l1c.WriteReq_miss_latency::cpu6 716784676 # number of WriteReq miss cycles
872 system.cpu6.l1c.WriteReq_miss_latency::total 716784676 # number of WriteReq miss cycles
873 system.cpu6.l1c.demand_miss_latency::cpu6 1326681363 # number of demand (read+write) miss cycles
874 system.cpu6.l1c.demand_miss_latency::total 1326681363 # number of demand (read+write) miss cycles
875 system.cpu6.l1c.overall_miss_latency::cpu6 1326681363 # number of overall miss cycles
876 system.cpu6.l1c.overall_miss_latency::total 1326681363 # number of overall miss cycles
877 system.cpu6.l1c.ReadReq_accesses::cpu6 45464 # number of ReadReq accesses(hits+misses)
878 system.cpu6.l1c.ReadReq_accesses::total 45464 # number of ReadReq accesses(hits+misses)
879 system.cpu6.l1c.WriteReq_accesses::cpu6 24945 # number of WriteReq accesses(hits+misses)
880 system.cpu6.l1c.WriteReq_accesses::total 24945 # number of WriteReq accesses(hits+misses)
881 system.cpu6.l1c.demand_accesses::cpu6 70409 # number of demand (read+write) accesses
882 system.cpu6.l1c.demand_accesses::total 70409 # number of demand (read+write) accesses
883 system.cpu6.l1c.overall_accesses::cpu6 70409 # number of overall (read+write) accesses
884 system.cpu6.l1c.overall_accesses::total 70409 # number of overall (read+write) accesses
885 system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.807958 # miss rate for ReadReq accesses
886 system.cpu6.l1c.ReadReq_miss_rate::total 0.807958 # miss rate for ReadReq accesses
887 system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.953899 # miss rate for WriteReq accesses
888 system.cpu6.l1c.WriteReq_miss_rate::total 0.953899 # miss rate for WriteReq accesses
889 system.cpu6.l1c.demand_miss_rate::cpu6 0.859663 # miss rate for demand accesses
890 system.cpu6.l1c.demand_miss_rate::total 0.859663 # miss rate for demand accesses
891 system.cpu6.l1c.overall_miss_rate::cpu6 0.859663 # miss rate for overall accesses
892 system.cpu6.l1c.overall_miss_rate::total 0.859663 # miss rate for overall accesses
893 system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 16603.508752 # average ReadReq miss latency
894 system.cpu6.l1c.ReadReq_avg_miss_latency::total 16603.508752 # average ReadReq miss latency
895 system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 30123.331624 # average WriteReq miss latency
896 system.cpu6.l1c.WriteReq_avg_miss_latency::total 30123.331624 # average WriteReq miss latency
897 system.cpu6.l1c.demand_avg_miss_latency::cpu6 21918.473483 # average overall miss latency
898 system.cpu6.l1c.demand_avg_miss_latency::total 21918.473483 # average overall miss latency
899 system.cpu6.l1c.overall_avg_miss_latency::cpu6 21918.473483 # average overall miss latency
900 system.cpu6.l1c.overall_avg_miss_latency::total 21918.473483 # average overall miss latency
901 system.cpu6.l1c.blocked_cycles::no_mshrs 822803 # number of cycles access was blocked
902 system.cpu6.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
903 system.cpu6.l1c.blocked::no_mshrs 62827 # number of cycles access was blocked
904 system.cpu6.l1c.blocked::no_targets 0 # number of cycles access was blocked
905 system.cpu6.l1c.avg_blocked_cycles::no_mshrs 13.096328 # average number of cycles each access was blocked
906 system.cpu6.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
907 system.cpu6.l1c.fast_writes 0 # number of fast writes performed
908 system.cpu6.l1c.cache_copies 0 # number of cache copies performed
909 system.cpu6.l1c.writebacks::writebacks 9777 # number of writebacks
910 system.cpu6.l1c.writebacks::total 9777 # number of writebacks
911 system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36733 # number of ReadReq MSHR misses
912 system.cpu6.l1c.ReadReq_mshr_misses::total 36733 # number of ReadReq MSHR misses
913 system.cpu6.l1c.WriteReq_mshr_misses::cpu6 23795 # number of WriteReq MSHR misses
914 system.cpu6.l1c.WriteReq_mshr_misses::total 23795 # number of WriteReq MSHR misses
915 system.cpu6.l1c.demand_mshr_misses::cpu6 60528 # number of demand (read+write) MSHR misses
916 system.cpu6.l1c.demand_mshr_misses::total 60528 # number of demand (read+write) MSHR misses
917 system.cpu6.l1c.overall_mshr_misses::cpu6 60528 # number of overall MSHR misses
918 system.cpu6.l1c.overall_mshr_misses::total 60528 # number of overall MSHR misses
919 system.cpu6.l1c.ReadReq_mshr_uncacheable::cpu6 9837 # number of ReadReq MSHR uncacheable
920 system.cpu6.l1c.ReadReq_mshr_uncacheable::total 9837 # number of ReadReq MSHR uncacheable
921 system.cpu6.l1c.WriteReq_mshr_uncacheable::cpu6 5532 # number of WriteReq MSHR uncacheable
922 system.cpu6.l1c.WriteReq_mshr_uncacheable::total 5532 # number of WriteReq MSHR uncacheable
923 system.cpu6.l1c.overall_mshr_uncacheable_misses::cpu6 15369 # number of overall MSHR uncacheable misses
924 system.cpu6.l1c.overall_mshr_uncacheable_misses::total 15369 # number of overall MSHR uncacheable misses
925 system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 573164687 # number of ReadReq MSHR miss cycles
926 system.cpu6.l1c.ReadReq_mshr_miss_latency::total 573164687 # number of ReadReq MSHR miss cycles
927 system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 692991676 # number of WriteReq MSHR miss cycles
928 system.cpu6.l1c.WriteReq_mshr_miss_latency::total 692991676 # number of WriteReq MSHR miss cycles
929 system.cpu6.l1c.demand_mshr_miss_latency::cpu6 1266156363 # number of demand (read+write) MSHR miss cycles
930 system.cpu6.l1c.demand_mshr_miss_latency::total 1266156363 # number of demand (read+write) MSHR miss cycles
931 system.cpu6.l1c.overall_mshr_miss_latency::cpu6 1266156363 # number of overall MSHR miss cycles
932 system.cpu6.l1c.overall_mshr_miss_latency::total 1266156363 # number of overall MSHR miss cycles
933 system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 718909036 # number of ReadReq MSHR uncacheable cycles
934 system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 718909036 # number of ReadReq MSHR uncacheable cycles
935 system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 867837123 # number of WriteReq MSHR uncacheable cycles
936 system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 867837123 # number of WriteReq MSHR uncacheable cycles
937 system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 1586746159 # number of overall MSHR uncacheable cycles
938 system.cpu6.l1c.overall_mshr_uncacheable_latency::total 1586746159 # number of overall MSHR uncacheable cycles
939 system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.807958 # mshr miss rate for ReadReq accesses
940 system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.807958 # mshr miss rate for ReadReq accesses
941 system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.953899 # mshr miss rate for WriteReq accesses
942 system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.953899 # mshr miss rate for WriteReq accesses
943 system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.859663 # mshr miss rate for demand accesses
944 system.cpu6.l1c.demand_mshr_miss_rate::total 0.859663 # mshr miss rate for demand accesses
945 system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.859663 # mshr miss rate for overall accesses
946 system.cpu6.l1c.overall_mshr_miss_rate::total 0.859663 # mshr miss rate for overall accesses
947 system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 15603.535976 # average ReadReq mshr miss latency
948 system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 15603.535976 # average ReadReq mshr miss latency
949 system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 29123.415676 # average WriteReq mshr miss latency
950 system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 29123.415676 # average WriteReq mshr miss latency
951 system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 20918.523047 # average overall mshr miss latency
952 system.cpu6.l1c.demand_avg_mshr_miss_latency::total 20918.523047 # average overall mshr miss latency
953 system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 20918.523047 # average overall mshr miss latency
954 system.cpu6.l1c.overall_avg_mshr_miss_latency::total 20918.523047 # average overall mshr miss latency
955 system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 73082.142523 # average ReadReq mshr uncacheable latency
956 system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total 73082.142523 # average ReadReq mshr uncacheable latency
957 system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 156875.835683 # average WriteReq mshr uncacheable latency
958 system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total 156875.835683 # average WriteReq mshr uncacheable latency
959 system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 103243.292277 # average overall mshr uncacheable latency
960 system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total 103243.292277 # average overall mshr uncacheable latency
961 system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
962 system.cpu7.num_reads 99734 # number of read accesses completed
963 system.cpu7.num_writes 54921 # number of write accesses completed
964 system.cpu7.l1c.tags.replacements 22329 # number of replacements
965 system.cpu7.l1c.tags.tagsinuse 392.290074 # Cycle average of tags in use
966 system.cpu7.l1c.tags.total_refs 13499 # Total number of references to valid blocks.
967 system.cpu7.l1c.tags.sampled_refs 22713 # Sample count of references to valid blocks.
968 system.cpu7.l1c.tags.avg_refs 0.594329 # Average number of references to valid blocks.
969 system.cpu7.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
970 system.cpu7.l1c.tags.occ_blocks::cpu7 392.290074 # Average occupied blocks per requestor
971 system.cpu7.l1c.tags.occ_percent::cpu7 0.766192 # Average percentage of cache occupancy
972 system.cpu7.l1c.tags.occ_percent::total 0.766192 # Average percentage of cache occupancy
973 system.cpu7.l1c.tags.occ_task_id_blocks::1024 384 # Occupied blocks per task id
974 system.cpu7.l1c.tags.age_task_id_blocks_1024::0 371 # Occupied blocks per task id
975 system.cpu7.l1c.tags.age_task_id_blocks_1024::1 13 # Occupied blocks per task id
976 system.cpu7.l1c.tags.occ_task_id_percent::1024 0.750000 # Percentage of cache occupancy per task id
977 system.cpu7.l1c.tags.tag_accesses 338596 # Number of tag accesses
978 system.cpu7.l1c.tags.data_accesses 338596 # Number of data accesses
979 system.cpu7.l1c.ReadReq_hits::cpu7 8795 # number of ReadReq hits
980 system.cpu7.l1c.ReadReq_hits::total 8795 # number of ReadReq hits
981 system.cpu7.l1c.WriteReq_hits::cpu7 1165 # number of WriteReq hits
982 system.cpu7.l1c.WriteReq_hits::total 1165 # number of WriteReq hits
983 system.cpu7.l1c.demand_hits::cpu7 9960 # number of demand (read+write) hits
984 system.cpu7.l1c.demand_hits::total 9960 # number of demand (read+write) hits
985 system.cpu7.l1c.overall_hits::cpu7 9960 # number of overall hits
986 system.cpu7.l1c.overall_hits::total 9960 # number of overall hits
987 system.cpu7.l1c.ReadReq_misses::cpu7 36684 # number of ReadReq misses
988 system.cpu7.l1c.ReadReq_misses::total 36684 # number of ReadReq misses
989 system.cpu7.l1c.WriteReq_misses::cpu7 23790 # number of WriteReq misses
990 system.cpu7.l1c.WriteReq_misses::total 23790 # number of WriteReq misses
991 system.cpu7.l1c.demand_misses::cpu7 60474 # number of demand (read+write) misses
992 system.cpu7.l1c.demand_misses::total 60474 # number of demand (read+write) misses
993 system.cpu7.l1c.overall_misses::cpu7 60474 # number of overall misses
994 system.cpu7.l1c.overall_misses::total 60474 # number of overall misses
995 system.cpu7.l1c.ReadReq_miss_latency::cpu7 611011013 # number of ReadReq miss cycles
996 system.cpu7.l1c.ReadReq_miss_latency::total 611011013 # number of ReadReq miss cycles
997 system.cpu7.l1c.WriteReq_miss_latency::cpu7 715403706 # number of WriteReq miss cycles
998 system.cpu7.l1c.WriteReq_miss_latency::total 715403706 # number of WriteReq miss cycles
999 system.cpu7.l1c.demand_miss_latency::cpu7 1326414719 # number of demand (read+write) miss cycles
1000 system.cpu7.l1c.demand_miss_latency::total 1326414719 # number of demand (read+write) miss cycles
1001 system.cpu7.l1c.overall_miss_latency::cpu7 1326414719 # number of overall miss cycles
1002 system.cpu7.l1c.overall_miss_latency::total 1326414719 # number of overall miss cycles
1003 system.cpu7.l1c.ReadReq_accesses::cpu7 45479 # number of ReadReq accesses(hits+misses)
1004 system.cpu7.l1c.ReadReq_accesses::total 45479 # number of ReadReq accesses(hits+misses)
1005 system.cpu7.l1c.WriteReq_accesses::cpu7 24955 # number of WriteReq accesses(hits+misses)
1006 system.cpu7.l1c.WriteReq_accesses::total 24955 # number of WriteReq accesses(hits+misses)
1007 system.cpu7.l1c.demand_accesses::cpu7 70434 # number of demand (read+write) accesses
1008 system.cpu7.l1c.demand_accesses::total 70434 # number of demand (read+write) accesses
1009 system.cpu7.l1c.overall_accesses::cpu7 70434 # number of overall (read+write) accesses
1010 system.cpu7.l1c.overall_accesses::total 70434 # number of overall (read+write) accesses
1011 system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.806614 # miss rate for ReadReq accesses
1012 system.cpu7.l1c.ReadReq_miss_rate::total 0.806614 # miss rate for ReadReq accesses
1013 system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.953316 # miss rate for WriteReq accesses
1014 system.cpu7.l1c.WriteReq_miss_rate::total 0.953316 # miss rate for WriteReq accesses
1015 system.cpu7.l1c.demand_miss_rate::cpu7 0.858591 # miss rate for demand accesses
1016 system.cpu7.l1c.demand_miss_rate::total 0.858591 # miss rate for demand accesses
1017 system.cpu7.l1c.overall_miss_rate::cpu7 0.858591 # miss rate for overall accesses
1018 system.cpu7.l1c.overall_miss_rate::total 0.858591 # miss rate for overall accesses
1019 system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 16656.062943 # average ReadReq miss latency
1020 system.cpu7.l1c.ReadReq_avg_miss_latency::total 16656.062943 # average ReadReq miss latency
1021 system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 30071.614376 # average WriteReq miss latency
1022 system.cpu7.l1c.WriteReq_avg_miss_latency::total 30071.614376 # average WriteReq miss latency
1023 system.cpu7.l1c.demand_avg_miss_latency::cpu7 21933.636257 # average overall miss latency
1024 system.cpu7.l1c.demand_avg_miss_latency::total 21933.636257 # average overall miss latency
1025 system.cpu7.l1c.overall_avg_miss_latency::cpu7 21933.636257 # average overall miss latency
1026 system.cpu7.l1c.overall_avg_miss_latency::total 21933.636257 # average overall miss latency
1027 system.cpu7.l1c.blocked_cycles::no_mshrs 829723 # number of cycles access was blocked
1028 system.cpu7.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
1029 system.cpu7.l1c.blocked::no_mshrs 63058 # number of cycles access was blocked
1030 system.cpu7.l1c.blocked::no_targets 0 # number of cycles access was blocked
1031 system.cpu7.l1c.avg_blocked_cycles::no_mshrs 13.158093 # average number of cycles each access was blocked
1032 system.cpu7.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1033 system.cpu7.l1c.fast_writes 0 # number of fast writes performed
1034 system.cpu7.l1c.cache_copies 0 # number of cache copies performed
1035 system.cpu7.l1c.writebacks::writebacks 9746 # number of writebacks
1036 system.cpu7.l1c.writebacks::total 9746 # number of writebacks
1037 system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36684 # number of ReadReq MSHR misses
1038 system.cpu7.l1c.ReadReq_mshr_misses::total 36684 # number of ReadReq MSHR misses
1039 system.cpu7.l1c.WriteReq_mshr_misses::cpu7 23790 # number of WriteReq MSHR misses
1040 system.cpu7.l1c.WriteReq_mshr_misses::total 23790 # number of WriteReq MSHR misses
1041 system.cpu7.l1c.demand_mshr_misses::cpu7 60474 # number of demand (read+write) MSHR misses
1042 system.cpu7.l1c.demand_mshr_misses::total 60474 # number of demand (read+write) MSHR misses
1043 system.cpu7.l1c.overall_mshr_misses::cpu7 60474 # number of overall MSHR misses
1044 system.cpu7.l1c.overall_mshr_misses::total 60474 # number of overall MSHR misses
1045 system.cpu7.l1c.ReadReq_mshr_uncacheable::cpu7 9918 # number of ReadReq MSHR uncacheable
1046 system.cpu7.l1c.ReadReq_mshr_uncacheable::total 9918 # number of ReadReq MSHR uncacheable
1047 system.cpu7.l1c.WriteReq_mshr_uncacheable::cpu7 5421 # number of WriteReq MSHR uncacheable
1048 system.cpu7.l1c.WriteReq_mshr_uncacheable::total 5421 # number of WriteReq MSHR uncacheable
1049 system.cpu7.l1c.overall_mshr_uncacheable_misses::cpu7 15339 # number of overall MSHR uncacheable misses
1050 system.cpu7.l1c.overall_mshr_uncacheable_misses::total 15339 # number of overall MSHR uncacheable misses
1051 system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 574327013 # number of ReadReq MSHR miss cycles
1052 system.cpu7.l1c.ReadReq_mshr_miss_latency::total 574327013 # number of ReadReq MSHR miss cycles
1053 system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 691615706 # number of WriteReq MSHR miss cycles
1054 system.cpu7.l1c.WriteReq_mshr_miss_latency::total 691615706 # number of WriteReq MSHR miss cycles
1055 system.cpu7.l1c.demand_mshr_miss_latency::cpu7 1265942719 # number of demand (read+write) MSHR miss cycles
1056 system.cpu7.l1c.demand_mshr_miss_latency::total 1265942719 # number of demand (read+write) MSHR miss cycles
1057 system.cpu7.l1c.overall_mshr_miss_latency::cpu7 1265942719 # number of overall MSHR miss cycles
1058 system.cpu7.l1c.overall_mshr_miss_latency::total 1265942719 # number of overall MSHR miss cycles
1059 system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 726668427 # number of ReadReq MSHR uncacheable cycles
1060 system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 726668427 # number of ReadReq MSHR uncacheable cycles
1061 system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 847371643 # number of WriteReq MSHR uncacheable cycles
1062 system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 847371643 # number of WriteReq MSHR uncacheable cycles
1063 system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 1574040070 # number of overall MSHR uncacheable cycles
1064 system.cpu7.l1c.overall_mshr_uncacheable_latency::total 1574040070 # number of overall MSHR uncacheable cycles
1065 system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.806614 # mshr miss rate for ReadReq accesses
1066 system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.806614 # mshr miss rate for ReadReq accesses
1067 system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.953316 # mshr miss rate for WriteReq accesses
1068 system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.953316 # mshr miss rate for WriteReq accesses
1069 system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.858591 # mshr miss rate for demand accesses
1070 system.cpu7.l1c.demand_mshr_miss_rate::total 0.858591 # mshr miss rate for demand accesses
1071 system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.858591 # mshr miss rate for overall accesses
1072 system.cpu7.l1c.overall_mshr_miss_rate::total 0.858591 # mshr miss rate for overall accesses
1073 system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 15656.062943 # average ReadReq mshr miss latency
1074 system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 15656.062943 # average ReadReq mshr miss latency
1075 system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 29071.698445 # average WriteReq mshr miss latency
1076 system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 29071.698445 # average WriteReq mshr miss latency
1077 system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 20933.669329 # average overall mshr miss latency
1078 system.cpu7.l1c.demand_avg_mshr_miss_latency::total 20933.669329 # average overall mshr miss latency
1079 system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 20933.669329 # average overall mshr miss latency
1080 system.cpu7.l1c.overall_avg_mshr_miss_latency::total 20933.669329 # average overall mshr miss latency
1081 system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 73267.637326 # average ReadReq mshr uncacheable latency
1082 system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total 73267.637326 # average ReadReq mshr uncacheable latency
1083 system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 156312.791551 # average WriteReq mshr uncacheable latency
1084 system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::total 156312.791551 # average WriteReq mshr uncacheable latency
1085 system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 102616.863550 # average overall mshr uncacheable latency
1086 system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total 102616.863550 # average overall mshr uncacheable latency
1087 system.cpu7.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
1088 system.l2c.tags.replacements 14328 # number of replacements
1089 system.l2c.tags.tagsinuse 791.177993 # Cycle average of tags in use
1090 system.l2c.tags.total_refs 163940 # Total number of references to valid blocks.
1091 system.l2c.tags.sampled_refs 15120 # Sample count of references to valid blocks.
1092 system.l2c.tags.avg_refs 10.842593 # Average number of references to valid blocks.
1093 system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1094 system.l2c.tags.occ_blocks::writebacks 732.189847 # Average occupied blocks per requestor
1095 system.l2c.tags.occ_blocks::cpu0 7.660754 # Average occupied blocks per requestor
1096 system.l2c.tags.occ_blocks::cpu1 7.418431 # Average occupied blocks per requestor
1097 system.l2c.tags.occ_blocks::cpu2 7.928491 # Average occupied blocks per requestor
1098 system.l2c.tags.occ_blocks::cpu3 7.181835 # Average occupied blocks per requestor
1099 system.l2c.tags.occ_blocks::cpu4 7.391664 # Average occupied blocks per requestor
1100 system.l2c.tags.occ_blocks::cpu5 6.508374 # Average occupied blocks per requestor
1101 system.l2c.tags.occ_blocks::cpu6 7.134486 # Average occupied blocks per requestor
1102 system.l2c.tags.occ_blocks::cpu7 7.764111 # Average occupied blocks per requestor
1103 system.l2c.tags.occ_percent::writebacks 0.715029 # Average percentage of cache occupancy
1104 system.l2c.tags.occ_percent::cpu0 0.007481 # Average percentage of cache occupancy
1105 system.l2c.tags.occ_percent::cpu1 0.007245 # Average percentage of cache occupancy
1106 system.l2c.tags.occ_percent::cpu2 0.007743 # Average percentage of cache occupancy
1107 system.l2c.tags.occ_percent::cpu3 0.007014 # Average percentage of cache occupancy
1108 system.l2c.tags.occ_percent::cpu4 0.007218 # Average percentage of cache occupancy
1109 system.l2c.tags.occ_percent::cpu5 0.006356 # Average percentage of cache occupancy
1110 system.l2c.tags.occ_percent::cpu6 0.006967 # Average percentage of cache occupancy
1111 system.l2c.tags.occ_percent::cpu7 0.007582 # Average percentage of cache occupancy
1112 system.l2c.tags.occ_percent::total 0.772635 # Average percentage of cache occupancy
1113 system.l2c.tags.occ_task_id_blocks::1024 792 # Occupied blocks per task id
1114 system.l2c.tags.age_task_id_blocks_1024::0 650 # Occupied blocks per task id
1115 system.l2c.tags.age_task_id_blocks_1024::1 142 # Occupied blocks per task id
1116 system.l2c.tags.occ_task_id_percent::1024 0.773438 # Percentage of cache occupancy per task id
1117 system.l2c.tags.tag_accesses 2105170 # Number of tag accesses
1118 system.l2c.tags.data_accesses 2105170 # Number of data accesses
1119 system.l2c.WritebackDirty_hits::writebacks 77576 # number of WritebackDirty hits
1120 system.l2c.WritebackDirty_hits::total 77576 # number of WritebackDirty hits
1121 system.l2c.UpgradeReq_hits::cpu0 276 # number of UpgradeReq hits
1122 system.l2c.UpgradeReq_hits::cpu1 259 # number of UpgradeReq hits
1123 system.l2c.UpgradeReq_hits::cpu2 279 # number of UpgradeReq hits
1124 system.l2c.UpgradeReq_hits::cpu3 261 # number of UpgradeReq hits
1125 system.l2c.UpgradeReq_hits::cpu4 303 # number of UpgradeReq hits
1126 system.l2c.UpgradeReq_hits::cpu5 269 # number of UpgradeReq hits
1127 system.l2c.UpgradeReq_hits::cpu6 291 # number of UpgradeReq hits
1128 system.l2c.UpgradeReq_hits::cpu7 289 # number of UpgradeReq hits
1129 system.l2c.UpgradeReq_hits::total 2227 # number of UpgradeReq hits
1130 system.l2c.ReadExReq_hits::cpu0 1751 # number of ReadExReq hits
1131 system.l2c.ReadExReq_hits::cpu1 1771 # number of ReadExReq hits
1132 system.l2c.ReadExReq_hits::cpu2 1804 # number of ReadExReq hits
1133 system.l2c.ReadExReq_hits::cpu3 1773 # number of ReadExReq hits
1134 system.l2c.ReadExReq_hits::cpu4 1863 # number of ReadExReq hits
1135 system.l2c.ReadExReq_hits::cpu5 1769 # number of ReadExReq hits
1136 system.l2c.ReadExReq_hits::cpu6 1750 # number of ReadExReq hits
1137 system.l2c.ReadExReq_hits::cpu7 1757 # number of ReadExReq hits
1138 system.l2c.ReadExReq_hits::total 14238 # number of ReadExReq hits
1139 system.l2c.ReadSharedReq_hits::cpu0 10760 # number of ReadSharedReq hits
1140 system.l2c.ReadSharedReq_hits::cpu1 10778 # number of ReadSharedReq hits
1141 system.l2c.ReadSharedReq_hits::cpu2 10893 # number of ReadSharedReq hits
1142 system.l2c.ReadSharedReq_hits::cpu3 11049 # number of ReadSharedReq hits
1143 system.l2c.ReadSharedReq_hits::cpu4 10672 # number of ReadSharedReq hits
1144 system.l2c.ReadSharedReq_hits::cpu5 10913 # number of ReadSharedReq hits
1145 system.l2c.ReadSharedReq_hits::cpu6 11141 # number of ReadSharedReq hits
1146 system.l2c.ReadSharedReq_hits::cpu7 10949 # number of ReadSharedReq hits
1147 system.l2c.ReadSharedReq_hits::total 87155 # number of ReadSharedReq hits
1148 system.l2c.demand_hits::cpu0 12511 # number of demand (read+write) hits
1149 system.l2c.demand_hits::cpu1 12549 # number of demand (read+write) hits
1150 system.l2c.demand_hits::cpu2 12697 # number of demand (read+write) hits
1151 system.l2c.demand_hits::cpu3 12822 # number of demand (read+write) hits
1152 system.l2c.demand_hits::cpu4 12535 # number of demand (read+write) hits
1153 system.l2c.demand_hits::cpu5 12682 # number of demand (read+write) hits
1154 system.l2c.demand_hits::cpu6 12891 # number of demand (read+write) hits
1155 system.l2c.demand_hits::cpu7 12706 # number of demand (read+write) hits
1156 system.l2c.demand_hits::total 101393 # number of demand (read+write) hits
1157 system.l2c.overall_hits::cpu0 12511 # number of overall hits
1158 system.l2c.overall_hits::cpu1 12549 # number of overall hits
1159 system.l2c.overall_hits::cpu2 12697 # number of overall hits
1160 system.l2c.overall_hits::cpu3 12822 # number of overall hits
1161 system.l2c.overall_hits::cpu4 12535 # number of overall hits
1162 system.l2c.overall_hits::cpu5 12682 # number of overall hits
1163 system.l2c.overall_hits::cpu6 12891 # number of overall hits
1164 system.l2c.overall_hits::cpu7 12706 # number of overall hits
1165 system.l2c.overall_hits::total 101393 # number of overall hits
1166 system.l2c.UpgradeReq_misses::cpu0 2046 # number of UpgradeReq misses
1167 system.l2c.UpgradeReq_misses::cpu1 2029 # number of UpgradeReq misses
1168 system.l2c.UpgradeReq_misses::cpu2 2111 # number of UpgradeReq misses
1169 system.l2c.UpgradeReq_misses::cpu3 2056 # number of UpgradeReq misses
1170 system.l2c.UpgradeReq_misses::cpu4 2033 # number of UpgradeReq misses
1171 system.l2c.UpgradeReq_misses::cpu5 2090 # number of UpgradeReq misses
1172 system.l2c.UpgradeReq_misses::cpu6 2030 # number of UpgradeReq misses
1173 system.l2c.UpgradeReq_misses::cpu7 1987 # number of UpgradeReq misses
1174 system.l2c.UpgradeReq_misses::total 16382 # number of UpgradeReq misses
1175 system.l2c.ReadExReq_misses::cpu0 4599 # number of ReadExReq misses
1176 system.l2c.ReadExReq_misses::cpu1 4725 # number of ReadExReq misses
1177 system.l2c.ReadExReq_misses::cpu2 4817 # number of ReadExReq misses
1178 system.l2c.ReadExReq_misses::cpu3 4668 # number of ReadExReq misses
1179 system.l2c.ReadExReq_misses::cpu4 4596 # number of ReadExReq misses
1180 system.l2c.ReadExReq_misses::cpu5 4594 # number of ReadExReq misses
1181 system.l2c.ReadExReq_misses::cpu6 4511 # number of ReadExReq misses
1182 system.l2c.ReadExReq_misses::cpu7 4557 # number of ReadExReq misses
1183 system.l2c.ReadExReq_misses::total 37067 # number of ReadExReq misses
1184 system.l2c.ReadSharedReq_misses::cpu0 771 # number of ReadSharedReq misses
1185 system.l2c.ReadSharedReq_misses::cpu1 761 # number of ReadSharedReq misses
1186 system.l2c.ReadSharedReq_misses::cpu2 769 # number of ReadSharedReq misses
1187 system.l2c.ReadSharedReq_misses::cpu3 709 # number of ReadSharedReq misses
1188 system.l2c.ReadSharedReq_misses::cpu4 779 # number of ReadSharedReq misses
1189 system.l2c.ReadSharedReq_misses::cpu5 699 # number of ReadSharedReq misses
1190 system.l2c.ReadSharedReq_misses::cpu6 722 # number of ReadSharedReq misses
1191 system.l2c.ReadSharedReq_misses::cpu7 759 # number of ReadSharedReq misses
1192 system.l2c.ReadSharedReq_misses::total 5969 # number of ReadSharedReq misses
1193 system.l2c.demand_misses::cpu0 5370 # number of demand (read+write) misses
1194 system.l2c.demand_misses::cpu1 5486 # number of demand (read+write) misses
1195 system.l2c.demand_misses::cpu2 5586 # number of demand (read+write) misses
1196 system.l2c.demand_misses::cpu3 5377 # number of demand (read+write) misses
1197 system.l2c.demand_misses::cpu4 5375 # number of demand (read+write) misses
1198 system.l2c.demand_misses::cpu5 5293 # number of demand (read+write) misses
1199 system.l2c.demand_misses::cpu6 5233 # number of demand (read+write) misses
1200 system.l2c.demand_misses::cpu7 5316 # number of demand (read+write) misses
1201 system.l2c.demand_misses::total 43036 # number of demand (read+write) misses
1202 system.l2c.overall_misses::cpu0 5370 # number of overall misses
1203 system.l2c.overall_misses::cpu1 5486 # number of overall misses
1204 system.l2c.overall_misses::cpu2 5586 # number of overall misses
1205 system.l2c.overall_misses::cpu3 5377 # number of overall misses
1206 system.l2c.overall_misses::cpu4 5375 # number of overall misses
1207 system.l2c.overall_misses::cpu5 5293 # number of overall misses
1208 system.l2c.overall_misses::cpu6 5233 # number of overall misses
1209 system.l2c.overall_misses::cpu7 5316 # number of overall misses
1210 system.l2c.overall_misses::total 43036 # number of overall misses
1211 system.l2c.UpgradeReq_miss_latency::cpu0 72840477 # number of UpgradeReq miss cycles
1212 system.l2c.UpgradeReq_miss_latency::cpu1 70862981 # number of UpgradeReq miss cycles
1213 system.l2c.UpgradeReq_miss_latency::cpu2 74683475 # number of UpgradeReq miss cycles
1214 system.l2c.UpgradeReq_miss_latency::cpu3 72897976 # number of UpgradeReq miss cycles
1215 system.l2c.UpgradeReq_miss_latency::cpu4 72564980 # number of UpgradeReq miss cycles
1216 system.l2c.UpgradeReq_miss_latency::cpu5 68905302 # number of UpgradeReq miss cycles
1217 system.l2c.UpgradeReq_miss_latency::cpu6 71238981 # number of UpgradeReq miss cycles
1218 system.l2c.UpgradeReq_miss_latency::cpu7 72107979 # number of UpgradeReq miss cycles
1219 system.l2c.UpgradeReq_miss_latency::total 576102151 # number of UpgradeReq miss cycles
1220 system.l2c.ReadExReq_miss_latency::cpu0 293596847 # number of ReadExReq miss cycles
1221 system.l2c.ReadExReq_miss_latency::cpu1 301266861 # number of ReadExReq miss cycles
1222 system.l2c.ReadExReq_miss_latency::cpu2 306960376 # number of ReadExReq miss cycles
1223 system.l2c.ReadExReq_miss_latency::cpu3 297631356 # number of ReadExReq miss cycles
1224 system.l2c.ReadExReq_miss_latency::cpu4 293263365 # number of ReadExReq miss cycles
1225 system.l2c.ReadExReq_miss_latency::cpu5 292806382 # number of ReadExReq miss cycles
1226 system.l2c.ReadExReq_miss_latency::cpu6 287321715 # number of ReadExReq miss cycles
1227 system.l2c.ReadExReq_miss_latency::cpu7 290617373 # number of ReadExReq miss cycles
1228 system.l2c.ReadExReq_miss_latency::total 2363464275 # number of ReadExReq miss cycles
1229 system.l2c.ReadSharedReq_miss_latency::cpu0 53018410 # number of ReadSharedReq miss cycles
1230 system.l2c.ReadSharedReq_miss_latency::cpu1 52427412 # number of ReadSharedReq miss cycles
1231 system.l2c.ReadSharedReq_miss_latency::cpu2 53340392 # number of ReadSharedReq miss cycles
1232 system.l2c.ReadSharedReq_miss_latency::cpu3 48936413 # number of ReadSharedReq miss cycles
1233 system.l2c.ReadSharedReq_miss_latency::cpu4 53163418 # number of ReadSharedReq miss cycles
1234 system.l2c.ReadSharedReq_miss_latency::cpu5 48227901 # number of ReadSharedReq miss cycles
1235 system.l2c.ReadSharedReq_miss_latency::cpu6 50021405 # number of ReadSharedReq miss cycles
1236 system.l2c.ReadSharedReq_miss_latency::cpu7 52163904 # number of ReadSharedReq miss cycles
1237 system.l2c.ReadSharedReq_miss_latency::total 411299255 # number of ReadSharedReq miss cycles
1238 system.l2c.demand_miss_latency::cpu0 346615257 # number of demand (read+write) miss cycles
1239 system.l2c.demand_miss_latency::cpu1 353694273 # number of demand (read+write) miss cycles
1240 system.l2c.demand_miss_latency::cpu2 360300768 # number of demand (read+write) miss cycles
1241 system.l2c.demand_miss_latency::cpu3 346567769 # number of demand (read+write) miss cycles
1242 system.l2c.demand_miss_latency::cpu4 346426783 # number of demand (read+write) miss cycles
1243 system.l2c.demand_miss_latency::cpu5 341034283 # number of demand (read+write) miss cycles
1244 system.l2c.demand_miss_latency::cpu6 337343120 # number of demand (read+write) miss cycles
1245 system.l2c.demand_miss_latency::cpu7 342781277 # number of demand (read+write) miss cycles
1246 system.l2c.demand_miss_latency::total 2774763530 # number of demand (read+write) miss cycles
1247 system.l2c.overall_miss_latency::cpu0 346615257 # number of overall miss cycles
1248 system.l2c.overall_miss_latency::cpu1 353694273 # number of overall miss cycles
1249 system.l2c.overall_miss_latency::cpu2 360300768 # number of overall miss cycles
1250 system.l2c.overall_miss_latency::cpu3 346567769 # number of overall miss cycles
1251 system.l2c.overall_miss_latency::cpu4 346426783 # number of overall miss cycles
1252 system.l2c.overall_miss_latency::cpu5 341034283 # number of overall miss cycles
1253 system.l2c.overall_miss_latency::cpu6 337343120 # number of overall miss cycles
1254 system.l2c.overall_miss_latency::cpu7 342781277 # number of overall miss cycles
1255 system.l2c.overall_miss_latency::total 2774763530 # number of overall miss cycles
1256 system.l2c.WritebackDirty_accesses::writebacks 77576 # number of WritebackDirty accesses(hits+misses)
1257 system.l2c.WritebackDirty_accesses::total 77576 # number of WritebackDirty accesses(hits+misses)
1258 system.l2c.UpgradeReq_accesses::cpu0 2322 # number of UpgradeReq accesses(hits+misses)
1259 system.l2c.UpgradeReq_accesses::cpu1 2288 # number of UpgradeReq accesses(hits+misses)
1260 system.l2c.UpgradeReq_accesses::cpu2 2390 # number of UpgradeReq accesses(hits+misses)
1261 system.l2c.UpgradeReq_accesses::cpu3 2317 # number of UpgradeReq accesses(hits+misses)
1262 system.l2c.UpgradeReq_accesses::cpu4 2336 # number of UpgradeReq accesses(hits+misses)
1263 system.l2c.UpgradeReq_accesses::cpu5 2359 # number of UpgradeReq accesses(hits+misses)
1264 system.l2c.UpgradeReq_accesses::cpu6 2321 # number of UpgradeReq accesses(hits+misses)
1265 system.l2c.UpgradeReq_accesses::cpu7 2276 # number of UpgradeReq accesses(hits+misses)
1266 system.l2c.UpgradeReq_accesses::total 18609 # number of UpgradeReq accesses(hits+misses)
1267 system.l2c.ReadExReq_accesses::cpu0 6350 # number of ReadExReq accesses(hits+misses)
1268 system.l2c.ReadExReq_accesses::cpu1 6496 # number of ReadExReq accesses(hits+misses)
1269 system.l2c.ReadExReq_accesses::cpu2 6621 # number of ReadExReq accesses(hits+misses)
1270 system.l2c.ReadExReq_accesses::cpu3 6441 # number of ReadExReq accesses(hits+misses)
1271 system.l2c.ReadExReq_accesses::cpu4 6459 # number of ReadExReq accesses(hits+misses)
1272 system.l2c.ReadExReq_accesses::cpu5 6363 # number of ReadExReq accesses(hits+misses)
1273 system.l2c.ReadExReq_accesses::cpu6 6261 # number of ReadExReq accesses(hits+misses)
1274 system.l2c.ReadExReq_accesses::cpu7 6314 # number of ReadExReq accesses(hits+misses)
1275 system.l2c.ReadExReq_accesses::total 51305 # number of ReadExReq accesses(hits+misses)
1276 system.l2c.ReadSharedReq_accesses::cpu0 11531 # number of ReadSharedReq accesses(hits+misses)
1277 system.l2c.ReadSharedReq_accesses::cpu1 11539 # number of ReadSharedReq accesses(hits+misses)
1278 system.l2c.ReadSharedReq_accesses::cpu2 11662 # number of ReadSharedReq accesses(hits+misses)
1279 system.l2c.ReadSharedReq_accesses::cpu3 11758 # number of ReadSharedReq accesses(hits+misses)
1280 system.l2c.ReadSharedReq_accesses::cpu4 11451 # number of ReadSharedReq accesses(hits+misses)
1281 system.l2c.ReadSharedReq_accesses::cpu5 11612 # number of ReadSharedReq accesses(hits+misses)
1282 system.l2c.ReadSharedReq_accesses::cpu6 11863 # number of ReadSharedReq accesses(hits+misses)
1283 system.l2c.ReadSharedReq_accesses::cpu7 11708 # number of ReadSharedReq accesses(hits+misses)
1284 system.l2c.ReadSharedReq_accesses::total 93124 # number of ReadSharedReq accesses(hits+misses)
1285 system.l2c.demand_accesses::cpu0 17881 # number of demand (read+write) accesses
1286 system.l2c.demand_accesses::cpu1 18035 # number of demand (read+write) accesses
1287 system.l2c.demand_accesses::cpu2 18283 # number of demand (read+write) accesses
1288 system.l2c.demand_accesses::cpu3 18199 # number of demand (read+write) accesses
1289 system.l2c.demand_accesses::cpu4 17910 # number of demand (read+write) accesses
1290 system.l2c.demand_accesses::cpu5 17975 # number of demand (read+write) accesses
1291 system.l2c.demand_accesses::cpu6 18124 # number of demand (read+write) accesses
1292 system.l2c.demand_accesses::cpu7 18022 # number of demand (read+write) accesses
1293 system.l2c.demand_accesses::total 144429 # number of demand (read+write) accesses
1294 system.l2c.overall_accesses::cpu0 17881 # number of overall (read+write) accesses
1295 system.l2c.overall_accesses::cpu1 18035 # number of overall (read+write) accesses
1296 system.l2c.overall_accesses::cpu2 18283 # number of overall (read+write) accesses
1297 system.l2c.overall_accesses::cpu3 18199 # number of overall (read+write) accesses
1298 system.l2c.overall_accesses::cpu4 17910 # number of overall (read+write) accesses
1299 system.l2c.overall_accesses::cpu5 17975 # number of overall (read+write) accesses
1300 system.l2c.overall_accesses::cpu6 18124 # number of overall (read+write) accesses
1301 system.l2c.overall_accesses::cpu7 18022 # number of overall (read+write) accesses
1302 system.l2c.overall_accesses::total 144429 # number of overall (read+write) accesses
1303 system.l2c.UpgradeReq_miss_rate::cpu0 0.881137 # miss rate for UpgradeReq accesses
1304 system.l2c.UpgradeReq_miss_rate::cpu1 0.886801 # miss rate for UpgradeReq accesses
1305 system.l2c.UpgradeReq_miss_rate::cpu2 0.883264 # miss rate for UpgradeReq accesses
1306 system.l2c.UpgradeReq_miss_rate::cpu3 0.887354 # miss rate for UpgradeReq accesses
1307 system.l2c.UpgradeReq_miss_rate::cpu4 0.870291 # miss rate for UpgradeReq accesses
1308 system.l2c.UpgradeReq_miss_rate::cpu5 0.885969 # miss rate for UpgradeReq accesses
1309 system.l2c.UpgradeReq_miss_rate::cpu6 0.874623 # miss rate for UpgradeReq accesses
1310 system.l2c.UpgradeReq_miss_rate::cpu7 0.873023 # miss rate for UpgradeReq accesses
1311 system.l2c.UpgradeReq_miss_rate::total 0.880327 # miss rate for UpgradeReq accesses
1312 system.l2c.ReadExReq_miss_rate::cpu0 0.724252 # miss rate for ReadExReq accesses
1313 system.l2c.ReadExReq_miss_rate::cpu1 0.727371 # miss rate for ReadExReq accesses
1314 system.l2c.ReadExReq_miss_rate::cpu2 0.727534 # miss rate for ReadExReq accesses
1315 system.l2c.ReadExReq_miss_rate::cpu3 0.724732 # miss rate for ReadExReq accesses
1316 system.l2c.ReadExReq_miss_rate::cpu4 0.711565 # miss rate for ReadExReq accesses
1317 system.l2c.ReadExReq_miss_rate::cpu5 0.721986 # miss rate for ReadExReq accesses
1318 system.l2c.ReadExReq_miss_rate::cpu6 0.720492 # miss rate for ReadExReq accesses
1319 system.l2c.ReadExReq_miss_rate::cpu7 0.721729 # miss rate for ReadExReq accesses
1320 system.l2c.ReadExReq_miss_rate::total 0.722483 # miss rate for ReadExReq accesses
1321 system.l2c.ReadSharedReq_miss_rate::cpu0 0.066863 # miss rate for ReadSharedReq accesses
1322 system.l2c.ReadSharedReq_miss_rate::cpu1 0.065950 # miss rate for ReadSharedReq accesses
1323 system.l2c.ReadSharedReq_miss_rate::cpu2 0.065941 # miss rate for ReadSharedReq accesses
1324 system.l2c.ReadSharedReq_miss_rate::cpu3 0.060299 # miss rate for ReadSharedReq accesses
1325 system.l2c.ReadSharedReq_miss_rate::cpu4 0.068029 # miss rate for ReadSharedReq accesses
1326 system.l2c.ReadSharedReq_miss_rate::cpu5 0.060196 # miss rate for ReadSharedReq accesses
1327 system.l2c.ReadSharedReq_miss_rate::cpu6 0.060862 # miss rate for ReadSharedReq accesses
1328 system.l2c.ReadSharedReq_miss_rate::cpu7 0.064827 # miss rate for ReadSharedReq accesses
1329 system.l2c.ReadSharedReq_miss_rate::total 0.064097 # miss rate for ReadSharedReq accesses
1330 system.l2c.demand_miss_rate::cpu0 0.300319 # miss rate for demand accesses
1331 system.l2c.demand_miss_rate::cpu1 0.304186 # miss rate for demand accesses
1332 system.l2c.demand_miss_rate::cpu2 0.305530 # miss rate for demand accesses
1333 system.l2c.demand_miss_rate::cpu3 0.295456 # miss rate for demand accesses
1334 system.l2c.demand_miss_rate::cpu4 0.300112 # miss rate for demand accesses
1335 system.l2c.demand_miss_rate::cpu5 0.294465 # miss rate for demand accesses
1336 system.l2c.demand_miss_rate::cpu6 0.288733 # miss rate for demand accesses
1337 system.l2c.demand_miss_rate::cpu7 0.294973 # miss rate for demand accesses
1338 system.l2c.demand_miss_rate::total 0.297973 # miss rate for demand accesses
1339 system.l2c.overall_miss_rate::cpu0 0.300319 # miss rate for overall accesses
1340 system.l2c.overall_miss_rate::cpu1 0.304186 # miss rate for overall accesses
1341 system.l2c.overall_miss_rate::cpu2 0.305530 # miss rate for overall accesses
1342 system.l2c.overall_miss_rate::cpu3 0.295456 # miss rate for overall accesses
1343 system.l2c.overall_miss_rate::cpu4 0.300112 # miss rate for overall accesses
1344 system.l2c.overall_miss_rate::cpu5 0.294465 # miss rate for overall accesses
1345 system.l2c.overall_miss_rate::cpu6 0.288733 # miss rate for overall accesses
1346 system.l2c.overall_miss_rate::cpu7 0.294973 # miss rate for overall accesses
1347 system.l2c.overall_miss_rate::total 0.297973 # miss rate for overall accesses
1348 system.l2c.UpgradeReq_avg_miss_latency::cpu0 35601.406158 # average UpgradeReq miss latency
1349 system.l2c.UpgradeReq_avg_miss_latency::cpu1 34925.076885 # average UpgradeReq miss latency
1350 system.l2c.UpgradeReq_avg_miss_latency::cpu2 35378.244908 # average UpgradeReq miss latency
1351 system.l2c.UpgradeReq_avg_miss_latency::cpu3 35456.214008 # average UpgradeReq miss latency
1352 system.l2c.UpgradeReq_avg_miss_latency::cpu4 35693.546483 # average UpgradeReq miss latency
1353 system.l2c.UpgradeReq_avg_miss_latency::cpu5 32969.044019 # average UpgradeReq miss latency
1354 system.l2c.UpgradeReq_avg_miss_latency::cpu6 35093.094089 # average UpgradeReq miss latency
1355 system.l2c.UpgradeReq_avg_miss_latency::cpu7 36289.873679 # average UpgradeReq miss latency
1356 system.l2c.UpgradeReq_avg_miss_latency::total 35166.777622 # average UpgradeReq miss latency
1357 system.l2c.ReadExReq_avg_miss_latency::cpu0 63839.279626 # average ReadExReq miss latency
1358 system.l2c.ReadExReq_avg_miss_latency::cpu1 63760.182222 # average ReadExReq miss latency
1359 system.l2c.ReadExReq_avg_miss_latency::cpu2 63724.387793 # average ReadExReq miss latency
1360 system.l2c.ReadExReq_avg_miss_latency::cpu3 63759.930591 # average ReadExReq miss latency
1361 system.l2c.ReadExReq_avg_miss_latency::cpu4 63808.390992 # average ReadExReq miss latency
1362 system.l2c.ReadExReq_avg_miss_latency::cpu5 63736.696125 # average ReadExReq miss latency
1363 system.l2c.ReadExReq_avg_miss_latency::cpu6 63693.574595 # average ReadExReq miss latency
1364 system.l2c.ReadExReq_avg_miss_latency::cpu7 63773.836515 # average ReadExReq miss latency
1365 system.l2c.ReadExReq_avg_miss_latency::total 63761.952006 # average ReadExReq miss latency
1366 system.l2c.ReadSharedReq_avg_miss_latency::cpu0 68765.771725 # average ReadSharedReq miss latency
1367 system.l2c.ReadSharedReq_avg_miss_latency::cpu1 68892.788436 # average ReadSharedReq miss latency
1368 system.l2c.ReadSharedReq_avg_miss_latency::cpu2 69363.318596 # average ReadSharedReq miss latency
1369 system.l2c.ReadSharedReq_avg_miss_latency::cpu3 69021.739069 # average ReadSharedReq miss latency
1370 system.l2c.ReadSharedReq_avg_miss_latency::cpu4 68245.722721 # average ReadSharedReq miss latency
1371 system.l2c.ReadSharedReq_avg_miss_latency::cpu5 68995.566524 # average ReadSharedReq miss latency
1372 system.l2c.ReadSharedReq_avg_miss_latency::cpu6 69281.724377 # average ReadSharedReq miss latency
1373 system.l2c.ReadSharedReq_avg_miss_latency::cpu7 68727.146245 # average ReadSharedReq miss latency
1374 system.l2c.ReadSharedReq_avg_miss_latency::total 68905.889596 # average ReadSharedReq miss latency
1375 system.l2c.demand_avg_miss_latency::cpu0 64546.602793 # average overall miss latency
1376 system.l2c.demand_avg_miss_latency::cpu1 64472.160591 # average overall miss latency
1377 system.l2c.demand_avg_miss_latency::cpu2 64500.674544 # average overall miss latency
1378 system.l2c.demand_avg_miss_latency::cpu3 64453.741678 # average overall miss latency
1379 system.l2c.demand_avg_miss_latency::cpu4 64451.494512 # average overall miss latency
1380 system.l2c.demand_avg_miss_latency::cpu5 64431.188929 # average overall miss latency
1381 system.l2c.demand_avg_miss_latency::cpu6 64464.574814 # average overall miss latency
1382 system.l2c.demand_avg_miss_latency::cpu7 64481.052859 # average overall miss latency
1383 system.l2c.demand_avg_miss_latency::total 64475.405010 # average overall miss latency
1384 system.l2c.overall_avg_miss_latency::cpu0 64546.602793 # average overall miss latency
1385 system.l2c.overall_avg_miss_latency::cpu1 64472.160591 # average overall miss latency
1386 system.l2c.overall_avg_miss_latency::cpu2 64500.674544 # average overall miss latency
1387 system.l2c.overall_avg_miss_latency::cpu3 64453.741678 # average overall miss latency
1388 system.l2c.overall_avg_miss_latency::cpu4 64451.494512 # average overall miss latency
1389 system.l2c.overall_avg_miss_latency::cpu5 64431.188929 # average overall miss latency
1390 system.l2c.overall_avg_miss_latency::cpu6 64464.574814 # average overall miss latency
1391 system.l2c.overall_avg_miss_latency::cpu7 64481.052859 # average overall miss latency
1392 system.l2c.overall_avg_miss_latency::total 64475.405010 # average overall miss latency
1393 system.l2c.blocked_cycles::no_mshrs 37689 # number of cycles access was blocked
1394 system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
1395 system.l2c.blocked::no_mshrs 7229 # number of cycles access was blocked
1396 system.l2c.blocked::no_targets 0 # number of cycles access was blocked
1397 system.l2c.avg_blocked_cycles::no_mshrs 5.213584 # average number of cycles each access was blocked
1398 system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1399 system.l2c.fast_writes 0 # number of fast writes performed
1400 system.l2c.cache_copies 0 # number of cache copies performed
1401 system.l2c.writebacks::writebacks 6662 # number of writebacks
1402 system.l2c.writebacks::total 6662 # number of writebacks
1403 system.l2c.UpgradeReq_mshr_hits::cpu0 1 # number of UpgradeReq MSHR hits
1404 system.l2c.UpgradeReq_mshr_hits::cpu1 5 # number of UpgradeReq MSHR hits
1405 system.l2c.UpgradeReq_mshr_hits::cpu3 1 # number of UpgradeReq MSHR hits
1406 system.l2c.UpgradeReq_mshr_hits::cpu4 1 # number of UpgradeReq MSHR hits
1407 system.l2c.UpgradeReq_mshr_hits::total 8 # number of UpgradeReq MSHR hits
1408 system.l2c.ReadExReq_mshr_hits::cpu0 7 # number of ReadExReq MSHR hits
1409 system.l2c.ReadExReq_mshr_hits::cpu1 5 # number of ReadExReq MSHR hits
1410 system.l2c.ReadExReq_mshr_hits::cpu2 7 # number of ReadExReq MSHR hits
1411 system.l2c.ReadExReq_mshr_hits::cpu3 7 # number of ReadExReq MSHR hits
1412 system.l2c.ReadExReq_mshr_hits::cpu4 3 # number of ReadExReq MSHR hits
1413 system.l2c.ReadExReq_mshr_hits::cpu5 4 # number of ReadExReq MSHR hits
1414 system.l2c.ReadExReq_mshr_hits::cpu6 6 # number of ReadExReq MSHR hits
1415 system.l2c.ReadExReq_mshr_hits::cpu7 6 # number of ReadExReq MSHR hits
1416 system.l2c.ReadExReq_mshr_hits::total 45 # number of ReadExReq MSHR hits
1417 system.l2c.ReadSharedReq_mshr_hits::cpu0 9 # number of ReadSharedReq MSHR hits
1418 system.l2c.ReadSharedReq_mshr_hits::cpu1 9 # number of ReadSharedReq MSHR hits
1419 system.l2c.ReadSharedReq_mshr_hits::cpu2 12 # number of ReadSharedReq MSHR hits
1420 system.l2c.ReadSharedReq_mshr_hits::cpu3 7 # number of ReadSharedReq MSHR hits
1421 system.l2c.ReadSharedReq_mshr_hits::cpu4 14 # number of ReadSharedReq MSHR hits
1422 system.l2c.ReadSharedReq_mshr_hits::cpu5 5 # number of ReadSharedReq MSHR hits
1423 system.l2c.ReadSharedReq_mshr_hits::cpu6 8 # number of ReadSharedReq MSHR hits
1424 system.l2c.ReadSharedReq_mshr_hits::cpu7 8 # number of ReadSharedReq MSHR hits
1425 system.l2c.ReadSharedReq_mshr_hits::total 72 # number of ReadSharedReq MSHR hits
1426 system.l2c.demand_mshr_hits::cpu0 16 # number of demand (read+write) MSHR hits
1427 system.l2c.demand_mshr_hits::cpu1 14 # number of demand (read+write) MSHR hits
1428 system.l2c.demand_mshr_hits::cpu2 19 # number of demand (read+write) MSHR hits
1429 system.l2c.demand_mshr_hits::cpu3 14 # number of demand (read+write) MSHR hits
1430 system.l2c.demand_mshr_hits::cpu4 17 # number of demand (read+write) MSHR hits
1431 system.l2c.demand_mshr_hits::cpu5 9 # number of demand (read+write) MSHR hits
1432 system.l2c.demand_mshr_hits::cpu6 14 # number of demand (read+write) MSHR hits
1433 system.l2c.demand_mshr_hits::cpu7 14 # number of demand (read+write) MSHR hits
1434 system.l2c.demand_mshr_hits::total 117 # number of demand (read+write) MSHR hits
1435 system.l2c.overall_mshr_hits::cpu0 16 # number of overall MSHR hits
1436 system.l2c.overall_mshr_hits::cpu1 14 # number of overall MSHR hits
1437 system.l2c.overall_mshr_hits::cpu2 19 # number of overall MSHR hits
1438 system.l2c.overall_mshr_hits::cpu3 14 # number of overall MSHR hits
1439 system.l2c.overall_mshr_hits::cpu4 17 # number of overall MSHR hits
1440 system.l2c.overall_mshr_hits::cpu5 9 # number of overall MSHR hits
1441 system.l2c.overall_mshr_hits::cpu6 14 # number of overall MSHR hits
1442 system.l2c.overall_mshr_hits::cpu7 14 # number of overall MSHR hits
1443 system.l2c.overall_mshr_hits::total 117 # number of overall MSHR hits
1444 system.l2c.CleanEvict_mshr_misses::writebacks 1261 # number of CleanEvict MSHR misses
1445 system.l2c.CleanEvict_mshr_misses::total 1261 # number of CleanEvict MSHR misses
1446 system.l2c.UpgradeReq_mshr_misses::cpu0 2045 # number of UpgradeReq MSHR misses
1447 system.l2c.UpgradeReq_mshr_misses::cpu1 2024 # number of UpgradeReq MSHR misses
1448 system.l2c.UpgradeReq_mshr_misses::cpu2 2111 # number of UpgradeReq MSHR misses
1449 system.l2c.UpgradeReq_mshr_misses::cpu3 2055 # number of UpgradeReq MSHR misses
1450 system.l2c.UpgradeReq_mshr_misses::cpu4 2032 # number of UpgradeReq MSHR misses
1451 system.l2c.UpgradeReq_mshr_misses::cpu5 2090 # number of UpgradeReq MSHR misses
1452 system.l2c.UpgradeReq_mshr_misses::cpu6 2030 # number of UpgradeReq MSHR misses
1453 system.l2c.UpgradeReq_mshr_misses::cpu7 1987 # number of UpgradeReq MSHR misses
1454 system.l2c.UpgradeReq_mshr_misses::total 16374 # number of UpgradeReq MSHR misses
1455 system.l2c.ReadExReq_mshr_misses::cpu0 4592 # number of ReadExReq MSHR misses
1456 system.l2c.ReadExReq_mshr_misses::cpu1 4720 # number of ReadExReq MSHR misses
1457 system.l2c.ReadExReq_mshr_misses::cpu2 4810 # number of ReadExReq MSHR misses
1458 system.l2c.ReadExReq_mshr_misses::cpu3 4661 # number of ReadExReq MSHR misses
1459 system.l2c.ReadExReq_mshr_misses::cpu4 4593 # number of ReadExReq MSHR misses
1460 system.l2c.ReadExReq_mshr_misses::cpu5 4590 # number of ReadExReq MSHR misses
1461 system.l2c.ReadExReq_mshr_misses::cpu6 4505 # number of ReadExReq MSHR misses
1462 system.l2c.ReadExReq_mshr_misses::cpu7 4551 # number of ReadExReq MSHR misses
1463 system.l2c.ReadExReq_mshr_misses::total 37022 # number of ReadExReq MSHR misses
1464 system.l2c.ReadSharedReq_mshr_misses::cpu0 762 # number of ReadSharedReq MSHR misses
1465 system.l2c.ReadSharedReq_mshr_misses::cpu1 752 # number of ReadSharedReq MSHR misses
1466 system.l2c.ReadSharedReq_mshr_misses::cpu2 757 # number of ReadSharedReq MSHR misses
1467 system.l2c.ReadSharedReq_mshr_misses::cpu3 702 # number of ReadSharedReq MSHR misses
1468 system.l2c.ReadSharedReq_mshr_misses::cpu4 765 # number of ReadSharedReq MSHR misses
1469 system.l2c.ReadSharedReq_mshr_misses::cpu5 694 # number of ReadSharedReq MSHR misses
1470 system.l2c.ReadSharedReq_mshr_misses::cpu6 714 # number of ReadSharedReq MSHR misses
1471 system.l2c.ReadSharedReq_mshr_misses::cpu7 751 # number of ReadSharedReq MSHR misses
1472 system.l2c.ReadSharedReq_mshr_misses::total 5897 # number of ReadSharedReq MSHR misses
1473 system.l2c.demand_mshr_misses::cpu0 5354 # number of demand (read+write) MSHR misses
1474 system.l2c.demand_mshr_misses::cpu1 5472 # number of demand (read+write) MSHR misses
1475 system.l2c.demand_mshr_misses::cpu2 5567 # number of demand (read+write) MSHR misses
1476 system.l2c.demand_mshr_misses::cpu3 5363 # number of demand (read+write) MSHR misses
1477 system.l2c.demand_mshr_misses::cpu4 5358 # number of demand (read+write) MSHR misses
1478 system.l2c.demand_mshr_misses::cpu5 5284 # number of demand (read+write) MSHR misses
1479 system.l2c.demand_mshr_misses::cpu6 5219 # number of demand (read+write) MSHR misses
1480 system.l2c.demand_mshr_misses::cpu7 5302 # number of demand (read+write) MSHR misses
1481 system.l2c.demand_mshr_misses::total 42919 # number of demand (read+write) MSHR misses
1482 system.l2c.overall_mshr_misses::cpu0 5354 # number of overall MSHR misses
1483 system.l2c.overall_mshr_misses::cpu1 5472 # number of overall MSHR misses
1484 system.l2c.overall_mshr_misses::cpu2 5567 # number of overall MSHR misses
1485 system.l2c.overall_mshr_misses::cpu3 5363 # number of overall MSHR misses
1486 system.l2c.overall_mshr_misses::cpu4 5358 # number of overall MSHR misses
1487 system.l2c.overall_mshr_misses::cpu5 5284 # number of overall MSHR misses
1488 system.l2c.overall_mshr_misses::cpu6 5219 # number of overall MSHR misses
1489 system.l2c.overall_mshr_misses::cpu7 5302 # number of overall MSHR misses
1490 system.l2c.overall_mshr_misses::total 42919 # number of overall MSHR misses
1491 system.l2c.ReadReq_mshr_uncacheable::cpu0 9885 # number of ReadReq MSHR uncacheable
1492 system.l2c.ReadReq_mshr_uncacheable::cpu1 9741 # number of ReadReq MSHR uncacheable
1493 system.l2c.ReadReq_mshr_uncacheable::cpu2 9774 # number of ReadReq MSHR uncacheable
1494 system.l2c.ReadReq_mshr_uncacheable::cpu3 9813 # number of ReadReq MSHR uncacheable
1495 system.l2c.ReadReq_mshr_uncacheable::cpu4 9945 # number of ReadReq MSHR uncacheable
1496 system.l2c.ReadReq_mshr_uncacheable::cpu5 9798 # number of ReadReq MSHR uncacheable
1497 system.l2c.ReadReq_mshr_uncacheable::cpu6 9837 # number of ReadReq MSHR uncacheable
1498 system.l2c.ReadReq_mshr_uncacheable::cpu7 9918 # number of ReadReq MSHR uncacheable
1499 system.l2c.ReadReq_mshr_uncacheable::total 78711 # number of ReadReq MSHR uncacheable
1500 system.l2c.WriteReq_mshr_uncacheable::cpu0 5567 # number of WriteReq MSHR uncacheable
1501 system.l2c.WriteReq_mshr_uncacheable::cpu1 5462 # number of WriteReq MSHR uncacheable
1502 system.l2c.WriteReq_mshr_uncacheable::cpu2 5416 # number of WriteReq MSHR uncacheable
1503 system.l2c.WriteReq_mshr_uncacheable::cpu3 5447 # number of WriteReq MSHR uncacheable
1504 system.l2c.WriteReq_mshr_uncacheable::cpu4 5329 # number of WriteReq MSHR uncacheable
1505 system.l2c.WriteReq_mshr_uncacheable::cpu5 5472 # number of WriteReq MSHR uncacheable
1506 system.l2c.WriteReq_mshr_uncacheable::cpu6 5532 # number of WriteReq MSHR uncacheable
1507 system.l2c.WriteReq_mshr_uncacheable::cpu7 5421 # number of WriteReq MSHR uncacheable
1508 system.l2c.WriteReq_mshr_uncacheable::total 43646 # number of WriteReq MSHR uncacheable
1509 system.l2c.overall_mshr_uncacheable_misses::cpu0 15452 # number of overall MSHR uncacheable misses
1510 system.l2c.overall_mshr_uncacheable_misses::cpu1 15203 # number of overall MSHR uncacheable misses
1511 system.l2c.overall_mshr_uncacheable_misses::cpu2 15190 # number of overall MSHR uncacheable misses
1512 system.l2c.overall_mshr_uncacheable_misses::cpu3 15260 # number of overall MSHR uncacheable misses
1513 system.l2c.overall_mshr_uncacheable_misses::cpu4 15274 # number of overall MSHR uncacheable misses
1514 system.l2c.overall_mshr_uncacheable_misses::cpu5 15270 # number of overall MSHR uncacheable misses
1515 system.l2c.overall_mshr_uncacheable_misses::cpu6 15369 # number of overall MSHR uncacheable misses
1516 system.l2c.overall_mshr_uncacheable_misses::cpu7 15339 # number of overall MSHR uncacheable misses
1517 system.l2c.overall_mshr_uncacheable_misses::total 122357 # number of overall MSHR uncacheable misses
1518 system.l2c.UpgradeReq_mshr_miss_latency::cpu0 109082461 # number of UpgradeReq MSHR miss cycles
1519 system.l2c.UpgradeReq_mshr_miss_latency::cpu1 108150960 # number of UpgradeReq MSHR miss cycles
1520 system.l2c.UpgradeReq_mshr_miss_latency::cpu2 112626780 # number of UpgradeReq MSHR miss cycles
1521 system.l2c.UpgradeReq_mshr_miss_latency::cpu3 109540787 # number of UpgradeReq MSHR miss cycles
1522 system.l2c.UpgradeReq_mshr_miss_latency::cpu4 108317960 # number of UpgradeReq MSHR miss cycles
1523 system.l2c.UpgradeReq_mshr_miss_latency::cpu5 111427287 # number of UpgradeReq MSHR miss cycles
1524 system.l2c.UpgradeReq_mshr_miss_latency::cpu6 108309961 # number of UpgradeReq MSHR miss cycles
1525 system.l2c.UpgradeReq_mshr_miss_latency::cpu7 105900964 # number of UpgradeReq MSHR miss cycles
1526 system.l2c.UpgradeReq_mshr_miss_latency::total 873357160 # number of UpgradeReq MSHR miss cycles
1527 system.l2c.ReadExReq_mshr_miss_latency::cpu0 247432848 # number of ReadExReq MSHR miss cycles
1528 system.l2c.ReadExReq_mshr_miss_latency::cpu1 253923362 # number of ReadExReq MSHR miss cycles
1529 system.l2c.ReadExReq_mshr_miss_latency::cpu2 258718876 # number of ReadExReq MSHR miss cycles
1530 system.l2c.ReadExReq_mshr_miss_latency::cpu3 250876356 # number of ReadExReq MSHR miss cycles
1531 system.l2c.ReadExReq_mshr_miss_latency::cpu4 247138365 # number of ReadExReq MSHR miss cycles
1532 system.l2c.ReadExReq_mshr_miss_latency::cpu5 246828882 # number of ReadExReq MSHR miss cycles
1533 system.l2c.ReadExReq_mshr_miss_latency::cpu6 242219215 # number of ReadExReq MSHR miss cycles
1534 system.l2c.ReadExReq_mshr_miss_latency::cpu7 244887373 # number of ReadExReq MSHR miss cycles
1535 system.l2c.ReadExReq_mshr_miss_latency::total 1992025277 # number of ReadExReq MSHR miss cycles
1536 system.l2c.ReadSharedReq_mshr_miss_latency::cpu0 45035910 # number of ReadSharedReq MSHR miss cycles
1537 system.l2c.ReadSharedReq_mshr_miss_latency::cpu1 44634913 # number of ReadSharedReq MSHR miss cycles
1538 system.l2c.ReadSharedReq_mshr_miss_latency::cpu2 45307393 # number of ReadSharedReq MSHR miss cycles
1539 system.l2c.ReadSharedReq_mshr_miss_latency::cpu3 41572414 # number of ReadSharedReq MSHR miss cycles
1540 system.l2c.ReadSharedReq_mshr_miss_latency::cpu4 44985419 # number of ReadSharedReq MSHR miss cycles
1541 system.l2c.ReadSharedReq_mshr_miss_latency::cpu5 41094402 # number of ReadSharedReq MSHR miss cycles
1542 system.l2c.ReadSharedReq_mshr_miss_latency::cpu6 42561407 # number of ReadSharedReq MSHR miss cycles
1543 system.l2c.ReadSharedReq_mshr_miss_latency::cpu7 44302905 # number of ReadSharedReq MSHR miss cycles
1544 system.l2c.ReadSharedReq_mshr_miss_latency::total 349494763 # number of ReadSharedReq MSHR miss cycles
1545 system.l2c.demand_mshr_miss_latency::cpu0 292468758 # number of demand (read+write) MSHR miss cycles
1546 system.l2c.demand_mshr_miss_latency::cpu1 298558275 # number of demand (read+write) MSHR miss cycles
1547 system.l2c.demand_mshr_miss_latency::cpu2 304026269 # number of demand (read+write) MSHR miss cycles
1548 system.l2c.demand_mshr_miss_latency::cpu3 292448770 # number of demand (read+write) MSHR miss cycles
1549 system.l2c.demand_mshr_miss_latency::cpu4 292123784 # number of demand (read+write) MSHR miss cycles
1550 system.l2c.demand_mshr_miss_latency::cpu5 287923284 # number of demand (read+write) MSHR miss cycles
1551 system.l2c.demand_mshr_miss_latency::cpu6 284780622 # number of demand (read+write) MSHR miss cycles
1552 system.l2c.demand_mshr_miss_latency::cpu7 289190278 # number of demand (read+write) MSHR miss cycles
1553 system.l2c.demand_mshr_miss_latency::total 2341520040 # number of demand (read+write) MSHR miss cycles
1554 system.l2c.overall_mshr_miss_latency::cpu0 292468758 # number of overall MSHR miss cycles
1555 system.l2c.overall_mshr_miss_latency::cpu1 298558275 # number of overall MSHR miss cycles
1556 system.l2c.overall_mshr_miss_latency::cpu2 304026269 # number of overall MSHR miss cycles
1557 system.l2c.overall_mshr_miss_latency::cpu3 292448770 # number of overall MSHR miss cycles
1558 system.l2c.overall_mshr_miss_latency::cpu4 292123784 # number of overall MSHR miss cycles
1559 system.l2c.overall_mshr_miss_latency::cpu5 287923284 # number of overall MSHR miss cycles
1560 system.l2c.overall_mshr_miss_latency::cpu6 284780622 # number of overall MSHR miss cycles
1561 system.l2c.overall_mshr_miss_latency::cpu7 289190278 # number of overall MSHR miss cycles
1562 system.l2c.overall_mshr_miss_latency::total 2341520040 # number of overall MSHR miss cycles
1563 system.l2c.ReadReq_mshr_uncacheable_latency::cpu0 521573114 # number of ReadReq MSHR uncacheable cycles
1564 system.l2c.ReadReq_mshr_uncacheable_latency::cpu1 514181757 # number of ReadReq MSHR uncacheable cycles
1565 system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 515732776 # number of ReadReq MSHR uncacheable cycles
1566 system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 517979251 # number of ReadReq MSHR uncacheable cycles
1567 system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 524791253 # number of ReadReq MSHR uncacheable cycles
1568 system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 517494740 # number of ReadReq MSHR uncacheable cycles
1569 system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 519233265 # number of ReadReq MSHR uncacheable cycles
1570 system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 524055269 # number of ReadReq MSHR uncacheable cycles
1571 system.l2c.ReadReq_mshr_uncacheable_latency::total 4155041425 # number of ReadReq MSHR uncacheable cycles
1572 system.l2c.WriteReq_mshr_uncacheable_latency::cpu0 302263386 # number of WriteReq MSHR uncacheable cycles
1573 system.l2c.WriteReq_mshr_uncacheable_latency::cpu1 299275381 # number of WriteReq MSHR uncacheable cycles
1574 system.l2c.WriteReq_mshr_uncacheable_latency::cpu2 295496378 # number of WriteReq MSHR uncacheable cycles
1575 system.l2c.WriteReq_mshr_uncacheable_latency::cpu3 297456387 # number of WriteReq MSHR uncacheable cycles
1576 system.l2c.WriteReq_mshr_uncacheable_latency::cpu4 290732905 # number of WriteReq MSHR uncacheable cycles
1577 system.l2c.WriteReq_mshr_uncacheable_latency::cpu5 298997210 # number of WriteReq MSHR uncacheable cycles
1578 system.l2c.WriteReq_mshr_uncacheable_latency::cpu6 303692889 # number of WriteReq MSHR uncacheable cycles
1579 system.l2c.WriteReq_mshr_uncacheable_latency::cpu7 296080198 # number of WriteReq MSHR uncacheable cycles
1580 system.l2c.WriteReq_mshr_uncacheable_latency::total 2383994734 # number of WriteReq MSHR uncacheable cycles
1581 system.l2c.overall_mshr_uncacheable_latency::cpu0 823836500 # number of overall MSHR uncacheable cycles
1582 system.l2c.overall_mshr_uncacheable_latency::cpu1 813457138 # number of overall MSHR uncacheable cycles
1583 system.l2c.overall_mshr_uncacheable_latency::cpu2 811229154 # number of overall MSHR uncacheable cycles
1584 system.l2c.overall_mshr_uncacheable_latency::cpu3 815435638 # number of overall MSHR uncacheable cycles
1585 system.l2c.overall_mshr_uncacheable_latency::cpu4 815524158 # number of overall MSHR uncacheable cycles
1586 system.l2c.overall_mshr_uncacheable_latency::cpu5 816491950 # number of overall MSHR uncacheable cycles
1587 system.l2c.overall_mshr_uncacheable_latency::cpu6 822926154 # number of overall MSHR uncacheable cycles
1588 system.l2c.overall_mshr_uncacheable_latency::cpu7 820135467 # number of overall MSHR uncacheable cycles
1589 system.l2c.overall_mshr_uncacheable_latency::total 6539036159 # number of overall MSHR uncacheable cycles
1590 system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
1591 system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
1592 system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.880706 # mshr miss rate for UpgradeReq accesses
1593 system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.884615 # mshr miss rate for UpgradeReq accesses
1594 system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.883264 # mshr miss rate for UpgradeReq accesses
1595 system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.886923 # mshr miss rate for UpgradeReq accesses
1596 system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.869863 # mshr miss rate for UpgradeReq accesses
1597 system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.885969 # mshr miss rate for UpgradeReq accesses
1598 system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.874623 # mshr miss rate for UpgradeReq accesses
1599 system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.873023 # mshr miss rate for UpgradeReq accesses
1600 system.l2c.UpgradeReq_mshr_miss_rate::total 0.879897 # mshr miss rate for UpgradeReq accesses
1601 system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.723150 # mshr miss rate for ReadExReq accesses
1602 system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.726601 # mshr miss rate for ReadExReq accesses
1603 system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.726476 # mshr miss rate for ReadExReq accesses
1604 system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.723645 # mshr miss rate for ReadExReq accesses
1605 system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.711101 # mshr miss rate for ReadExReq accesses
1606 system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.721358 # mshr miss rate for ReadExReq accesses
1607 system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.719534 # mshr miss rate for ReadExReq accesses
1608 system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.720779 # mshr miss rate for ReadExReq accesses
1609 system.l2c.ReadExReq_mshr_miss_rate::total 0.721606 # mshr miss rate for ReadExReq accesses
1610 system.l2c.ReadSharedReq_mshr_miss_rate::cpu0 0.066083 # mshr miss rate for ReadSharedReq accesses
1611 system.l2c.ReadSharedReq_mshr_miss_rate::cpu1 0.065170 # mshr miss rate for ReadSharedReq accesses
1612 system.l2c.ReadSharedReq_mshr_miss_rate::cpu2 0.064912 # mshr miss rate for ReadSharedReq accesses
1613 system.l2c.ReadSharedReq_mshr_miss_rate::cpu3 0.059704 # mshr miss rate for ReadSharedReq accesses
1614 system.l2c.ReadSharedReq_mshr_miss_rate::cpu4 0.066806 # mshr miss rate for ReadSharedReq accesses
1615 system.l2c.ReadSharedReq_mshr_miss_rate::cpu5 0.059766 # mshr miss rate for ReadSharedReq accesses
1616 system.l2c.ReadSharedReq_mshr_miss_rate::cpu6 0.060187 # mshr miss rate for ReadSharedReq accesses
1617 system.l2c.ReadSharedReq_mshr_miss_rate::cpu7 0.064144 # mshr miss rate for ReadSharedReq accesses
1618 system.l2c.ReadSharedReq_mshr_miss_rate::total 0.063324 # mshr miss rate for ReadSharedReq accesses
1619 system.l2c.demand_mshr_miss_rate::cpu0 0.299424 # mshr miss rate for demand accesses
1620 system.l2c.demand_mshr_miss_rate::cpu1 0.303410 # mshr miss rate for demand accesses
1621 system.l2c.demand_mshr_miss_rate::cpu2 0.304491 # mshr miss rate for demand accesses
1622 system.l2c.demand_mshr_miss_rate::cpu3 0.294687 # mshr miss rate for demand accesses
1623 system.l2c.demand_mshr_miss_rate::cpu4 0.299162 # mshr miss rate for demand accesses
1624 system.l2c.demand_mshr_miss_rate::cpu5 0.293964 # mshr miss rate for demand accesses
1625 system.l2c.demand_mshr_miss_rate::cpu6 0.287961 # mshr miss rate for demand accesses
1626 system.l2c.demand_mshr_miss_rate::cpu7 0.294196 # mshr miss rate for demand accesses
1627 system.l2c.demand_mshr_miss_rate::total 0.297163 # mshr miss rate for demand accesses
1628 system.l2c.overall_mshr_miss_rate::cpu0 0.299424 # mshr miss rate for overall accesses
1629 system.l2c.overall_mshr_miss_rate::cpu1 0.303410 # mshr miss rate for overall accesses
1630 system.l2c.overall_mshr_miss_rate::cpu2 0.304491 # mshr miss rate for overall accesses
1631 system.l2c.overall_mshr_miss_rate::cpu3 0.294687 # mshr miss rate for overall accesses
1632 system.l2c.overall_mshr_miss_rate::cpu4 0.299162 # mshr miss rate for overall accesses
1633 system.l2c.overall_mshr_miss_rate::cpu5 0.293964 # mshr miss rate for overall accesses
1634 system.l2c.overall_mshr_miss_rate::cpu6 0.287961 # mshr miss rate for overall accesses
1635 system.l2c.overall_mshr_miss_rate::cpu7 0.294196 # mshr miss rate for overall accesses
1636 system.l2c.overall_mshr_miss_rate::total 0.297163 # mshr miss rate for overall accesses
1637 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 53341.056724 # average UpgradeReq mshr miss latency
1638 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 53434.268775 # average UpgradeReq mshr miss latency
1639 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 53352.335386 # average UpgradeReq mshr miss latency
1640 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 53304.519221 # average UpgradeReq mshr miss latency
1641 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 53306.082677 # average UpgradeReq mshr miss latency
1642 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 53314.491388 # average UpgradeReq mshr miss latency
1643 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 53354.660591 # average UpgradeReq mshr miss latency
1644 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 53296.911928 # average UpgradeReq mshr miss latency
1645 system.l2c.UpgradeReq_avg_mshr_miss_latency::total 53338.045682 # average UpgradeReq mshr miss latency
1646 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 53883.459930 # average ReadExReq mshr miss latency
1647 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 53797.322458 # average ReadExReq mshr miss latency
1648 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 53787.708108 # average ReadExReq mshr miss latency
1649 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 53824.577558 # average ReadExReq mshr miss latency
1650 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 53807.612671 # average ReadExReq mshr miss latency
1651 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 53775.355556 # average ReadExReq mshr miss latency
1652 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 53766.751387 # average ReadExReq mshr miss latency
1653 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 53809.574379 # average ReadExReq mshr miss latency
1654 system.l2c.ReadExReq_avg_mshr_miss_latency::total 53806.527929 # average ReadExReq mshr miss latency
1655 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0 59102.244094 # average ReadSharedReq mshr miss latency
1656 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1 59354.937500 # average ReadSharedReq mshr miss latency
1657 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2 59851.245707 # average ReadSharedReq mshr miss latency
1658 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3 59219.962963 # average ReadSharedReq mshr miss latency
1659 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu4 58804.469281 # average ReadSharedReq mshr miss latency
1660 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu5 59213.835735 # average ReadSharedReq mshr miss latency
1661 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu6 59609.813725 # average ReadSharedReq mshr miss latency
1662 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu7 58991.884154 # average ReadSharedReq mshr miss latency
1663 system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 59266.536035 # average ReadSharedReq mshr miss latency
1664 system.l2c.demand_avg_mshr_miss_latency::cpu0 54626.215540 # average overall mshr miss latency
1665 system.l2c.demand_avg_mshr_miss_latency::cpu1 54561.088268 # average overall mshr miss latency
1666 system.l2c.demand_avg_mshr_miss_latency::cpu2 54612.227232 # average overall mshr miss latency
1667 system.l2c.demand_avg_mshr_miss_latency::cpu3 54530.816707 # average overall mshr miss latency
1668 system.l2c.demand_avg_mshr_miss_latency::cpu4 54521.049645 # average overall mshr miss latency
1669 system.l2c.demand_avg_mshr_miss_latency::cpu5 54489.644966 # average overall mshr miss latency
1670 system.l2c.demand_avg_mshr_miss_latency::cpu6 54566.127994 # average overall mshr miss latency
1671 system.l2c.demand_avg_mshr_miss_latency::cpu7 54543.620898 # average overall mshr miss latency
1672 system.l2c.demand_avg_mshr_miss_latency::total 54556.724062 # average overall mshr miss latency
1673 system.l2c.overall_avg_mshr_miss_latency::cpu0 54626.215540 # average overall mshr miss latency
1674 system.l2c.overall_avg_mshr_miss_latency::cpu1 54561.088268 # average overall mshr miss latency
1675 system.l2c.overall_avg_mshr_miss_latency::cpu2 54612.227232 # average overall mshr miss latency
1676 system.l2c.overall_avg_mshr_miss_latency::cpu3 54530.816707 # average overall mshr miss latency
1677 system.l2c.overall_avg_mshr_miss_latency::cpu4 54521.049645 # average overall mshr miss latency
1678 system.l2c.overall_avg_mshr_miss_latency::cpu5 54489.644966 # average overall mshr miss latency
1679 system.l2c.overall_avg_mshr_miss_latency::cpu6 54566.127994 # average overall mshr miss latency
1680 system.l2c.overall_avg_mshr_miss_latency::cpu7 54543.620898 # average overall mshr miss latency
1681 system.l2c.overall_avg_mshr_miss_latency::total 54556.724062 # average overall mshr miss latency
1682 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 52764.098533 # average ReadReq mshr uncacheable latency
1683 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 52785.315368 # average ReadReq mshr uncacheable latency
1684 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 52765.784326 # average ReadReq mshr uncacheable latency
1685 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3 52785.004688 # average ReadReq mshr uncacheable latency
1686 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4 52769.356762 # average ReadReq mshr uncacheable latency
1687 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5 52816.364564 # average ReadReq mshr uncacheable latency
1688 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6 52783.700823 # average ReadReq mshr uncacheable latency
1689 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7 52838.805102 # average ReadReq mshr uncacheable latency
1690 system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 52788.573706 # average ReadReq mshr uncacheable latency
1691 system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0 54295.560625 # average WriteReq mshr uncacheable latency
1692 system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1 54792.270414 # average WriteReq mshr uncacheable latency
1693 system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2 54559.892541 # average WriteReq mshr uncacheable latency
1694 system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3 54609.213696 # average WriteReq mshr uncacheable latency
1695 system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu4 54556.747044 # average WriteReq mshr uncacheable latency
1696 system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu5 54641.302997 # average WriteReq mshr uncacheable latency
1697 system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu6 54897.485358 # average WriteReq mshr uncacheable latency
1698 system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu7 54617.265818 # average WriteReq mshr uncacheable latency
1699 system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 54621.150483 # average WriteReq mshr uncacheable latency
1700 system.l2c.overall_avg_mshr_uncacheable_latency::cpu0 53315.849081 # average overall mshr uncacheable latency
1701 system.l2c.overall_avg_mshr_uncacheable_latency::cpu1 53506.356509 # average overall mshr uncacheable latency
1702 system.l2c.overall_avg_mshr_uncacheable_latency::cpu2 53405.474259 # average overall mshr uncacheable latency
1703 system.l2c.overall_avg_mshr_uncacheable_latency::cpu3 53436.149279 # average overall mshr uncacheable latency
1704 system.l2c.overall_avg_mshr_uncacheable_latency::cpu4 53392.965693 # average overall mshr uncacheable latency
1705 system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 53470.330714 # average overall mshr uncacheable latency
1706 system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 53544.547726 # average overall mshr uncacheable latency
1707 system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 53467.336006 # average overall mshr uncacheable latency
1708 system.l2c.overall_avg_mshr_uncacheable_latency::total 53442.272686 # average overall mshr uncacheable latency
1709 system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
1710 system.membus.snoop_filter.tot_requests 127545 # Total number of requests made to the snoop filter.
1711 system.membus.snoop_filter.hit_single_requests 121489 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1712 system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1713 system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
1714 system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1715 system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1716 system.membus.trans_dist::ReadReq 78710 # Transaction distribution
1717 system.membus.trans_dist::ReadResp 84594 # Transaction distribution
1718 system.membus.trans_dist::WriteReq 43645 # Transaction distribution
1719 system.membus.trans_dist::WriteResp 43644 # Transaction distribution
1720 system.membus.trans_dist::WritebackDirty 6662 # Transaction distribution
1721 system.membus.trans_dist::CleanEvict 1288 # Transaction distribution
1722 system.membus.trans_dist::UpgradeReq 60944 # Transaction distribution
1723 system.membus.trans_dist::UpgradeResp 50160 # Transaction distribution
1724 system.membus.trans_dist::ReadExReq 49324 # Transaction distribution
1725 system.membus.trans_dist::ReadExResp 3261 # Transaction distribution
1726 system.membus.trans_dist::ReadSharedReq 5890 # Transaction distribution
1727 system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 428122 # Packet count per connected master and slave (bytes)
1728 system.membus.pkt_count::total 428122 # Packet count per connected master and slave (bytes)
1729 system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1134381 # Cumulative packet size per connected master and slave (bytes)
1730 system.membus.pkt_size::total 1134381 # Cumulative packet size per connected master and slave (bytes)
1731 system.membus.snoops 56843 # Total snoops (count)
1732 system.membus.snoop_fanout::samples 246442 # Request fanout histogram
1733 system.membus.snoop_fanout::mean 0 # Request fanout histogram
1734 system.membus.snoop_fanout::stdev 0 # Request fanout histogram
1735 system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1736 system.membus.snoop_fanout::0 246442 100.00% 100.00% # Request fanout histogram
1737 system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
1738 system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1739 system.membus.snoop_fanout::min_value 0 # Request fanout histogram
1740 system.membus.snoop_fanout::max_value 0 # Request fanout histogram
1741 system.membus.snoop_fanout::total 246442 # Request fanout histogram
1742 system.membus.reqLayer0.occupancy 292771939 # Layer occupancy (ticks)
1743 system.membus.reqLayer0.utilization 54.1 # Layer utilization (%)
1744 system.membus.respLayer0.occupancy 296967000 # Layer occupancy (ticks)
1745 system.membus.respLayer0.utilization 54.9 # Layer utilization (%)
1746 system.toL2Bus.snoop_filter.tot_requests 667370 # Total number of requests made to the snoop filter.
1747 system.toL2Bus.snoop_filter.hit_single_requests 284034 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1748 system.toL2Bus.snoop_filter.hit_multi_requests 336982 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1749 system.toL2Bus.snoop_filter.tot_snoops 12889 # Total number of snoops made to the snoop filter.
1750 system.toL2Bus.snoop_filter.hit_single_snoops 5997 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1751 system.toL2Bus.snoop_filter.hit_multi_snoops 6892 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1752 system.toL2Bus.trans_dist::ReadReq 78711 # Transaction distribution
1753 system.toL2Bus.trans_dist::ReadResp 370868 # Transaction distribution
1754 system.toL2Bus.trans_dist::ReadRespWithInvalidate 5 # Transaction distribution
1755 system.toL2Bus.trans_dist::WriteReq 43646 # Transaction distribution
1756 system.toL2Bus.trans_dist::WriteResp 43643 # Transaction distribution
1757 system.toL2Bus.trans_dist::WritebackDirty 84238 # Transaction distribution
1758 system.toL2Bus.trans_dist::CleanEvict 20479 # Transaction distribution
1759 system.toL2Bus.trans_dist::UpgradeReq 29389 # Transaction distribution
1760 system.toL2Bus.trans_dist::UpgradeResp 29387 # Transaction distribution
1761 system.toL2Bus.trans_dist::ReadExReq 162232 # Transaction distribution
1762 system.toL2Bus.trans_dist::ReadExResp 162225 # Transaction distribution
1763 system.toL2Bus.trans_dist::ReadSharedReq 292173 # Transaction distribution
1764 system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 122572 # Packet count per connected master and slave (bytes)
1765 system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 122578 # Packet count per connected master and slave (bytes)
1766 system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 122851 # Packet count per connected master and slave (bytes)
1767 system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 122953 # Packet count per connected master and slave (bytes)
1768 system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 122545 # Packet count per connected master and slave (bytes)
1769 system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 122770 # Packet count per connected master and slave (bytes)
1770 system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 122967 # Packet count per connected master and slave (bytes)
1771 system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 122678 # Packet count per connected master and slave (bytes)
1772 system.toL2Bus.pkt_count::total 981914 # Packet count per connected master and slave (bytes)
1773 system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1769628 # Cumulative packet size per connected master and slave (bytes)
1774 system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1794530 # Cumulative packet size per connected master and slave (bytes)
1775 system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1801428 # Cumulative packet size per connected master and slave (bytes)
1776 system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1802844 # Cumulative packet size per connected master and slave (bytes)
1777 system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1789097 # Cumulative packet size per connected master and slave (bytes)
1778 system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1796324 # Cumulative packet size per connected master and slave (bytes)
1779 system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1791880 # Cumulative packet size per connected master and slave (bytes)
1780 system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1784489 # Cumulative packet size per connected master and slave (bytes)
1781 system.toL2Bus.pkt_size::total 14330220 # Cumulative packet size per connected master and slave (bytes)
1782 system.toL2Bus.snoops 335082 # Total snoops (count)
1783 system.toL2Bus.snoop_fanout::samples 628739 # Request fanout histogram
1784 system.toL2Bus.snoop_fanout::mean 1.148986 # Request fanout histogram
1785 system.toL2Bus.snoop_fanout::stdev 0.990092 # Request fanout histogram
1786 system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1787 system.toL2Bus.snoop_fanout::0 176143 28.02% 28.02% # Request fanout histogram
1788 system.toL2Bus.snoop_fanout::1 257926 41.02% 69.04% # Request fanout histogram
1789 system.toL2Bus.snoop_fanout::2 134453 21.38% 90.42% # Request fanout histogram
1790 system.toL2Bus.snoop_fanout::3 47224 7.51% 97.93% # Request fanout histogram
1791 system.toL2Bus.snoop_fanout::4 11211 1.78% 99.72% # Request fanout histogram
1792 system.toL2Bus.snoop_fanout::5 1632 0.26% 99.98% # Request fanout histogram
1793 system.toL2Bus.snoop_fanout::6 146 0.02% 100.00% # Request fanout histogram
1794 system.toL2Bus.snoop_fanout::7 4 0.00% 100.00% # Request fanout histogram
1795 system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram
1796 system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1797 system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
1798 system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram
1799 system.toL2Bus.snoop_fanout::total 628739 # Request fanout histogram
1800 system.toL2Bus.reqLayer0.occupancy 500695190 # Layer occupancy (ticks)
1801 system.toL2Bus.reqLayer0.utilization 92.6 # Layer utilization (%)
1802 system.toL2Bus.respLayer0.occupancy 101141048 # Layer occupancy (ticks)
1803 system.toL2Bus.respLayer0.utilization 18.7 # Layer utilization (%)
1804 system.toL2Bus.respLayer1.occupancy 101214213 # Layer occupancy (ticks)
1805 system.toL2Bus.respLayer1.utilization 18.7 # Layer utilization (%)
1806 system.toL2Bus.respLayer2.occupancy 101195728 # Layer occupancy (ticks)
1807 system.toL2Bus.respLayer2.utilization 18.7 # Layer utilization (%)
1808 system.toL2Bus.respLayer3.occupancy 101296930 # Layer occupancy (ticks)
1809 system.toL2Bus.respLayer3.utilization 18.7 # Layer utilization (%)
1810 system.toL2Bus.respLayer4.occupancy 101179412 # Layer occupancy (ticks)
1811 system.toL2Bus.respLayer4.utilization 18.7 # Layer utilization (%)
1812 system.toL2Bus.respLayer5.occupancy 101203668 # Layer occupancy (ticks)
1813 system.toL2Bus.respLayer5.utilization 18.7 # Layer utilization (%)
1814 system.toL2Bus.respLayer6.occupancy 101388789 # Layer occupancy (ticks)
1815 system.toL2Bus.respLayer6.utilization 18.7 # Layer utilization (%)
1816 system.toL2Bus.respLayer7.occupancy 101354632 # Layer occupancy (ticks)
1817 system.toL2Bus.respLayer7.utilization 18.7 # Layer utilization (%)
1819 ---------- End Simulation Statistics ----------
projects / gem5.git / blob