2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.001466 # Number of seconds simulated
4 sim_ticks 1466014000 # Number of ticks simulated
5 final_tick 1466014000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_tick_rate 362824283 # Simulator tick rate (ticks/s)
8 host_mem_usage 344492 # Number of bytes of host memory used
9 host_seconds 4.04 # Real time elapsed on the host
10 system.voltage_domain.voltage 1 # Voltage in Volts
11 system.clk_domain.clock 1000 # Clock period in ticks
12 system.physmem.bytes_read::cpu0 81024 # Number of bytes read from this memory
13 system.physmem.bytes_read::cpu1 82440 # Number of bytes read from this memory
14 system.physmem.bytes_read::cpu2 87271 # Number of bytes read from this memory
15 system.physmem.bytes_read::cpu3 81468 # Number of bytes read from this memory
16 system.physmem.bytes_read::cpu4 83154 # Number of bytes read from this memory
17 system.physmem.bytes_read::cpu5 83511 # Number of bytes read from this memory
18 system.physmem.bytes_read::cpu6 83243 # Number of bytes read from this memory
19 system.physmem.bytes_read::cpu7 81362 # Number of bytes read from this memory
20 system.physmem.bytes_read::total 663473 # Number of bytes read from this memory
21 system.physmem.bytes_written::writebacks 418112 # Number of bytes written to this memory
22 system.physmem.bytes_written::cpu0 5482 # Number of bytes written to this memory
23 system.physmem.bytes_written::cpu1 5323 # Number of bytes written to this memory
24 system.physmem.bytes_written::cpu2 5338 # Number of bytes written to this memory
25 system.physmem.bytes_written::cpu3 5333 # Number of bytes written to this memory
26 system.physmem.bytes_written::cpu4 5428 # Number of bytes written to this memory
27 system.physmem.bytes_written::cpu5 5332 # Number of bytes written to this memory
28 system.physmem.bytes_written::cpu6 5280 # Number of bytes written to this memory
29 system.physmem.bytes_written::cpu7 5327 # Number of bytes written to this memory
30 system.physmem.bytes_written::total 460955 # Number of bytes written to this memory
31 system.physmem.num_reads::cpu0 11094 # Number of read requests responded to by this memory
32 system.physmem.num_reads::cpu1 11124 # Number of read requests responded to by this memory
33 system.physmem.num_reads::cpu2 11230 # Number of read requests responded to by this memory
34 system.physmem.num_reads::cpu3 10971 # Number of read requests responded to by this memory
35 system.physmem.num_reads::cpu4 11082 # Number of read requests responded to by this memory
36 system.physmem.num_reads::cpu5 11061 # Number of read requests responded to by this memory
37 system.physmem.num_reads::cpu6 11171 # Number of read requests responded to by this memory
38 system.physmem.num_reads::cpu7 11117 # Number of read requests responded to by this memory
39 system.physmem.num_reads::total 88850 # Number of read requests responded to by this memory
40 system.physmem.num_writes::writebacks 6533 # Number of write requests responded to by this memory
41 system.physmem.num_writes::cpu0 5482 # Number of write requests responded to by this memory
42 system.physmem.num_writes::cpu1 5323 # Number of write requests responded to by this memory
43 system.physmem.num_writes::cpu2 5338 # Number of write requests responded to by this memory
44 system.physmem.num_writes::cpu3 5333 # Number of write requests responded to by this memory
45 system.physmem.num_writes::cpu4 5428 # Number of write requests responded to by this memory
46 system.physmem.num_writes::cpu5 5332 # Number of write requests responded to by this memory
47 system.physmem.num_writes::cpu6 5280 # Number of write requests responded to by this memory
48 system.physmem.num_writes::cpu7 5327 # Number of write requests responded to by this memory
49 system.physmem.num_writes::total 49376 # Number of write requests responded to by this memory
50 system.physmem.bw_read::cpu0 55268231 # Total read bandwidth from this memory (bytes/s)
51 system.physmem.bw_read::cpu1 56234115 # Total read bandwidth from this memory (bytes/s)
52 system.physmem.bw_read::cpu2 59529445 # Total read bandwidth from this memory (bytes/s)
53 system.physmem.bw_read::cpu3 55571093 # Total read bandwidth from this memory (bytes/s)
54 system.physmem.bw_read::cpu4 56721150 # Total read bandwidth from this memory (bytes/s)
55 system.physmem.bw_read::cpu5 56964667 # Total read bandwidth from this memory (bytes/s)
56 system.physmem.bw_read::cpu6 56781859 # Total read bandwidth from this memory (bytes/s)
57 system.physmem.bw_read::cpu7 55498788 # Total read bandwidth from this memory (bytes/s)
58 system.physmem.bw_read::total 452569348 # Total read bandwidth from this memory (bytes/s)
59 system.physmem.bw_write::writebacks 285203279 # Write bandwidth from this memory (bytes/s)
60 system.physmem.bw_write::cpu0 3739391 # Write bandwidth from this memory (bytes/s)
61 system.physmem.bw_write::cpu1 3630934 # Write bandwidth from this memory (bytes/s)
62 system.physmem.bw_write::cpu2 3641166 # Write bandwidth from this memory (bytes/s)
63 system.physmem.bw_write::cpu3 3637755 # Write bandwidth from this memory (bytes/s)
64 system.physmem.bw_write::cpu4 3702557 # Write bandwidth from this memory (bytes/s)
65 system.physmem.bw_write::cpu5 3637073 # Write bandwidth from this memory (bytes/s)
66 system.physmem.bw_write::cpu6 3601603 # Write bandwidth from this memory (bytes/s)
67 system.physmem.bw_write::cpu7 3633662 # Write bandwidth from this memory (bytes/s)
68 system.physmem.bw_write::total 314427420 # Write bandwidth from this memory (bytes/s)
69 system.physmem.bw_total::writebacks 285203279 # Total bandwidth to/from this memory (bytes/s)
70 system.physmem.bw_total::cpu0 59007622 # Total bandwidth to/from this memory (bytes/s)
71 system.physmem.bw_total::cpu1 59865049 # Total bandwidth to/from this memory (bytes/s)
72 system.physmem.bw_total::cpu2 63170611 # Total bandwidth to/from this memory (bytes/s)
73 system.physmem.bw_total::cpu3 59208848 # Total bandwidth to/from this memory (bytes/s)
74 system.physmem.bw_total::cpu4 60423707 # Total bandwidth to/from this memory (bytes/s)
75 system.physmem.bw_total::cpu5 60601741 # Total bandwidth to/from this memory (bytes/s)
76 system.physmem.bw_total::cpu6 60383462 # Total bandwidth to/from this memory (bytes/s)
77 system.physmem.bw_total::cpu7 59132450 # Total bandwidth to/from this memory (bytes/s)
78 system.physmem.bw_total::total 766996768 # Total bandwidth to/from this memory (bytes/s)
79 system.membus.snoop_filter.tot_requests 121068 # Total number of requests made to the snoop filter.
80 system.membus.snoop_filter.hit_single_requests 119020 # Number of requests hitting in the snoop filter with a single holder of the requested data.
81 system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
82 system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
83 system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
84 system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
85 system.membus.throughput 766995404 # Throughput (bytes/s)
86 system.membus.trans_dist::ReadReq 85646 # Transaction distribution
87 system.membus.trans_dist::ReadResp 85644 # Transaction distribution
88 system.membus.trans_dist::WriteReq 42843 # Transaction distribution
89 system.membus.trans_dist::WriteResp 42842 # Transaction distribution
90 system.membus.trans_dist::Writeback 6533 # Transaction distribution
91 system.membus.trans_dist::UpgradeReq 57248 # Transaction distribution
92 system.membus.trans_dist::UpgradeResp 46699 # Transaction distribution
93 system.membus.trans_dist::ReadExReq 48957 # Transaction distribution
94 system.membus.trans_dist::ReadExResp 3204 # Transaction distribution
95 system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 419616 # Packet count per connected master and slave (bytes)
96 system.membus.pkt_count::total 419616 # Packet count per connected master and slave (bytes)
97 system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 1124426 # Cumulative packet size per connected master and slave (bytes)
98 system.membus.tot_pkt_size::total 1124426 # Cumulative packet size per connected master and slave (bytes)
99 system.membus.data_through_bus 1124426 # Total data (bytes)
100 system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
101 system.membus.snoops_through_bus 56301 # Total snoops (count)
102 system.membus.snoop_fanout::samples 121068 # Request fanout histogram
103 system.membus.snoop_fanout::mean 0 # Request fanout histogram
104 system.membus.snoop_fanout::stdev 0 # Request fanout histogram
105 system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
106 system.membus.snoop_fanout::0 121068 100.00% 100.00% # Request fanout histogram
107 system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
108 system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
109 system.membus.snoop_fanout::min_value 0 # Request fanout histogram
110 system.membus.snoop_fanout::max_value 0 # Request fanout histogram
111 system.membus.snoop_fanout::total 121068 # Request fanout histogram
112 system.membus.reqLayer0.occupancy 476149500 # Layer occupancy (ticks)
113 system.membus.reqLayer0.utilization 32.5 # Layer utilization (%)
114 system.membus.respLayer0.occupancy 322630500 # Layer occupancy (ticks)
115 system.membus.respLayer0.utilization 22.0 # Layer utilization (%)
116 system.cpu_clk_domain.clock 500 # Clock period in ticks
117 system.l2c.tags.replacements 13552 # number of replacements
118 system.l2c.tags.tagsinuse 786.290427 # Cycle average of tags in use
119 system.l2c.tags.total_refs 149902 # Total number of references to valid blocks.
120 system.l2c.tags.sampled_refs 14350 # Sample count of references to valid blocks.
121 system.l2c.tags.avg_refs 10.446132 # Average number of references to valid blocks.
122 system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
123 system.l2c.tags.occ_blocks::writebacks 730.775276 # Average occupied blocks per requestor
124 system.l2c.tags.occ_blocks::cpu0 6.840177 # Average occupied blocks per requestor
125 system.l2c.tags.occ_blocks::cpu1 7.161871 # Average occupied blocks per requestor
126 system.l2c.tags.occ_blocks::cpu2 6.892698 # Average occupied blocks per requestor
127 system.l2c.tags.occ_blocks::cpu3 6.763865 # Average occupied blocks per requestor
128 system.l2c.tags.occ_blocks::cpu4 6.714219 # Average occupied blocks per requestor
129 system.l2c.tags.occ_blocks::cpu5 6.973391 # Average occupied blocks per requestor
130 system.l2c.tags.occ_blocks::cpu6 7.262671 # Average occupied blocks per requestor
131 system.l2c.tags.occ_blocks::cpu7 6.906259 # Average occupied blocks per requestor
132 system.l2c.tags.occ_percent::writebacks 0.713648 # Average percentage of cache occupancy
133 system.l2c.tags.occ_percent::cpu0 0.006680 # Average percentage of cache occupancy
134 system.l2c.tags.occ_percent::cpu1 0.006994 # Average percentage of cache occupancy
135 system.l2c.tags.occ_percent::cpu2 0.006731 # Average percentage of cache occupancy
136 system.l2c.tags.occ_percent::cpu3 0.006605 # Average percentage of cache occupancy
137 system.l2c.tags.occ_percent::cpu4 0.006557 # Average percentage of cache occupancy
138 system.l2c.tags.occ_percent::cpu5 0.006810 # Average percentage of cache occupancy
139 system.l2c.tags.occ_percent::cpu6 0.007092 # Average percentage of cache occupancy
140 system.l2c.tags.occ_percent::cpu7 0.006744 # Average percentage of cache occupancy
141 system.l2c.tags.occ_percent::total 0.767862 # Average percentage of cache occupancy
142 system.l2c.tags.occ_task_id_blocks::1024 798 # Occupied blocks per task id
143 system.l2c.tags.age_task_id_blocks_1024::0 368 # Occupied blocks per task id
144 system.l2c.tags.age_task_id_blocks_1024::1 428 # Occupied blocks per task id
145 system.l2c.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id
146 system.l2c.tags.occ_task_id_percent::1024 0.779297 # Percentage of cache occupancy per task id
147 system.l2c.tags.tag_accesses 1950254 # Number of tag accesses
148 system.l2c.tags.data_accesses 1950254 # Number of data accesses
149 system.l2c.ReadReq_hits::cpu0 10780 # number of ReadReq hits
150 system.l2c.ReadReq_hits::cpu1 10796 # number of ReadReq hits
151 system.l2c.ReadReq_hits::cpu2 10830 # number of ReadReq hits
152 system.l2c.ReadReq_hits::cpu3 10794 # number of ReadReq hits
153 system.l2c.ReadReq_hits::cpu4 10743 # number of ReadReq hits
154 system.l2c.ReadReq_hits::cpu5 10804 # number of ReadReq hits
155 system.l2c.ReadReq_hits::cpu6 10680 # number of ReadReq hits
156 system.l2c.ReadReq_hits::cpu7 10909 # number of ReadReq hits
157 system.l2c.ReadReq_hits::total 86336 # number of ReadReq hits
158 system.l2c.Writeback_hits::writebacks 74514 # number of Writeback hits
159 system.l2c.Writeback_hits::total 74514 # number of Writeback hits
160 system.l2c.UpgradeReq_hits::cpu0 330 # number of UpgradeReq hits
161 system.l2c.UpgradeReq_hits::cpu1 332 # number of UpgradeReq hits
162 system.l2c.UpgradeReq_hits::cpu2 379 # number of UpgradeReq hits
163 system.l2c.UpgradeReq_hits::cpu3 363 # number of UpgradeReq hits
164 system.l2c.UpgradeReq_hits::cpu4 357 # number of UpgradeReq hits
165 system.l2c.UpgradeReq_hits::cpu5 362 # number of UpgradeReq hits
166 system.l2c.UpgradeReq_hits::cpu6 317 # number of UpgradeReq hits
167 system.l2c.UpgradeReq_hits::cpu7 363 # number of UpgradeReq hits
168 system.l2c.UpgradeReq_hits::total 2803 # number of UpgradeReq hits
169 system.l2c.ReadExReq_hits::cpu0 1848 # number of ReadExReq hits
170 system.l2c.ReadExReq_hits::cpu1 1871 # number of ReadExReq hits
171 system.l2c.ReadExReq_hits::cpu2 1840 # number of ReadExReq hits
172 system.l2c.ReadExReq_hits::cpu3 1858 # number of ReadExReq hits
173 system.l2c.ReadExReq_hits::cpu4 1858 # number of ReadExReq hits
174 system.l2c.ReadExReq_hits::cpu5 1893 # number of ReadExReq hits
175 system.l2c.ReadExReq_hits::cpu6 1894 # number of ReadExReq hits
176 system.l2c.ReadExReq_hits::cpu7 1826 # number of ReadExReq hits
177 system.l2c.ReadExReq_hits::total 14888 # number of ReadExReq hits
178 system.l2c.demand_hits::cpu0 12628 # number of demand (read+write) hits
179 system.l2c.demand_hits::cpu1 12667 # number of demand (read+write) hits
180 system.l2c.demand_hits::cpu2 12670 # number of demand (read+write) hits
181 system.l2c.demand_hits::cpu3 12652 # number of demand (read+write) hits
182 system.l2c.demand_hits::cpu4 12601 # number of demand (read+write) hits
183 system.l2c.demand_hits::cpu5 12697 # number of demand (read+write) hits
184 system.l2c.demand_hits::cpu6 12574 # number of demand (read+write) hits
185 system.l2c.demand_hits::cpu7 12735 # number of demand (read+write) hits
186 system.l2c.demand_hits::total 101224 # number of demand (read+write) hits
187 system.l2c.overall_hits::cpu0 12628 # number of overall hits
188 system.l2c.overall_hits::cpu1 12667 # number of overall hits
189 system.l2c.overall_hits::cpu2 12670 # number of overall hits
190 system.l2c.overall_hits::cpu3 12652 # number of overall hits
191 system.l2c.overall_hits::cpu4 12601 # number of overall hits
192 system.l2c.overall_hits::cpu5 12697 # number of overall hits
193 system.l2c.overall_hits::cpu6 12574 # number of overall hits
194 system.l2c.overall_hits::cpu7 12735 # number of overall hits
195 system.l2c.overall_hits::total 101224 # number of overall hits
196 system.l2c.ReadReq_misses::cpu0 745 # number of ReadReq misses
197 system.l2c.ReadReq_misses::cpu1 743 # number of ReadReq misses
198 system.l2c.ReadReq_misses::cpu2 781 # number of ReadReq misses
199 system.l2c.ReadReq_misses::cpu3 728 # number of ReadReq misses
200 system.l2c.ReadReq_misses::cpu4 729 # number of ReadReq misses
201 system.l2c.ReadReq_misses::cpu5 753 # number of ReadReq misses
202 system.l2c.ReadReq_misses::cpu6 747 # number of ReadReq misses
203 system.l2c.ReadReq_misses::cpu7 720 # number of ReadReq misses
204 system.l2c.ReadReq_misses::total 5946 # number of ReadReq misses
205 system.l2c.UpgradeReq_misses::cpu0 1905 # number of UpgradeReq misses
206 system.l2c.UpgradeReq_misses::cpu1 1885 # number of UpgradeReq misses
207 system.l2c.UpgradeReq_misses::cpu2 1879 # number of UpgradeReq misses
208 system.l2c.UpgradeReq_misses::cpu3 1905 # number of UpgradeReq misses
209 system.l2c.UpgradeReq_misses::cpu4 1913 # number of UpgradeReq misses
210 system.l2c.UpgradeReq_misses::cpu5 1875 # number of UpgradeReq misses
211 system.l2c.UpgradeReq_misses::cpu6 1933 # number of UpgradeReq misses
212 system.l2c.UpgradeReq_misses::cpu7 1894 # number of UpgradeReq misses
213 system.l2c.UpgradeReq_misses::total 15189 # number of UpgradeReq misses
214 system.l2c.ReadExReq_misses::cpu0 4304 # number of ReadExReq misses
215 system.l2c.ReadExReq_misses::cpu1 4329 # number of ReadExReq misses
216 system.l2c.ReadExReq_misses::cpu2 4371 # number of ReadExReq misses
217 system.l2c.ReadExReq_misses::cpu3 4347 # number of ReadExReq misses
218 system.l2c.ReadExReq_misses::cpu4 4382 # number of ReadExReq misses
219 system.l2c.ReadExReq_misses::cpu5 4378 # number of ReadExReq misses
220 system.l2c.ReadExReq_misses::cpu6 4299 # number of ReadExReq misses
221 system.l2c.ReadExReq_misses::cpu7 4310 # number of ReadExReq misses
222 system.l2c.ReadExReq_misses::total 34720 # number of ReadExReq misses
223 system.l2c.demand_misses::cpu0 5049 # number of demand (read+write) misses
224 system.l2c.demand_misses::cpu1 5072 # number of demand (read+write) misses
225 system.l2c.demand_misses::cpu2 5152 # number of demand (read+write) misses
226 system.l2c.demand_misses::cpu3 5075 # number of demand (read+write) misses
227 system.l2c.demand_misses::cpu4 5111 # number of demand (read+write) misses
228 system.l2c.demand_misses::cpu5 5131 # number of demand (read+write) misses
229 system.l2c.demand_misses::cpu6 5046 # number of demand (read+write) misses
230 system.l2c.demand_misses::cpu7 5030 # number of demand (read+write) misses
231 system.l2c.demand_misses::total 40666 # number of demand (read+write) misses
232 system.l2c.overall_misses::cpu0 5049 # number of overall misses
233 system.l2c.overall_misses::cpu1 5072 # number of overall misses
234 system.l2c.overall_misses::cpu2 5152 # number of overall misses
235 system.l2c.overall_misses::cpu3 5075 # number of overall misses
236 system.l2c.overall_misses::cpu4 5111 # number of overall misses
237 system.l2c.overall_misses::cpu5 5131 # number of overall misses
238 system.l2c.overall_misses::cpu6 5046 # number of overall misses
239 system.l2c.overall_misses::cpu7 5030 # number of overall misses
240 system.l2c.overall_misses::total 40666 # number of overall misses
241 system.l2c.ReadReq_miss_latency::cpu0 43593500 # number of ReadReq miss cycles
242 system.l2c.ReadReq_miss_latency::cpu1 43998500 # number of ReadReq miss cycles
243 system.l2c.ReadReq_miss_latency::cpu2 45727000 # number of ReadReq miss cycles
244 system.l2c.ReadReq_miss_latency::cpu3 43059000 # number of ReadReq miss cycles
245 system.l2c.ReadReq_miss_latency::cpu4 43120000 # number of ReadReq miss cycles
246 system.l2c.ReadReq_miss_latency::cpu5 43827500 # number of ReadReq miss cycles
247 system.l2c.ReadReq_miss_latency::cpu6 44039000 # number of ReadReq miss cycles
248 system.l2c.ReadReq_miss_latency::cpu7 42172500 # number of ReadReq miss cycles
249 system.l2c.ReadReq_miss_latency::total 349537000 # number of ReadReq miss cycles
250 system.l2c.UpgradeReq_miss_latency::cpu0 55121000 # number of UpgradeReq miss cycles
251 system.l2c.UpgradeReq_miss_latency::cpu1 55784000 # number of UpgradeReq miss cycles
252 system.l2c.UpgradeReq_miss_latency::cpu2 54929500 # number of UpgradeReq miss cycles
253 system.l2c.UpgradeReq_miss_latency::cpu3 55686500 # number of UpgradeReq miss cycles
254 system.l2c.UpgradeReq_miss_latency::cpu4 54924000 # number of UpgradeReq miss cycles
255 system.l2c.UpgradeReq_miss_latency::cpu5 54520000 # number of UpgradeReq miss cycles
256 system.l2c.UpgradeReq_miss_latency::cpu6 53558500 # number of UpgradeReq miss cycles
257 system.l2c.UpgradeReq_miss_latency::cpu7 55750500 # number of UpgradeReq miss cycles
258 system.l2c.UpgradeReq_miss_latency::total 440274000 # number of UpgradeReq miss cycles
259 system.l2c.ReadExReq_miss_latency::cpu0 230029000 # number of ReadExReq miss cycles
260 system.l2c.ReadExReq_miss_latency::cpu1 231291500 # number of ReadExReq miss cycles
261 system.l2c.ReadExReq_miss_latency::cpu2 233753500 # number of ReadExReq miss cycles
262 system.l2c.ReadExReq_miss_latency::cpu3 232262000 # number of ReadExReq miss cycles
263 system.l2c.ReadExReq_miss_latency::cpu4 233669000 # number of ReadExReq miss cycles
264 system.l2c.ReadExReq_miss_latency::cpu5 234419500 # number of ReadExReq miss cycles
265 system.l2c.ReadExReq_miss_latency::cpu6 229747500 # number of ReadExReq miss cycles
266 system.l2c.ReadExReq_miss_latency::cpu7 230546000 # number of ReadExReq miss cycles
267 system.l2c.ReadExReq_miss_latency::total 1855718000 # number of ReadExReq miss cycles
268 system.l2c.demand_miss_latency::cpu0 273622500 # number of demand (read+write) miss cycles
269 system.l2c.demand_miss_latency::cpu1 275290000 # number of demand (read+write) miss cycles
270 system.l2c.demand_miss_latency::cpu2 279480500 # number of demand (read+write) miss cycles
271 system.l2c.demand_miss_latency::cpu3 275321000 # number of demand (read+write) miss cycles
272 system.l2c.demand_miss_latency::cpu4 276789000 # number of demand (read+write) miss cycles
273 system.l2c.demand_miss_latency::cpu5 278247000 # number of demand (read+write) miss cycles
274 system.l2c.demand_miss_latency::cpu6 273786500 # number of demand (read+write) miss cycles
275 system.l2c.demand_miss_latency::cpu7 272718500 # number of demand (read+write) miss cycles
276 system.l2c.demand_miss_latency::total 2205255000 # number of demand (read+write) miss cycles
277 system.l2c.overall_miss_latency::cpu0 273622500 # number of overall miss cycles
278 system.l2c.overall_miss_latency::cpu1 275290000 # number of overall miss cycles
279 system.l2c.overall_miss_latency::cpu2 279480500 # number of overall miss cycles
280 system.l2c.overall_miss_latency::cpu3 275321000 # number of overall miss cycles
281 system.l2c.overall_miss_latency::cpu4 276789000 # number of overall miss cycles
282 system.l2c.overall_miss_latency::cpu5 278247000 # number of overall miss cycles
283 system.l2c.overall_miss_latency::cpu6 273786500 # number of overall miss cycles
284 system.l2c.overall_miss_latency::cpu7 272718500 # number of overall miss cycles
285 system.l2c.overall_miss_latency::total 2205255000 # number of overall miss cycles
286 system.l2c.ReadReq_accesses::cpu0 11525 # number of ReadReq accesses(hits+misses)
287 system.l2c.ReadReq_accesses::cpu1 11539 # number of ReadReq accesses(hits+misses)
288 system.l2c.ReadReq_accesses::cpu2 11611 # number of ReadReq accesses(hits+misses)
289 system.l2c.ReadReq_accesses::cpu3 11522 # number of ReadReq accesses(hits+misses)
290 system.l2c.ReadReq_accesses::cpu4 11472 # number of ReadReq accesses(hits+misses)
291 system.l2c.ReadReq_accesses::cpu5 11557 # number of ReadReq accesses(hits+misses)
292 system.l2c.ReadReq_accesses::cpu6 11427 # number of ReadReq accesses(hits+misses)
293 system.l2c.ReadReq_accesses::cpu7 11629 # number of ReadReq accesses(hits+misses)
294 system.l2c.ReadReq_accesses::total 92282 # number of ReadReq accesses(hits+misses)
295 system.l2c.Writeback_accesses::writebacks 74514 # number of Writeback accesses(hits+misses)
296 system.l2c.Writeback_accesses::total 74514 # number of Writeback accesses(hits+misses)
297 system.l2c.UpgradeReq_accesses::cpu0 2235 # number of UpgradeReq accesses(hits+misses)
298 system.l2c.UpgradeReq_accesses::cpu1 2217 # number of UpgradeReq accesses(hits+misses)
299 system.l2c.UpgradeReq_accesses::cpu2 2258 # number of UpgradeReq accesses(hits+misses)
300 system.l2c.UpgradeReq_accesses::cpu3 2268 # number of UpgradeReq accesses(hits+misses)
301 system.l2c.UpgradeReq_accesses::cpu4 2270 # number of UpgradeReq accesses(hits+misses)
302 system.l2c.UpgradeReq_accesses::cpu5 2237 # number of UpgradeReq accesses(hits+misses)
303 system.l2c.UpgradeReq_accesses::cpu6 2250 # number of UpgradeReq accesses(hits+misses)
304 system.l2c.UpgradeReq_accesses::cpu7 2257 # number of UpgradeReq accesses(hits+misses)
305 system.l2c.UpgradeReq_accesses::total 17992 # number of UpgradeReq accesses(hits+misses)
306 system.l2c.ReadExReq_accesses::cpu0 6152 # number of ReadExReq accesses(hits+misses)
307 system.l2c.ReadExReq_accesses::cpu1 6200 # number of ReadExReq accesses(hits+misses)
308 system.l2c.ReadExReq_accesses::cpu2 6211 # number of ReadExReq accesses(hits+misses)
309 system.l2c.ReadExReq_accesses::cpu3 6205 # number of ReadExReq accesses(hits+misses)
310 system.l2c.ReadExReq_accesses::cpu4 6240 # number of ReadExReq accesses(hits+misses)
311 system.l2c.ReadExReq_accesses::cpu5 6271 # number of ReadExReq accesses(hits+misses)
312 system.l2c.ReadExReq_accesses::cpu6 6193 # number of ReadExReq accesses(hits+misses)
313 system.l2c.ReadExReq_accesses::cpu7 6136 # number of ReadExReq accesses(hits+misses)
314 system.l2c.ReadExReq_accesses::total 49608 # number of ReadExReq accesses(hits+misses)
315 system.l2c.demand_accesses::cpu0 17677 # number of demand (read+write) accesses
316 system.l2c.demand_accesses::cpu1 17739 # number of demand (read+write) accesses
317 system.l2c.demand_accesses::cpu2 17822 # number of demand (read+write) accesses
318 system.l2c.demand_accesses::cpu3 17727 # number of demand (read+write) accesses
319 system.l2c.demand_accesses::cpu4 17712 # number of demand (read+write) accesses
320 system.l2c.demand_accesses::cpu5 17828 # number of demand (read+write) accesses
321 system.l2c.demand_accesses::cpu6 17620 # number of demand (read+write) accesses
322 system.l2c.demand_accesses::cpu7 17765 # number of demand (read+write) accesses
323 system.l2c.demand_accesses::total 141890 # number of demand (read+write) accesses
324 system.l2c.overall_accesses::cpu0 17677 # number of overall (read+write) accesses
325 system.l2c.overall_accesses::cpu1 17739 # number of overall (read+write) accesses
326 system.l2c.overall_accesses::cpu2 17822 # number of overall (read+write) accesses
327 system.l2c.overall_accesses::cpu3 17727 # number of overall (read+write) accesses
328 system.l2c.overall_accesses::cpu4 17712 # number of overall (read+write) accesses
329 system.l2c.overall_accesses::cpu5 17828 # number of overall (read+write) accesses
330 system.l2c.overall_accesses::cpu6 17620 # number of overall (read+write) accesses
331 system.l2c.overall_accesses::cpu7 17765 # number of overall (read+write) accesses
332 system.l2c.overall_accesses::total 141890 # number of overall (read+write) accesses
333 system.l2c.ReadReq_miss_rate::cpu0 0.064642 # miss rate for ReadReq accesses
334 system.l2c.ReadReq_miss_rate::cpu1 0.064390 # miss rate for ReadReq accesses
335 system.l2c.ReadReq_miss_rate::cpu2 0.067264 # miss rate for ReadReq accesses
336 system.l2c.ReadReq_miss_rate::cpu3 0.063183 # miss rate for ReadReq accesses
337 system.l2c.ReadReq_miss_rate::cpu4 0.063546 # miss rate for ReadReq accesses
338 system.l2c.ReadReq_miss_rate::cpu5 0.065155 # miss rate for ReadReq accesses
339 system.l2c.ReadReq_miss_rate::cpu6 0.065371 # miss rate for ReadReq accesses
340 system.l2c.ReadReq_miss_rate::cpu7 0.061914 # miss rate for ReadReq accesses
341 system.l2c.ReadReq_miss_rate::total 0.064433 # miss rate for ReadReq accesses
342 system.l2c.UpgradeReq_miss_rate::cpu0 0.852349 # miss rate for UpgradeReq accesses
343 system.l2c.UpgradeReq_miss_rate::cpu1 0.850248 # miss rate for UpgradeReq accesses
344 system.l2c.UpgradeReq_miss_rate::cpu2 0.832152 # miss rate for UpgradeReq accesses
345 system.l2c.UpgradeReq_miss_rate::cpu3 0.839947 # miss rate for UpgradeReq accesses
346 system.l2c.UpgradeReq_miss_rate::cpu4 0.842731 # miss rate for UpgradeReq accesses
347 system.l2c.UpgradeReq_miss_rate::cpu5 0.838176 # miss rate for UpgradeReq accesses
348 system.l2c.UpgradeReq_miss_rate::cpu6 0.859111 # miss rate for UpgradeReq accesses
349 system.l2c.UpgradeReq_miss_rate::cpu7 0.839167 # miss rate for UpgradeReq accesses
350 system.l2c.UpgradeReq_miss_rate::total 0.844209 # miss rate for UpgradeReq accesses
351 system.l2c.ReadExReq_miss_rate::cpu0 0.699610 # miss rate for ReadExReq accesses
352 system.l2c.ReadExReq_miss_rate::cpu1 0.698226 # miss rate for ReadExReq accesses
353 system.l2c.ReadExReq_miss_rate::cpu2 0.703751 # miss rate for ReadExReq accesses
354 system.l2c.ReadExReq_miss_rate::cpu3 0.700564 # miss rate for ReadExReq accesses
355 system.l2c.ReadExReq_miss_rate::cpu4 0.702244 # miss rate for ReadExReq accesses
356 system.l2c.ReadExReq_miss_rate::cpu5 0.698134 # miss rate for ReadExReq accesses
357 system.l2c.ReadExReq_miss_rate::cpu6 0.694171 # miss rate for ReadExReq accesses
358 system.l2c.ReadExReq_miss_rate::cpu7 0.702412 # miss rate for ReadExReq accesses
359 system.l2c.ReadExReq_miss_rate::total 0.699887 # miss rate for ReadExReq accesses
360 system.l2c.demand_miss_rate::cpu0 0.285625 # miss rate for demand accesses
361 system.l2c.demand_miss_rate::cpu1 0.285924 # miss rate for demand accesses
362 system.l2c.demand_miss_rate::cpu2 0.289081 # miss rate for demand accesses
363 system.l2c.demand_miss_rate::cpu3 0.286286 # miss rate for demand accesses
364 system.l2c.demand_miss_rate::cpu4 0.288561 # miss rate for demand accesses
365 system.l2c.demand_miss_rate::cpu5 0.287806 # miss rate for demand accesses
366 system.l2c.demand_miss_rate::cpu6 0.286379 # miss rate for demand accesses
367 system.l2c.demand_miss_rate::cpu7 0.283141 # miss rate for demand accesses
368 system.l2c.demand_miss_rate::total 0.286602 # miss rate for demand accesses
369 system.l2c.overall_miss_rate::cpu0 0.285625 # miss rate for overall accesses
370 system.l2c.overall_miss_rate::cpu1 0.285924 # miss rate for overall accesses
371 system.l2c.overall_miss_rate::cpu2 0.289081 # miss rate for overall accesses
372 system.l2c.overall_miss_rate::cpu3 0.286286 # miss rate for overall accesses
373 system.l2c.overall_miss_rate::cpu4 0.288561 # miss rate for overall accesses
374 system.l2c.overall_miss_rate::cpu5 0.287806 # miss rate for overall accesses
375 system.l2c.overall_miss_rate::cpu6 0.286379 # miss rate for overall accesses
376 system.l2c.overall_miss_rate::cpu7 0.283141 # miss rate for overall accesses
377 system.l2c.overall_miss_rate::total 0.286602 # miss rate for overall accesses
378 system.l2c.ReadReq_avg_miss_latency::cpu0 58514.765101 # average ReadReq miss latency
379 system.l2c.ReadReq_avg_miss_latency::cpu1 59217.362046 # average ReadReq miss latency
380 system.l2c.ReadReq_avg_miss_latency::cpu2 58549.295775 # average ReadReq miss latency
381 system.l2c.ReadReq_avg_miss_latency::cpu3 59146.978022 # average ReadReq miss latency
382 system.l2c.ReadReq_avg_miss_latency::cpu4 59149.519890 # average ReadReq miss latency
383 system.l2c.ReadReq_avg_miss_latency::cpu5 58203.851262 # average ReadReq miss latency
384 system.l2c.ReadReq_avg_miss_latency::cpu6 58954.484605 # average ReadReq miss latency
385 system.l2c.ReadReq_avg_miss_latency::cpu7 58572.916667 # average ReadReq miss latency
386 system.l2c.ReadReq_avg_miss_latency::total 58785.233771 # average ReadReq miss latency
387 system.l2c.UpgradeReq_avg_miss_latency::cpu0 28934.908136 # average UpgradeReq miss latency
388 system.l2c.UpgradeReq_avg_miss_latency::cpu1 29593.633952 # average UpgradeReq miss latency
389 system.l2c.UpgradeReq_avg_miss_latency::cpu2 29233.368813 # average UpgradeReq miss latency
390 system.l2c.UpgradeReq_avg_miss_latency::cpu3 29231.758530 # average UpgradeReq miss latency
391 system.l2c.UpgradeReq_avg_miss_latency::cpu4 28710.925248 # average UpgradeReq miss latency
392 system.l2c.UpgradeReq_avg_miss_latency::cpu5 29077.333333 # average UpgradeReq miss latency
393 system.l2c.UpgradeReq_avg_miss_latency::cpu6 27707.449560 # average UpgradeReq miss latency
394 system.l2c.UpgradeReq_avg_miss_latency::cpu7 29435.322070 # average UpgradeReq miss latency
395 system.l2c.UpgradeReq_avg_miss_latency::total 28986.371716 # average UpgradeReq miss latency
396 system.l2c.ReadExReq_avg_miss_latency::cpu0 53445.399628 # average ReadExReq miss latency
397 system.l2c.ReadExReq_avg_miss_latency::cpu1 53428.389928 # average ReadExReq miss latency
398 system.l2c.ReadExReq_avg_miss_latency::cpu2 53478.265843 # average ReadExReq miss latency
399 system.l2c.ReadExReq_avg_miss_latency::cpu3 53430.411778 # average ReadExReq miss latency
400 system.l2c.ReadExReq_avg_miss_latency::cpu4 53324.737563 # average ReadExReq miss latency
401 system.l2c.ReadExReq_avg_miss_latency::cpu5 53544.883508 # average ReadExReq miss latency
402 system.l2c.ReadExReq_avg_miss_latency::cpu6 53442.079553 # average ReadExReq miss latency
403 system.l2c.ReadExReq_avg_miss_latency::cpu7 53490.951276 # average ReadExReq miss latency
404 system.l2c.ReadExReq_avg_miss_latency::total 53448.099078 # average ReadExReq miss latency
405 system.l2c.demand_avg_miss_latency::cpu0 54193.404635 # average overall miss latency
406 system.l2c.demand_avg_miss_latency::cpu1 54276.419558 # average overall miss latency
407 system.l2c.demand_avg_miss_latency::cpu2 54246.991460 # average overall miss latency
408 system.l2c.demand_avg_miss_latency::cpu3 54250.443350 # average overall miss latency
409 system.l2c.demand_avg_miss_latency::cpu4 54155.546860 # average overall miss latency
410 system.l2c.demand_avg_miss_latency::cpu5 54228.610407 # average overall miss latency
411 system.l2c.demand_avg_miss_latency::cpu6 54258.125248 # average overall miss latency
412 system.l2c.demand_avg_miss_latency::cpu7 54218.389662 # average overall miss latency
413 system.l2c.demand_avg_miss_latency::total 54228.470959 # average overall miss latency
414 system.l2c.overall_avg_miss_latency::cpu0 54193.404635 # average overall miss latency
415 system.l2c.overall_avg_miss_latency::cpu1 54276.419558 # average overall miss latency
416 system.l2c.overall_avg_miss_latency::cpu2 54246.991460 # average overall miss latency
417 system.l2c.overall_avg_miss_latency::cpu3 54250.443350 # average overall miss latency
418 system.l2c.overall_avg_miss_latency::cpu4 54155.546860 # average overall miss latency
419 system.l2c.overall_avg_miss_latency::cpu5 54228.610407 # average overall miss latency
420 system.l2c.overall_avg_miss_latency::cpu6 54258.125248 # average overall miss latency
421 system.l2c.overall_avg_miss_latency::cpu7 54218.389662 # average overall miss latency
422 system.l2c.overall_avg_miss_latency::total 54228.470959 # average overall miss latency
423 system.l2c.blocked_cycles::no_mshrs 6449 # number of cycles access was blocked
424 system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
425 system.l2c.blocked::no_mshrs 908 # number of cycles access was blocked
426 system.l2c.blocked::no_targets 0 # number of cycles access was blocked
427 system.l2c.avg_blocked_cycles::no_mshrs 7.102423 # average number of cycles each access was blocked
428 system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
429 system.l2c.fast_writes 0 # number of fast writes performed
430 system.l2c.cache_copies 0 # number of cache copies performed
431 system.l2c.writebacks::writebacks 6534 # number of writebacks
432 system.l2c.writebacks::total 6534 # number of writebacks
433 system.l2c.ReadReq_mshr_hits::cpu0 3 # number of ReadReq MSHR hits
434 system.l2c.ReadReq_mshr_hits::cpu1 4 # number of ReadReq MSHR hits
435 system.l2c.ReadReq_mshr_hits::cpu2 3 # number of ReadReq MSHR hits
436 system.l2c.ReadReq_mshr_hits::cpu3 2 # number of ReadReq MSHR hits
437 system.l2c.ReadReq_mshr_hits::cpu4 2 # number of ReadReq MSHR hits
438 system.l2c.ReadReq_mshr_hits::cpu5 2 # number of ReadReq MSHR hits
439 system.l2c.ReadReq_mshr_hits::cpu6 3 # number of ReadReq MSHR hits
440 system.l2c.ReadReq_mshr_hits::cpu7 4 # number of ReadReq MSHR hits
441 system.l2c.ReadReq_mshr_hits::total 23 # number of ReadReq MSHR hits
442 system.l2c.UpgradeReq_mshr_hits::cpu1 2 # number of UpgradeReq MSHR hits
443 system.l2c.UpgradeReq_mshr_hits::cpu3 1 # number of UpgradeReq MSHR hits
444 system.l2c.UpgradeReq_mshr_hits::total 3 # number of UpgradeReq MSHR hits
445 system.l2c.ReadExReq_mshr_hits::cpu0 3 # number of ReadExReq MSHR hits
446 system.l2c.ReadExReq_mshr_hits::cpu2 2 # number of ReadExReq MSHR hits
447 system.l2c.ReadExReq_mshr_hits::cpu4 1 # number of ReadExReq MSHR hits
448 system.l2c.ReadExReq_mshr_hits::cpu6 1 # number of ReadExReq MSHR hits
449 system.l2c.ReadExReq_mshr_hits::cpu7 1 # number of ReadExReq MSHR hits
450 system.l2c.ReadExReq_mshr_hits::total 8 # number of ReadExReq MSHR hits
451 system.l2c.demand_mshr_hits::cpu0 6 # number of demand (read+write) MSHR hits
452 system.l2c.demand_mshr_hits::cpu1 4 # number of demand (read+write) MSHR hits
453 system.l2c.demand_mshr_hits::cpu2 5 # number of demand (read+write) MSHR hits
454 system.l2c.demand_mshr_hits::cpu3 2 # number of demand (read+write) MSHR hits
455 system.l2c.demand_mshr_hits::cpu4 3 # number of demand (read+write) MSHR hits
456 system.l2c.demand_mshr_hits::cpu5 2 # number of demand (read+write) MSHR hits
457 system.l2c.demand_mshr_hits::cpu6 4 # number of demand (read+write) MSHR hits
458 system.l2c.demand_mshr_hits::cpu7 5 # number of demand (read+write) MSHR hits
459 system.l2c.demand_mshr_hits::total 31 # number of demand (read+write) MSHR hits
460 system.l2c.overall_mshr_hits::cpu0 6 # number of overall MSHR hits
461 system.l2c.overall_mshr_hits::cpu1 4 # number of overall MSHR hits
462 system.l2c.overall_mshr_hits::cpu2 5 # number of overall MSHR hits
463 system.l2c.overall_mshr_hits::cpu3 2 # number of overall MSHR hits
464 system.l2c.overall_mshr_hits::cpu4 3 # number of overall MSHR hits
465 system.l2c.overall_mshr_hits::cpu5 2 # number of overall MSHR hits
466 system.l2c.overall_mshr_hits::cpu6 4 # number of overall MSHR hits
467 system.l2c.overall_mshr_hits::cpu7 5 # number of overall MSHR hits
468 system.l2c.overall_mshr_hits::total 31 # number of overall MSHR hits
469 system.l2c.ReadReq_mshr_misses::cpu0 742 # number of ReadReq MSHR misses
470 system.l2c.ReadReq_mshr_misses::cpu1 739 # number of ReadReq MSHR misses
471 system.l2c.ReadReq_mshr_misses::cpu2 778 # number of ReadReq MSHR misses
472 system.l2c.ReadReq_mshr_misses::cpu3 726 # number of ReadReq MSHR misses
473 system.l2c.ReadReq_mshr_misses::cpu4 727 # number of ReadReq MSHR misses
474 system.l2c.ReadReq_mshr_misses::cpu5 751 # number of ReadReq MSHR misses
475 system.l2c.ReadReq_mshr_misses::cpu6 744 # number of ReadReq MSHR misses
476 system.l2c.ReadReq_mshr_misses::cpu7 716 # number of ReadReq MSHR misses
477 system.l2c.ReadReq_mshr_misses::total 5923 # number of ReadReq MSHR misses
478 system.l2c.UpgradeReq_mshr_misses::cpu0 1905 # number of UpgradeReq MSHR misses
479 system.l2c.UpgradeReq_mshr_misses::cpu1 1883 # number of UpgradeReq MSHR misses
480 system.l2c.UpgradeReq_mshr_misses::cpu2 1879 # number of UpgradeReq MSHR misses
481 system.l2c.UpgradeReq_mshr_misses::cpu3 1904 # number of UpgradeReq MSHR misses
482 system.l2c.UpgradeReq_mshr_misses::cpu4 1913 # number of UpgradeReq MSHR misses
483 system.l2c.UpgradeReq_mshr_misses::cpu5 1875 # number of UpgradeReq MSHR misses
484 system.l2c.UpgradeReq_mshr_misses::cpu6 1933 # number of UpgradeReq MSHR misses
485 system.l2c.UpgradeReq_mshr_misses::cpu7 1894 # number of UpgradeReq MSHR misses
486 system.l2c.UpgradeReq_mshr_misses::total 15186 # number of UpgradeReq MSHR misses
487 system.l2c.ReadExReq_mshr_misses::cpu0 4301 # number of ReadExReq MSHR misses
488 system.l2c.ReadExReq_mshr_misses::cpu1 4329 # number of ReadExReq MSHR misses
489 system.l2c.ReadExReq_mshr_misses::cpu2 4369 # number of ReadExReq MSHR misses
490 system.l2c.ReadExReq_mshr_misses::cpu3 4347 # number of ReadExReq MSHR misses
491 system.l2c.ReadExReq_mshr_misses::cpu4 4381 # number of ReadExReq MSHR misses
492 system.l2c.ReadExReq_mshr_misses::cpu5 4378 # number of ReadExReq MSHR misses
493 system.l2c.ReadExReq_mshr_misses::cpu6 4298 # number of ReadExReq MSHR misses
494 system.l2c.ReadExReq_mshr_misses::cpu7 4309 # number of ReadExReq MSHR misses
495 system.l2c.ReadExReq_mshr_misses::total 34712 # number of ReadExReq MSHR misses
496 system.l2c.demand_mshr_misses::cpu0 5043 # number of demand (read+write) MSHR misses
497 system.l2c.demand_mshr_misses::cpu1 5068 # number of demand (read+write) MSHR misses
498 system.l2c.demand_mshr_misses::cpu2 5147 # number of demand (read+write) MSHR misses
499 system.l2c.demand_mshr_misses::cpu3 5073 # number of demand (read+write) MSHR misses
500 system.l2c.demand_mshr_misses::cpu4 5108 # number of demand (read+write) MSHR misses
501 system.l2c.demand_mshr_misses::cpu5 5129 # number of demand (read+write) MSHR misses
502 system.l2c.demand_mshr_misses::cpu6 5042 # number of demand (read+write) MSHR misses
503 system.l2c.demand_mshr_misses::cpu7 5025 # number of demand (read+write) MSHR misses
504 system.l2c.demand_mshr_misses::total 40635 # number of demand (read+write) MSHR misses
505 system.l2c.overall_mshr_misses::cpu0 5043 # number of overall MSHR misses
506 system.l2c.overall_mshr_misses::cpu1 5068 # number of overall MSHR misses
507 system.l2c.overall_mshr_misses::cpu2 5147 # number of overall MSHR misses
508 system.l2c.overall_mshr_misses::cpu3 5073 # number of overall MSHR misses
509 system.l2c.overall_mshr_misses::cpu4 5108 # number of overall MSHR misses
510 system.l2c.overall_mshr_misses::cpu5 5129 # number of overall MSHR misses
511 system.l2c.overall_mshr_misses::cpu6 5042 # number of overall MSHR misses
512 system.l2c.overall_mshr_misses::cpu7 5025 # number of overall MSHR misses
513 system.l2c.overall_mshr_misses::total 40635 # number of overall MSHR misses
514 system.l2c.ReadReq_mshr_miss_latency::cpu0 34436500 # number of ReadReq MSHR miss cycles
515 system.l2c.ReadReq_mshr_miss_latency::cpu1 34879500 # number of ReadReq MSHR miss cycles
516 system.l2c.ReadReq_mshr_miss_latency::cpu2 36206000 # number of ReadReq MSHR miss cycles
517 system.l2c.ReadReq_mshr_miss_latency::cpu3 34201000 # number of ReadReq MSHR miss cycles
518 system.l2c.ReadReq_mshr_miss_latency::cpu4 34228500 # number of ReadReq MSHR miss cycles
519 system.l2c.ReadReq_mshr_miss_latency::cpu5 34696500 # number of ReadReq MSHR miss cycles
520 system.l2c.ReadReq_mshr_miss_latency::cpu6 34883500 # number of ReadReq MSHR miss cycles
521 system.l2c.ReadReq_mshr_miss_latency::cpu7 33321000 # number of ReadReq MSHR miss cycles
522 system.l2c.ReadReq_mshr_miss_latency::total 276852500 # number of ReadReq MSHR miss cycles
523 system.l2c.UpgradeReq_mshr_miss_latency::cpu0 77532500 # number of UpgradeReq MSHR miss cycles
524 system.l2c.UpgradeReq_mshr_miss_latency::cpu1 76774000 # number of UpgradeReq MSHR miss cycles
525 system.l2c.UpgradeReq_mshr_miss_latency::cpu2 76435500 # number of UpgradeReq MSHR miss cycles
526 system.l2c.UpgradeReq_mshr_miss_latency::cpu3 77640000 # number of UpgradeReq MSHR miss cycles
527 system.l2c.UpgradeReq_mshr_miss_latency::cpu4 77802000 # number of UpgradeReq MSHR miss cycles
528 system.l2c.UpgradeReq_mshr_miss_latency::cpu5 76297000 # number of UpgradeReq MSHR miss cycles
529 system.l2c.UpgradeReq_mshr_miss_latency::cpu6 78806000 # number of UpgradeReq MSHR miss cycles
530 system.l2c.UpgradeReq_mshr_miss_latency::cpu7 77127500 # number of UpgradeReq MSHR miss cycles
531 system.l2c.UpgradeReq_mshr_miss_latency::total 618414500 # number of UpgradeReq MSHR miss cycles
532 system.l2c.ReadExReq_mshr_miss_latency::cpu0 177611500 # number of ReadExReq MSHR miss cycles
533 system.l2c.ReadExReq_mshr_miss_latency::cpu1 178666500 # number of ReadExReq MSHR miss cycles
534 system.l2c.ReadExReq_mshr_miss_latency::cpu2 180593500 # number of ReadExReq MSHR miss cycles
535 system.l2c.ReadExReq_mshr_miss_latency::cpu3 179431000 # number of ReadExReq MSHR miss cycles
536 system.l2c.ReadExReq_mshr_miss_latency::cpu4 180375000 # number of ReadExReq MSHR miss cycles
537 system.l2c.ReadExReq_mshr_miss_latency::cpu5 181189000 # number of ReadExReq MSHR miss cycles
538 system.l2c.ReadExReq_mshr_miss_latency::cpu6 177424500 # number of ReadExReq MSHR miss cycles
539 system.l2c.ReadExReq_mshr_miss_latency::cpu7 178121500 # number of ReadExReq MSHR miss cycles
540 system.l2c.ReadExReq_mshr_miss_latency::total 1433412500 # number of ReadExReq MSHR miss cycles
541 system.l2c.demand_mshr_miss_latency::cpu0 212048000 # number of demand (read+write) MSHR miss cycles
542 system.l2c.demand_mshr_miss_latency::cpu1 213546000 # number of demand (read+write) MSHR miss cycles
543 system.l2c.demand_mshr_miss_latency::cpu2 216799500 # number of demand (read+write) MSHR miss cycles
544 system.l2c.demand_mshr_miss_latency::cpu3 213632000 # number of demand (read+write) MSHR miss cycles
545 system.l2c.demand_mshr_miss_latency::cpu4 214603500 # number of demand (read+write) MSHR miss cycles
546 system.l2c.demand_mshr_miss_latency::cpu5 215885500 # number of demand (read+write) MSHR miss cycles
547 system.l2c.demand_mshr_miss_latency::cpu6 212308000 # number of demand (read+write) MSHR miss cycles
548 system.l2c.demand_mshr_miss_latency::cpu7 211442500 # number of demand (read+write) MSHR miss cycles
549 system.l2c.demand_mshr_miss_latency::total 1710265000 # number of demand (read+write) MSHR miss cycles
550 system.l2c.overall_mshr_miss_latency::cpu0 212048000 # number of overall MSHR miss cycles
551 system.l2c.overall_mshr_miss_latency::cpu1 213546000 # number of overall MSHR miss cycles
552 system.l2c.overall_mshr_miss_latency::cpu2 216799500 # number of overall MSHR miss cycles
553 system.l2c.overall_mshr_miss_latency::cpu3 213632000 # number of overall MSHR miss cycles
554 system.l2c.overall_mshr_miss_latency::cpu4 214603500 # number of overall MSHR miss cycles
555 system.l2c.overall_mshr_miss_latency::cpu5 215885500 # number of overall MSHR miss cycles
556 system.l2c.overall_mshr_miss_latency::cpu6 212308000 # number of overall MSHR miss cycles
557 system.l2c.overall_mshr_miss_latency::cpu7 211442500 # number of overall MSHR miss cycles
558 system.l2c.overall_mshr_miss_latency::total 1710265000 # number of overall MSHR miss cycles
559 system.l2c.ReadReq_mshr_uncacheable_latency::cpu0 408522500 # number of ReadReq MSHR uncacheable cycles
560 system.l2c.ReadReq_mshr_uncacheable_latency::cpu1 408718000 # number of ReadReq MSHR uncacheable cycles
561 system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 409944000 # number of ReadReq MSHR uncacheable cycles
562 system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 402597000 # number of ReadReq MSHR uncacheable cycles
563 system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 406388000 # number of ReadReq MSHR uncacheable cycles
564 system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 405037500 # number of ReadReq MSHR uncacheable cycles
565 system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 409992000 # number of ReadReq MSHR uncacheable cycles
566 system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 408869000 # number of ReadReq MSHR uncacheable cycles
567 system.l2c.ReadReq_mshr_uncacheable_latency::total 3260068000 # number of ReadReq MSHR uncacheable cycles
568 system.l2c.WriteReq_mshr_uncacheable_latency::cpu0 227084000 # number of WriteReq MSHR uncacheable cycles
569 system.l2c.WriteReq_mshr_uncacheable_latency::cpu1 222076000 # number of WriteReq MSHR uncacheable cycles
570 system.l2c.WriteReq_mshr_uncacheable_latency::cpu2 221597500 # number of WriteReq MSHR uncacheable cycles
571 system.l2c.WriteReq_mshr_uncacheable_latency::cpu3 223921500 # number of WriteReq MSHR uncacheable cycles
572 system.l2c.WriteReq_mshr_uncacheable_latency::cpu4 226980000 # number of WriteReq MSHR uncacheable cycles
573 system.l2c.WriteReq_mshr_uncacheable_latency::cpu5 223544500 # number of WriteReq MSHR uncacheable cycles
574 system.l2c.WriteReq_mshr_uncacheable_latency::cpu6 219891000 # number of WriteReq MSHR uncacheable cycles
575 system.l2c.WriteReq_mshr_uncacheable_latency::cpu7 221144500 # number of WriteReq MSHR uncacheable cycles
576 system.l2c.WriteReq_mshr_uncacheable_latency::total 1786239000 # number of WriteReq MSHR uncacheable cycles
577 system.l2c.overall_mshr_uncacheable_latency::cpu0 635606500 # number of overall MSHR uncacheable cycles
578 system.l2c.overall_mshr_uncacheable_latency::cpu1 630794000 # number of overall MSHR uncacheable cycles
579 system.l2c.overall_mshr_uncacheable_latency::cpu2 631541500 # number of overall MSHR uncacheable cycles
580 system.l2c.overall_mshr_uncacheable_latency::cpu3 626518500 # number of overall MSHR uncacheable cycles
581 system.l2c.overall_mshr_uncacheable_latency::cpu4 633368000 # number of overall MSHR uncacheable cycles
582 system.l2c.overall_mshr_uncacheable_latency::cpu5 628582000 # number of overall MSHR uncacheable cycles
583 system.l2c.overall_mshr_uncacheable_latency::cpu6 629883000 # number of overall MSHR uncacheable cycles
584 system.l2c.overall_mshr_uncacheable_latency::cpu7 630013500 # number of overall MSHR uncacheable cycles
585 system.l2c.overall_mshr_uncacheable_latency::total 5046307000 # number of overall MSHR uncacheable cycles
586 system.l2c.ReadReq_mshr_miss_rate::cpu0 0.064382 # mshr miss rate for ReadReq accesses
587 system.l2c.ReadReq_mshr_miss_rate::cpu1 0.064044 # mshr miss rate for ReadReq accesses
588 system.l2c.ReadReq_mshr_miss_rate::cpu2 0.067005 # mshr miss rate for ReadReq accesses
589 system.l2c.ReadReq_mshr_miss_rate::cpu3 0.063010 # mshr miss rate for ReadReq accesses
590 system.l2c.ReadReq_mshr_miss_rate::cpu4 0.063372 # mshr miss rate for ReadReq accesses
591 system.l2c.ReadReq_mshr_miss_rate::cpu5 0.064982 # mshr miss rate for ReadReq accesses
592 system.l2c.ReadReq_mshr_miss_rate::cpu6 0.065109 # mshr miss rate for ReadReq accesses
593 system.l2c.ReadReq_mshr_miss_rate::cpu7 0.061570 # mshr miss rate for ReadReq accesses
594 system.l2c.ReadReq_mshr_miss_rate::total 0.064184 # mshr miss rate for ReadReq accesses
595 system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.852349 # mshr miss rate for UpgradeReq accesses
596 system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.849346 # mshr miss rate for UpgradeReq accesses
597 system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.832152 # mshr miss rate for UpgradeReq accesses
598 system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.839506 # mshr miss rate for UpgradeReq accesses
599 system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.842731 # mshr miss rate for UpgradeReq accesses
600 system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.838176 # mshr miss rate for UpgradeReq accesses
601 system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.859111 # mshr miss rate for UpgradeReq accesses
602 system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.839167 # mshr miss rate for UpgradeReq accesses
603 system.l2c.UpgradeReq_mshr_miss_rate::total 0.844042 # mshr miss rate for UpgradeReq accesses
604 system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.699122 # mshr miss rate for ReadExReq accesses
605 system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.698226 # mshr miss rate for ReadExReq accesses
606 system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.703429 # mshr miss rate for ReadExReq accesses
607 system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.700564 # mshr miss rate for ReadExReq accesses
608 system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.702083 # mshr miss rate for ReadExReq accesses
609 system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.698134 # mshr miss rate for ReadExReq accesses
610 system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.694009 # mshr miss rate for ReadExReq accesses
611 system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.702249 # mshr miss rate for ReadExReq accesses
612 system.l2c.ReadExReq_mshr_miss_rate::total 0.699726 # mshr miss rate for ReadExReq accesses
613 system.l2c.demand_mshr_miss_rate::cpu0 0.285286 # mshr miss rate for demand accesses
614 system.l2c.demand_mshr_miss_rate::cpu1 0.285698 # mshr miss rate for demand accesses
615 system.l2c.demand_mshr_miss_rate::cpu2 0.288800 # mshr miss rate for demand accesses
616 system.l2c.demand_mshr_miss_rate::cpu3 0.286174 # mshr miss rate for demand accesses
617 system.l2c.demand_mshr_miss_rate::cpu4 0.288392 # mshr miss rate for demand accesses
618 system.l2c.demand_mshr_miss_rate::cpu5 0.287694 # mshr miss rate for demand accesses
619 system.l2c.demand_mshr_miss_rate::cpu6 0.286152 # mshr miss rate for demand accesses
620 system.l2c.demand_mshr_miss_rate::cpu7 0.282860 # mshr miss rate for demand accesses
621 system.l2c.demand_mshr_miss_rate::total 0.286384 # mshr miss rate for demand accesses
622 system.l2c.overall_mshr_miss_rate::cpu0 0.285286 # mshr miss rate for overall accesses
623 system.l2c.overall_mshr_miss_rate::cpu1 0.285698 # mshr miss rate for overall accesses
624 system.l2c.overall_mshr_miss_rate::cpu2 0.288800 # mshr miss rate for overall accesses
625 system.l2c.overall_mshr_miss_rate::cpu3 0.286174 # mshr miss rate for overall accesses
626 system.l2c.overall_mshr_miss_rate::cpu4 0.288392 # mshr miss rate for overall accesses
627 system.l2c.overall_mshr_miss_rate::cpu5 0.287694 # mshr miss rate for overall accesses
628 system.l2c.overall_mshr_miss_rate::cpu6 0.286152 # mshr miss rate for overall accesses
629 system.l2c.overall_mshr_miss_rate::cpu7 0.282860 # mshr miss rate for overall accesses
630 system.l2c.overall_mshr_miss_rate::total 0.286384 # mshr miss rate for overall accesses
631 system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 46410.377358 # average ReadReq mshr miss latency
632 system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 47198.240866 # average ReadReq mshr miss latency
633 system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 46537.275064 # average ReadReq mshr miss latency
634 system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 47108.815427 # average ReadReq mshr miss latency
635 system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 47081.843191 # average ReadReq mshr miss latency
636 system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 46200.399467 # average ReadReq mshr miss latency
637 system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 46886.424731 # average ReadReq mshr miss latency
638 system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 46537.709497 # average ReadReq mshr miss latency
639 system.l2c.ReadReq_avg_mshr_miss_latency::total 46741.938207 # average ReadReq mshr miss latency
640 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 40699.475066 # average UpgradeReq mshr miss latency
641 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 40772.172066 # average UpgradeReq mshr miss latency
642 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 40678.818520 # average UpgradeReq mshr miss latency
643 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 40777.310924 # average UpgradeReq mshr miss latency
644 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 40670.151594 # average UpgradeReq mshr miss latency
645 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 40691.733333 # average UpgradeReq mshr miss latency
646 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 40768.753233 # average UpgradeReq mshr miss latency
647 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 40722.016895 # average UpgradeReq mshr miss latency
648 system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40722.672198 # average UpgradeReq mshr miss latency
649 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 41295.396419 # average ReadExReq mshr miss latency
650 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 41272.002772 # average ReadExReq mshr miss latency
651 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 41335.202564 # average ReadExReq mshr miss latency
652 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 41276.972625 # average ReadExReq mshr miss latency
653 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 41172.106825 # average ReadExReq mshr miss latency
654 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 41386.249429 # average ReadExReq mshr miss latency
655 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 41280.711959 # average ReadExReq mshr miss latency
656 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 41337.085171 # average ReadExReq mshr miss latency
657 system.l2c.ReadExReq_avg_mshr_miss_latency::total 41294.437082 # average ReadExReq mshr miss latency
658 system.l2c.demand_avg_mshr_miss_latency::cpu0 42047.987309 # average overall mshr miss latency
659 system.l2c.demand_avg_mshr_miss_latency::cpu1 42136.148382 # average overall mshr miss latency
660 system.l2c.demand_avg_mshr_miss_latency::cpu2 42121.527103 # average overall mshr miss latency
661 system.l2c.demand_avg_mshr_miss_latency::cpu3 42111.571062 # average overall mshr miss latency
662 system.l2c.demand_avg_mshr_miss_latency::cpu4 42013.214565 # average overall mshr miss latency
663 system.l2c.demand_avg_mshr_miss_latency::cpu5 42091.148372 # average overall mshr miss latency
664 system.l2c.demand_avg_mshr_miss_latency::cpu6 42107.893693 # average overall mshr miss latency
665 system.l2c.demand_avg_mshr_miss_latency::cpu7 42078.109453 # average overall mshr miss latency
666 system.l2c.demand_avg_mshr_miss_latency::total 42088.470530 # average overall mshr miss latency
667 system.l2c.overall_avg_mshr_miss_latency::cpu0 42047.987309 # average overall mshr miss latency
668 system.l2c.overall_avg_mshr_miss_latency::cpu1 42136.148382 # average overall mshr miss latency
669 system.l2c.overall_avg_mshr_miss_latency::cpu2 42121.527103 # average overall mshr miss latency
670 system.l2c.overall_avg_mshr_miss_latency::cpu3 42111.571062 # average overall mshr miss latency
671 system.l2c.overall_avg_mshr_miss_latency::cpu4 42013.214565 # average overall mshr miss latency
672 system.l2c.overall_avg_mshr_miss_latency::cpu5 42091.148372 # average overall mshr miss latency
673 system.l2c.overall_avg_mshr_miss_latency::cpu6 42107.893693 # average overall mshr miss latency
674 system.l2c.overall_avg_mshr_miss_latency::cpu7 42078.109453 # average overall mshr miss latency
675 system.l2c.overall_avg_mshr_miss_latency::total 42088.470530 # average overall mshr miss latency
676 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency
677 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency
678 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency
679 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3 inf # average ReadReq mshr uncacheable latency
680 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4 inf # average ReadReq mshr uncacheable latency
681 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5 inf # average ReadReq mshr uncacheable latency
682 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6 inf # average ReadReq mshr uncacheable latency
683 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7 inf # average ReadReq mshr uncacheable latency
684 system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
685 system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0 inf # average WriteReq mshr uncacheable latency
686 system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1 inf # average WriteReq mshr uncacheable latency
687 system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2 inf # average WriteReq mshr uncacheable latency
688 system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3 inf # average WriteReq mshr uncacheable latency
689 system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu4 inf # average WriteReq mshr uncacheable latency
690 system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu5 inf # average WriteReq mshr uncacheable latency
691 system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu6 inf # average WriteReq mshr uncacheable latency
692 system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu7 inf # average WriteReq mshr uncacheable latency
693 system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
694 system.l2c.overall_avg_mshr_uncacheable_latency::cpu0 inf # average overall mshr uncacheable latency
695 system.l2c.overall_avg_mshr_uncacheable_latency::cpu1 inf # average overall mshr uncacheable latency
696 system.l2c.overall_avg_mshr_uncacheable_latency::cpu2 inf # average overall mshr uncacheable latency
697 system.l2c.overall_avg_mshr_uncacheable_latency::cpu3 inf # average overall mshr uncacheable latency
698 system.l2c.overall_avg_mshr_uncacheable_latency::cpu4 inf # average overall mshr uncacheable latency
699 system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 inf # average overall mshr uncacheable latency
700 system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 inf # average overall mshr uncacheable latency
701 system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 inf # average overall mshr uncacheable latency
702 system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
703 system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
704 system.funcbus.throughput 0 # Throughput (bytes/s)
705 system.funcbus.data_through_bus 0 # Total data (bytes)
706 system.toL2Bus.snoop_filter.tot_requests 548567 # Total number of requests made to the snoop filter.
707 system.toL2Bus.snoop_filter.hit_single_requests 252509 # Number of requests hitting in the snoop filter with a single holder of the requested data.
708 system.toL2Bus.snoop_filter.hit_multi_requests 294010 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
709 system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
710 system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
711 system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
712 system.toL2Bus.throughput 22759385654 # Throughput (bytes/s)
713 system.toL2Bus.trans_dist::ReadReq 368934 # Transaction distribution
714 system.toL2Bus.trans_dist::ReadResp 368931 # Transaction distribution
715 system.toL2Bus.trans_dist::WriteReq 42843 # Transaction distribution
716 system.toL2Bus.trans_dist::WriteResp 42841 # Transaction distribution
717 system.toL2Bus.trans_dist::Writeback 74514 # Transaction distribution
718 system.toL2Bus.trans_dist::UpgradeReq 28540 # Transaction distribution
719 system.toL2Bus.trans_dist::UpgradeResp 28540 # Transaction distribution
720 system.toL2Bus.trans_dist::ReadExReq 155707 # Transaction distribution
721 system.toL2Bus.trans_dist::ReadExResp 155704 # Transaction distribution
722 system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 118962 # Packet count per connected master and slave (bytes)
723 system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 119173 # Packet count per connected master and slave (bytes)
724 system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 119464 # Packet count per connected master and slave (bytes)
725 system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 119154 # Packet count per connected master and slave (bytes)
726 system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 118978 # Packet count per connected master and slave (bytes)
727 system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 119360 # Packet count per connected master and slave (bytes)
728 system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 119013 # Packet count per connected master and slave (bytes)
729 system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 118881 # Packet count per connected master and slave (bytes)
730 system.toL2Bus.pkt_count::total 952985 # Packet count per connected master and slave (bytes)
731 system.toL2Bus.tot_pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1734762 # Cumulative packet size per connected master and slave (bytes)
732 system.toL2Bus.tot_pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1749843 # Cumulative packet size per connected master and slave (bytes)
733 system.toL2Bus.tot_pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1754305 # Cumulative packet size per connected master and slave (bytes)
734 system.toL2Bus.tot_pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1751569 # Cumulative packet size per connected master and slave (bytes)
735 system.toL2Bus.tot_pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1739334 # Cumulative packet size per connected master and slave (bytes)
736 system.toL2Bus.tot_pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1759819 # Cumulative packet size per connected master and slave (bytes)
737 system.toL2Bus.tot_pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1742411 # Cumulative packet size per connected master and slave (bytes)
738 system.toL2Bus.tot_pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1740191 # Cumulative packet size per connected master and slave (bytes)
739 system.toL2Bus.tot_pkt_size::total 13972234 # Cumulative packet size per connected master and slave (bytes)
740 system.toL2Bus.data_through_bus 13972234 # Total data (bytes)
741 system.toL2Bus.snoop_data_through_bus 19393344 # Total snoop data (bytes)
742 system.toL2Bus.snoops_through_bus 313569 # Total snoops (count)
743 system.toL2Bus.snoop_fanout::samples 548567 # Request fanout histogram
744 system.toL2Bus.snoop_fanout::mean 1.700997 # Request fanout histogram
745 system.toL2Bus.snoop_fanout::stdev 1.184770 # Request fanout histogram
746 system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
747 system.toL2Bus.snoop_fanout::0 51420 9.37% 9.37% # Request fanout histogram
748 system.toL2Bus.snoop_fanout::1 243442 44.38% 53.75% # Request fanout histogram
749 system.toL2Bus.snoop_fanout::2 138727 25.29% 79.04% # Request fanout histogram
750 system.toL2Bus.snoop_fanout::3 68606 12.51% 91.55% # Request fanout histogram
751 system.toL2Bus.snoop_fanout::4 30441 5.55% 97.10% # Request fanout histogram
752 system.toL2Bus.snoop_fanout::5 11622 2.12% 99.21% # Request fanout histogram
753 system.toL2Bus.snoop_fanout::6 3640 0.66% 99.88% # Request fanout histogram
754 system.toL2Bus.snoop_fanout::7 669 0.12% 100.00% # Request fanout histogram
755 system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram
756 system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
757 system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
758 system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram
759 system.toL2Bus.snoop_fanout::total 548567 # Request fanout histogram
760 system.toL2Bus.reqLayer0.occupancy 1466016000 # Layer occupancy (ticks)
761 system.toL2Bus.reqLayer0.utilization 100.0 # Layer utilization (%)
762 system.toL2Bus.respLayer0.occupancy 156116317 # Layer occupancy (ticks)
763 system.toL2Bus.respLayer0.utilization 10.6 # Layer utilization (%)
764 system.toL2Bus.respLayer1.occupancy 156768205 # Layer occupancy (ticks)
765 system.toL2Bus.respLayer1.utilization 10.7 # Layer utilization (%)
766 system.toL2Bus.respLayer2.occupancy 156913339 # Layer occupancy (ticks)
767 system.toL2Bus.respLayer2.utilization 10.7 # Layer utilization (%)
768 system.toL2Bus.respLayer3.occupancy 156965244 # Layer occupancy (ticks)
769 system.toL2Bus.respLayer3.utilization 10.7 # Layer utilization (%)
770 system.toL2Bus.respLayer4.occupancy 156103724 # Layer occupancy (ticks)
771 system.toL2Bus.respLayer4.utilization 10.6 # Layer utilization (%)
772 system.toL2Bus.respLayer5.occupancy 156986709 # Layer occupancy (ticks)
773 system.toL2Bus.respLayer5.utilization 10.7 # Layer utilization (%)
774 system.toL2Bus.respLayer6.occupancy 156696078 # Layer occupancy (ticks)
775 system.toL2Bus.respLayer6.utilization 10.7 # Layer utilization (%)
776 system.toL2Bus.respLayer7.occupancy 156271715 # Layer occupancy (ticks)
777 system.toL2Bus.respLayer7.utilization 10.7 # Layer utilization (%)
778 system.cpu0.num_reads 99418 # number of read accesses completed
779 system.cpu0.num_writes 53245 # number of write accesses completed
780 system.cpu0.num_copies 0 # number of copy accesses completed
781 system.cpu0.l1c.tags.replacements 22099 # number of replacements
782 system.cpu0.l1c.tags.tagsinuse 397.065512 # Cycle average of tags in use
783 system.cpu0.l1c.tags.total_refs 13209 # Total number of references to valid blocks.
784 system.cpu0.l1c.tags.sampled_refs 22488 # Sample count of references to valid blocks.
785 system.cpu0.l1c.tags.avg_refs 0.587380 # Average number of references to valid blocks.
786 system.cpu0.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
787 system.cpu0.l1c.tags.occ_blocks::cpu0 397.065512 # Average occupied blocks per requestor
788 system.cpu0.l1c.tags.occ_percent::cpu0 0.775519 # Average percentage of cache occupancy
789 system.cpu0.l1c.tags.occ_percent::total 0.775519 # Average percentage of cache occupancy
790 system.cpu0.l1c.tags.occ_task_id_blocks::1024 389 # Occupied blocks per task id
791 system.cpu0.l1c.tags.age_task_id_blocks_1024::0 259 # Occupied blocks per task id
792 system.cpu0.l1c.tags.age_task_id_blocks_1024::1 130 # Occupied blocks per task id
793 system.cpu0.l1c.tags.occ_task_id_percent::1024 0.759766 # Percentage of cache occupancy per task id
794 system.cpu0.l1c.tags.tag_accesses 330123 # Number of tag accesses
795 system.cpu0.l1c.tags.data_accesses 330123 # Number of data accesses
796 system.cpu0.l1c.ReadReq_hits::cpu0 8700 # number of ReadReq hits
797 system.cpu0.l1c.ReadReq_hits::total 8700 # number of ReadReq hits
798 system.cpu0.l1c.WriteReq_hits::cpu0 1042 # number of WriteReq hits
799 system.cpu0.l1c.WriteReq_hits::total 1042 # number of WriteReq hits
800 system.cpu0.l1c.demand_hits::cpu0 9742 # number of demand (read+write) hits
801 system.cpu0.l1c.demand_hits::total 9742 # number of demand (read+write) hits
802 system.cpu0.l1c.overall_hits::cpu0 9742 # number of overall hits
803 system.cpu0.l1c.overall_hits::total 9742 # number of overall hits
804 system.cpu0.l1c.ReadReq_misses::cpu0 35979 # number of ReadReq misses
805 system.cpu0.l1c.ReadReq_misses::total 35979 # number of ReadReq misses
806 system.cpu0.l1c.WriteReq_misses::cpu0 22956 # number of WriteReq misses
807 system.cpu0.l1c.WriteReq_misses::total 22956 # number of WriteReq misses
808 system.cpu0.l1c.demand_misses::cpu0 58935 # number of demand (read+write) misses
809 system.cpu0.l1c.demand_misses::total 58935 # number of demand (read+write) misses
810 system.cpu0.l1c.overall_misses::cpu0 58935 # number of overall misses
811 system.cpu0.l1c.overall_misses::total 58935 # number of overall misses
812 system.cpu0.l1c.ReadReq_miss_latency::cpu0 2431275055 # number of ReadReq miss cycles
813 system.cpu0.l1c.ReadReq_miss_latency::total 2431275055 # number of ReadReq miss cycles
814 system.cpu0.l1c.WriteReq_miss_latency::cpu0 1798190271 # number of WriteReq miss cycles
815 system.cpu0.l1c.WriteReq_miss_latency::total 1798190271 # number of WriteReq miss cycles
816 system.cpu0.l1c.demand_miss_latency::cpu0 4229465326 # number of demand (read+write) miss cycles
817 system.cpu0.l1c.demand_miss_latency::total 4229465326 # number of demand (read+write) miss cycles
818 system.cpu0.l1c.overall_miss_latency::cpu0 4229465326 # number of overall miss cycles
819 system.cpu0.l1c.overall_miss_latency::total 4229465326 # number of overall miss cycles
820 system.cpu0.l1c.ReadReq_accesses::cpu0 44679 # number of ReadReq accesses(hits+misses)
821 system.cpu0.l1c.ReadReq_accesses::total 44679 # number of ReadReq accesses(hits+misses)
822 system.cpu0.l1c.WriteReq_accesses::cpu0 23998 # number of WriteReq accesses(hits+misses)
823 system.cpu0.l1c.WriteReq_accesses::total 23998 # number of WriteReq accesses(hits+misses)
824 system.cpu0.l1c.demand_accesses::cpu0 68677 # number of demand (read+write) accesses
825 system.cpu0.l1c.demand_accesses::total 68677 # number of demand (read+write) accesses
826 system.cpu0.l1c.overall_accesses::cpu0 68677 # number of overall (read+write) accesses
827 system.cpu0.l1c.overall_accesses::total 68677 # number of overall (read+write) accesses
828 system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.805278 # miss rate for ReadReq accesses
829 system.cpu0.l1c.ReadReq_miss_rate::total 0.805278 # miss rate for ReadReq accesses
830 system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.956580 # miss rate for WriteReq accesses
831 system.cpu0.l1c.WriteReq_miss_rate::total 0.956580 # miss rate for WriteReq accesses
832 system.cpu0.l1c.demand_miss_rate::cpu0 0.858148 # miss rate for demand accesses
833 system.cpu0.l1c.demand_miss_rate::total 0.858148 # miss rate for demand accesses
834 system.cpu0.l1c.overall_miss_rate::cpu0 0.858148 # miss rate for overall accesses
835 system.cpu0.l1c.overall_miss_rate::total 0.858148 # miss rate for overall accesses
836 system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 67574.836849 # average ReadReq miss latency
837 system.cpu0.l1c.ReadReq_avg_miss_latency::total 67574.836849 # average ReadReq miss latency
838 system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 78332.038291 # average WriteReq miss latency
839 system.cpu0.l1c.WriteReq_avg_miss_latency::total 78332.038291 # average WriteReq miss latency
840 system.cpu0.l1c.demand_avg_miss_latency::cpu0 71764.916026 # average overall miss latency
841 system.cpu0.l1c.demand_avg_miss_latency::total 71764.916026 # average overall miss latency
842 system.cpu0.l1c.overall_avg_miss_latency::cpu0 71764.916026 # average overall miss latency
843 system.cpu0.l1c.overall_avg_miss_latency::total 71764.916026 # average overall miss latency
844 system.cpu0.l1c.blocked_cycles::no_mshrs 2152877 # number of cycles access was blocked
845 system.cpu0.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
846 system.cpu0.l1c.blocked::no_mshrs 58943 # number of cycles access was blocked
847 system.cpu0.l1c.blocked::no_targets 0 # number of cycles access was blocked
848 system.cpu0.l1c.avg_blocked_cycles::no_mshrs 36.524727 # average number of cycles each access was blocked
849 system.cpu0.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
850 system.cpu0.l1c.fast_writes 0 # number of fast writes performed
851 system.cpu0.l1c.cache_copies 0 # number of cache copies performed
852 system.cpu0.l1c.writebacks::writebacks 9551 # number of writebacks
853 system.cpu0.l1c.writebacks::total 9551 # number of writebacks
854 system.cpu0.l1c.ReadReq_mshr_misses::cpu0 35979 # number of ReadReq MSHR misses
855 system.cpu0.l1c.ReadReq_mshr_misses::total 35979 # number of ReadReq MSHR misses
856 system.cpu0.l1c.WriteReq_mshr_misses::cpu0 22956 # number of WriteReq MSHR misses
857 system.cpu0.l1c.WriteReq_mshr_misses::total 22956 # number of WriteReq MSHR misses
858 system.cpu0.l1c.demand_mshr_misses::cpu0 58935 # number of demand (read+write) MSHR misses
859 system.cpu0.l1c.demand_mshr_misses::total 58935 # number of demand (read+write) MSHR misses
860 system.cpu0.l1c.overall_mshr_misses::cpu0 58935 # number of overall MSHR misses
861 system.cpu0.l1c.overall_mshr_misses::total 58935 # number of overall MSHR misses
862 system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 2355407447 # number of ReadReq MSHR miss cycles
863 system.cpu0.l1c.ReadReq_mshr_miss_latency::total 2355407447 # number of ReadReq MSHR miss cycles
864 system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 1750135961 # number of WriteReq MSHR miss cycles
865 system.cpu0.l1c.WriteReq_mshr_miss_latency::total 1750135961 # number of WriteReq MSHR miss cycles
866 system.cpu0.l1c.demand_mshr_miss_latency::cpu0 4105543408 # number of demand (read+write) MSHR miss cycles
867 system.cpu0.l1c.demand_mshr_miss_latency::total 4105543408 # number of demand (read+write) MSHR miss cycles
868 system.cpu0.l1c.overall_mshr_miss_latency::cpu0 4105543408 # number of overall MSHR miss cycles
869 system.cpu0.l1c.overall_mshr_miss_latency::total 4105543408 # number of overall MSHR miss cycles
870 system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 1091154570 # number of ReadReq MSHR uncacheable cycles
871 system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 1091154570 # number of ReadReq MSHR uncacheable cycles
872 system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 4041529643 # number of WriteReq MSHR uncacheable cycles
873 system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 4041529643 # number of WriteReq MSHR uncacheable cycles
874 system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 5132684213 # number of overall MSHR uncacheable cycles
875 system.cpu0.l1c.overall_mshr_uncacheable_latency::total 5132684213 # number of overall MSHR uncacheable cycles
876 system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.805278 # mshr miss rate for ReadReq accesses
877 system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.805278 # mshr miss rate for ReadReq accesses
878 system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.956580 # mshr miss rate for WriteReq accesses
879 system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.956580 # mshr miss rate for WriteReq accesses
880 system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.858148 # mshr miss rate for demand accesses
881 system.cpu0.l1c.demand_mshr_miss_rate::total 0.858148 # mshr miss rate for demand accesses
882 system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.858148 # mshr miss rate for overall accesses
883 system.cpu0.l1c.overall_mshr_miss_rate::total 0.858148 # mshr miss rate for overall accesses
884 system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 65466.173240 # average ReadReq mshr miss latency
885 system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 65466.173240 # average ReadReq mshr miss latency
886 system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 76238.715848 # average WriteReq mshr miss latency
887 system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 76238.715848 # average WriteReq mshr miss latency
888 system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 69662.228014 # average overall mshr miss latency
889 system.cpu0.l1c.demand_avg_mshr_miss_latency::total 69662.228014 # average overall mshr miss latency
890 system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 69662.228014 # average overall mshr miss latency
891 system.cpu0.l1c.overall_avg_mshr_miss_latency::total 69662.228014 # average overall mshr miss latency
892 system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency
893 system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
894 system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 inf # average WriteReq mshr uncacheable latency
895 system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
896 system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 inf # average overall mshr uncacheable latency
897 system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
898 system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
899 system.cpu1.num_reads 99768 # number of read accesses completed
900 system.cpu1.num_writes 53422 # number of write accesses completed
901 system.cpu1.num_copies 0 # number of copy accesses completed
902 system.cpu1.l1c.tags.replacements 22481 # number of replacements
903 system.cpu1.l1c.tags.tagsinuse 398.933743 # Cycle average of tags in use
904 system.cpu1.l1c.tags.total_refs 13300 # Total number of references to valid blocks.
905 system.cpu1.l1c.tags.sampled_refs 22873 # Sample count of references to valid blocks.
906 system.cpu1.l1c.tags.avg_refs 0.581472 # Average number of references to valid blocks.
907 system.cpu1.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
908 system.cpu1.l1c.tags.occ_blocks::cpu1 398.933743 # Average occupied blocks per requestor
909 system.cpu1.l1c.tags.occ_percent::cpu1 0.779167 # Average percentage of cache occupancy
910 system.cpu1.l1c.tags.occ_percent::total 0.779167 # Average percentage of cache occupancy
911 system.cpu1.l1c.tags.occ_task_id_blocks::1024 392 # Occupied blocks per task id
912 system.cpu1.l1c.tags.age_task_id_blocks_1024::0 265 # Occupied blocks per task id
913 system.cpu1.l1c.tags.age_task_id_blocks_1024::1 127 # Occupied blocks per task id
914 system.cpu1.l1c.tags.occ_task_id_percent::1024 0.765625 # Percentage of cache occupancy per task id
915 system.cpu1.l1c.tags.tag_accesses 331866 # Number of tag accesses
916 system.cpu1.l1c.tags.data_accesses 331866 # Number of data accesses
917 system.cpu1.l1c.ReadReq_hits::cpu1 8705 # number of ReadReq hits
918 system.cpu1.l1c.ReadReq_hits::total 8705 # number of ReadReq hits
919 system.cpu1.l1c.WriteReq_hits::cpu1 1116 # number of WriteReq hits
920 system.cpu1.l1c.WriteReq_hits::total 1116 # number of WriteReq hits
921 system.cpu1.l1c.demand_hits::cpu1 9821 # number of demand (read+write) hits
922 system.cpu1.l1c.demand_hits::total 9821 # number of demand (read+write) hits
923 system.cpu1.l1c.overall_hits::cpu1 9821 # number of overall hits
924 system.cpu1.l1c.overall_hits::total 9821 # number of overall hits
925 system.cpu1.l1c.ReadReq_misses::cpu1 36262 # number of ReadReq misses
926 system.cpu1.l1c.ReadReq_misses::total 36262 # number of ReadReq misses
927 system.cpu1.l1c.WriteReq_misses::cpu1 22965 # number of WriteReq misses
928 system.cpu1.l1c.WriteReq_misses::total 22965 # number of WriteReq misses
929 system.cpu1.l1c.demand_misses::cpu1 59227 # number of demand (read+write) misses
930 system.cpu1.l1c.demand_misses::total 59227 # number of demand (read+write) misses
931 system.cpu1.l1c.overall_misses::cpu1 59227 # number of overall misses
932 system.cpu1.l1c.overall_misses::total 59227 # number of overall misses
933 system.cpu1.l1c.ReadReq_miss_latency::cpu1 2445520804 # number of ReadReq miss cycles
934 system.cpu1.l1c.ReadReq_miss_latency::total 2445520804 # number of ReadReq miss cycles
935 system.cpu1.l1c.WriteReq_miss_latency::cpu1 1800113040 # number of WriteReq miss cycles
936 system.cpu1.l1c.WriteReq_miss_latency::total 1800113040 # number of WriteReq miss cycles
937 system.cpu1.l1c.demand_miss_latency::cpu1 4245633844 # number of demand (read+write) miss cycles
938 system.cpu1.l1c.demand_miss_latency::total 4245633844 # number of demand (read+write) miss cycles
939 system.cpu1.l1c.overall_miss_latency::cpu1 4245633844 # number of overall miss cycles
940 system.cpu1.l1c.overall_miss_latency::total 4245633844 # number of overall miss cycles
941 system.cpu1.l1c.ReadReq_accesses::cpu1 44967 # number of ReadReq accesses(hits+misses)
942 system.cpu1.l1c.ReadReq_accesses::total 44967 # number of ReadReq accesses(hits+misses)
943 system.cpu1.l1c.WriteReq_accesses::cpu1 24081 # number of WriteReq accesses(hits+misses)
944 system.cpu1.l1c.WriteReq_accesses::total 24081 # number of WriteReq accesses(hits+misses)
945 system.cpu1.l1c.demand_accesses::cpu1 69048 # number of demand (read+write) accesses
946 system.cpu1.l1c.demand_accesses::total 69048 # number of demand (read+write) accesses
947 system.cpu1.l1c.overall_accesses::cpu1 69048 # number of overall (read+write) accesses
948 system.cpu1.l1c.overall_accesses::total 69048 # number of overall (read+write) accesses
949 system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.806414 # miss rate for ReadReq accesses
950 system.cpu1.l1c.ReadReq_miss_rate::total 0.806414 # miss rate for ReadReq accesses
951 system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.953656 # miss rate for WriteReq accesses
952 system.cpu1.l1c.WriteReq_miss_rate::total 0.953656 # miss rate for WriteReq accesses
953 system.cpu1.l1c.demand_miss_rate::cpu1 0.857766 # miss rate for demand accesses
954 system.cpu1.l1c.demand_miss_rate::total 0.857766 # miss rate for demand accesses
955 system.cpu1.l1c.overall_miss_rate::cpu1 0.857766 # miss rate for overall accesses
956 system.cpu1.l1c.overall_miss_rate::total 0.857766 # miss rate for overall accesses
957 system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 67440.317798 # average ReadReq miss latency
958 system.cpu1.l1c.ReadReq_avg_miss_latency::total 67440.317798 # average ReadReq miss latency
959 system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 78385.065970 # average WriteReq miss latency
960 system.cpu1.l1c.WriteReq_avg_miss_latency::total 78385.065970 # average WriteReq miss latency
961 system.cpu1.l1c.demand_avg_miss_latency::cpu1 71684.094146 # average overall miss latency
962 system.cpu1.l1c.demand_avg_miss_latency::total 71684.094146 # average overall miss latency
963 system.cpu1.l1c.overall_avg_miss_latency::cpu1 71684.094146 # average overall miss latency
964 system.cpu1.l1c.overall_avg_miss_latency::total 71684.094146 # average overall miss latency
965 system.cpu1.l1c.blocked_cycles::no_mshrs 2169051 # number of cycles access was blocked
966 system.cpu1.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
967 system.cpu1.l1c.blocked::no_mshrs 59314 # number of cycles access was blocked
968 system.cpu1.l1c.blocked::no_targets 0 # number of cycles access was blocked
969 system.cpu1.l1c.avg_blocked_cycles::no_mshrs 36.568955 # average number of cycles each access was blocked
970 system.cpu1.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
971 system.cpu1.l1c.fast_writes 0 # number of fast writes performed
972 system.cpu1.l1c.cache_copies 0 # number of cache copies performed
973 system.cpu1.l1c.writebacks::writebacks 9774 # number of writebacks
974 system.cpu1.l1c.writebacks::total 9774 # number of writebacks
975 system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36262 # number of ReadReq MSHR misses
976 system.cpu1.l1c.ReadReq_mshr_misses::total 36262 # number of ReadReq MSHR misses
977 system.cpu1.l1c.WriteReq_mshr_misses::cpu1 22965 # number of WriteReq MSHR misses
978 system.cpu1.l1c.WriteReq_mshr_misses::total 22965 # number of WriteReq MSHR misses
979 system.cpu1.l1c.demand_mshr_misses::cpu1 59227 # number of demand (read+write) MSHR misses
980 system.cpu1.l1c.demand_mshr_misses::total 59227 # number of demand (read+write) MSHR misses
981 system.cpu1.l1c.overall_mshr_misses::cpu1 59227 # number of overall MSHR misses
982 system.cpu1.l1c.overall_mshr_misses::total 59227 # number of overall MSHR misses
983 system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 2368901584 # number of ReadReq MSHR miss cycles
984 system.cpu1.l1c.ReadReq_mshr_miss_latency::total 2368901584 # number of ReadReq MSHR miss cycles
985 system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 1752103572 # number of WriteReq MSHR miss cycles
986 system.cpu1.l1c.WriteReq_mshr_miss_latency::total 1752103572 # number of WriteReq MSHR miss cycles
987 system.cpu1.l1c.demand_mshr_miss_latency::cpu1 4121005156 # number of demand (read+write) MSHR miss cycles
988 system.cpu1.l1c.demand_mshr_miss_latency::total 4121005156 # number of demand (read+write) MSHR miss cycles
989 system.cpu1.l1c.overall_mshr_miss_latency::cpu1 4121005156 # number of overall MSHR miss cycles
990 system.cpu1.l1c.overall_mshr_miss_latency::total 4121005156 # number of overall MSHR miss cycles
991 system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 1095385986 # number of ReadReq MSHR uncacheable cycles
992 system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 1095385986 # number of ReadReq MSHR uncacheable cycles
993 system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 3917382799 # number of WriteReq MSHR uncacheable cycles
994 system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 3917382799 # number of WriteReq MSHR uncacheable cycles
995 system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 5012768785 # number of overall MSHR uncacheable cycles
996 system.cpu1.l1c.overall_mshr_uncacheable_latency::total 5012768785 # number of overall MSHR uncacheable cycles
997 system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.806414 # mshr miss rate for ReadReq accesses
998 system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.806414 # mshr miss rate for ReadReq accesses
999 system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.953656 # mshr miss rate for WriteReq accesses
1000 system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.953656 # mshr miss rate for WriteReq accesses
1001 system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.857766 # mshr miss rate for demand accesses
1002 system.cpu1.l1c.demand_mshr_miss_rate::total 0.857766 # mshr miss rate for demand accesses
1003 system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.857766 # mshr miss rate for overall accesses
1004 system.cpu1.l1c.overall_mshr_miss_rate::total 0.857766 # mshr miss rate for overall accesses
1005 system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 65327.383597 # average ReadReq mshr miss latency
1006 system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 65327.383597 # average ReadReq mshr miss latency
1007 system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 76294.516525 # average WriteReq mshr miss latency
1008 system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 76294.516525 # average WriteReq mshr miss latency
1009 system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 69579.839533 # average overall mshr miss latency
1010 system.cpu1.l1c.demand_avg_mshr_miss_latency::total 69579.839533 # average overall mshr miss latency
1011 system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 69579.839533 # average overall mshr miss latency
1012 system.cpu1.l1c.overall_avg_mshr_miss_latency::total 69579.839533 # average overall mshr miss latency
1013 system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency
1014 system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1015 system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 inf # average WriteReq mshr uncacheable latency
1016 system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1017 system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 inf # average overall mshr uncacheable latency
1018 system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1019 system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
1020 system.cpu2.num_reads 100000 # number of read accesses completed
1021 system.cpu2.num_writes 53603 # number of write accesses completed
1022 system.cpu2.num_copies 0 # number of copy accesses completed
1023 system.cpu2.l1c.tags.replacements 22539 # number of replacements
1024 system.cpu2.l1c.tags.tagsinuse 397.267456 # Cycle average of tags in use
1025 system.cpu2.l1c.tags.total_refs 13362 # Total number of references to valid blocks.
1026 system.cpu2.l1c.tags.sampled_refs 22949 # Sample count of references to valid blocks.
1027 system.cpu2.l1c.tags.avg_refs 0.582248 # Average number of references to valid blocks.
1028 system.cpu2.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1029 system.cpu2.l1c.tags.occ_blocks::cpu2 397.267456 # Average occupied blocks per requestor
1030 system.cpu2.l1c.tags.occ_percent::cpu2 0.775913 # Average percentage of cache occupancy
1031 system.cpu2.l1c.tags.occ_percent::total 0.775913 # Average percentage of cache occupancy
1032 system.cpu2.l1c.tags.occ_task_id_blocks::1024 410 # Occupied blocks per task id
1033 system.cpu2.l1c.tags.age_task_id_blocks_1024::0 285 # Occupied blocks per task id
1034 system.cpu2.l1c.tags.age_task_id_blocks_1024::1 125 # Occupied blocks per task id
1035 system.cpu2.l1c.tags.occ_task_id_percent::1024 0.800781 # Percentage of cache occupancy per task id
1036 system.cpu2.l1c.tags.tag_accesses 332293 # Number of tag accesses
1037 system.cpu2.l1c.tags.data_accesses 332293 # Number of data accesses
1038 system.cpu2.l1c.ReadReq_hits::cpu2 8761 # number of ReadReq hits
1039 system.cpu2.l1c.ReadReq_hits::total 8761 # number of ReadReq hits
1040 system.cpu2.l1c.WriteReq_hits::cpu2 1062 # number of WriteReq hits
1041 system.cpu2.l1c.WriteReq_hits::total 1062 # number of WriteReq hits
1042 system.cpu2.l1c.demand_hits::cpu2 9823 # number of demand (read+write) hits
1043 system.cpu2.l1c.demand_hits::total 9823 # number of demand (read+write) hits
1044 system.cpu2.l1c.overall_hits::cpu2 9823 # number of overall hits
1045 system.cpu2.l1c.overall_hits::total 9823 # number of overall hits
1046 system.cpu2.l1c.ReadReq_misses::cpu2 36321 # number of ReadReq misses
1047 system.cpu2.l1c.ReadReq_misses::total 36321 # number of ReadReq misses
1048 system.cpu2.l1c.WriteReq_misses::cpu2 22996 # number of WriteReq misses
1049 system.cpu2.l1c.WriteReq_misses::total 22996 # number of WriteReq misses
1050 system.cpu2.l1c.demand_misses::cpu2 59317 # number of demand (read+write) misses
1051 system.cpu2.l1c.demand_misses::total 59317 # number of demand (read+write) misses
1052 system.cpu2.l1c.overall_misses::cpu2 59317 # number of overall misses
1053 system.cpu2.l1c.overall_misses::total 59317 # number of overall misses
1054 system.cpu2.l1c.ReadReq_miss_latency::cpu2 2442264018 # number of ReadReq miss cycles
1055 system.cpu2.l1c.ReadReq_miss_latency::total 2442264018 # number of ReadReq miss cycles
1056 system.cpu2.l1c.WriteReq_miss_latency::cpu2 1799405026 # number of WriteReq miss cycles
1057 system.cpu2.l1c.WriteReq_miss_latency::total 1799405026 # number of WriteReq miss cycles
1058 system.cpu2.l1c.demand_miss_latency::cpu2 4241669044 # number of demand (read+write) miss cycles
1059 system.cpu2.l1c.demand_miss_latency::total 4241669044 # number of demand (read+write) miss cycles
1060 system.cpu2.l1c.overall_miss_latency::cpu2 4241669044 # number of overall miss cycles
1061 system.cpu2.l1c.overall_miss_latency::total 4241669044 # number of overall miss cycles
1062 system.cpu2.l1c.ReadReq_accesses::cpu2 45082 # number of ReadReq accesses(hits+misses)
1063 system.cpu2.l1c.ReadReq_accesses::total 45082 # number of ReadReq accesses(hits+misses)
1064 system.cpu2.l1c.WriteReq_accesses::cpu2 24058 # number of WriteReq accesses(hits+misses)
1065 system.cpu2.l1c.WriteReq_accesses::total 24058 # number of WriteReq accesses(hits+misses)
1066 system.cpu2.l1c.demand_accesses::cpu2 69140 # number of demand (read+write) accesses
1067 system.cpu2.l1c.demand_accesses::total 69140 # number of demand (read+write) accesses
1068 system.cpu2.l1c.overall_accesses::cpu2 69140 # number of overall (read+write) accesses
1069 system.cpu2.l1c.overall_accesses::total 69140 # number of overall (read+write) accesses
1070 system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.805665 # miss rate for ReadReq accesses
1071 system.cpu2.l1c.ReadReq_miss_rate::total 0.805665 # miss rate for ReadReq accesses
1072 system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.955857 # miss rate for WriteReq accesses
1073 system.cpu2.l1c.WriteReq_miss_rate::total 0.955857 # miss rate for WriteReq accesses
1074 system.cpu2.l1c.demand_miss_rate::cpu2 0.857926 # miss rate for demand accesses
1075 system.cpu2.l1c.demand_miss_rate::total 0.857926 # miss rate for demand accesses
1076 system.cpu2.l1c.overall_miss_rate::cpu2 0.857926 # miss rate for overall accesses
1077 system.cpu2.l1c.overall_miss_rate::total 0.857926 # miss rate for overall accesses
1078 system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 67241.100686 # average ReadReq miss latency
1079 system.cpu2.l1c.ReadReq_avg_miss_latency::total 67241.100686 # average ReadReq miss latency
1080 system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 78248.609584 # average WriteReq miss latency
1081 system.cpu2.l1c.WriteReq_avg_miss_latency::total 78248.609584 # average WriteReq miss latency
1082 system.cpu2.l1c.demand_avg_miss_latency::cpu2 71508.489033 # average overall miss latency
1083 system.cpu2.l1c.demand_avg_miss_latency::total 71508.489033 # average overall miss latency
1084 system.cpu2.l1c.overall_avg_miss_latency::cpu2 71508.489033 # average overall miss latency
1085 system.cpu2.l1c.overall_avg_miss_latency::total 71508.489033 # average overall miss latency
1086 system.cpu2.l1c.blocked_cycles::no_mshrs 2171204 # number of cycles access was blocked
1087 system.cpu2.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
1088 system.cpu2.l1c.blocked::no_mshrs 59435 # number of cycles access was blocked
1089 system.cpu2.l1c.blocked::no_targets 0 # number of cycles access was blocked
1090 system.cpu2.l1c.avg_blocked_cycles::no_mshrs 36.530731 # average number of cycles each access was blocked
1091 system.cpu2.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1092 system.cpu2.l1c.fast_writes 0 # number of fast writes performed
1093 system.cpu2.l1c.cache_copies 0 # number of cache copies performed
1094 system.cpu2.l1c.writebacks::writebacks 9704 # number of writebacks
1095 system.cpu2.l1c.writebacks::total 9704 # number of writebacks
1096 system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36321 # number of ReadReq MSHR misses
1097 system.cpu2.l1c.ReadReq_mshr_misses::total 36321 # number of ReadReq MSHR misses
1098 system.cpu2.l1c.WriteReq_mshr_misses::cpu2 22996 # number of WriteReq MSHR misses
1099 system.cpu2.l1c.WriteReq_mshr_misses::total 22996 # number of WriteReq MSHR misses
1100 system.cpu2.l1c.demand_mshr_misses::cpu2 59317 # number of demand (read+write) MSHR misses
1101 system.cpu2.l1c.demand_mshr_misses::total 59317 # number of demand (read+write) MSHR misses
1102 system.cpu2.l1c.overall_mshr_misses::cpu2 59317 # number of overall MSHR misses
1103 system.cpu2.l1c.overall_mshr_misses::total 59317 # number of overall MSHR misses
1104 system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 2365672458 # number of ReadReq MSHR miss cycles
1105 system.cpu2.l1c.ReadReq_mshr_miss_latency::total 2365672458 # number of ReadReq MSHR miss cycles
1106 system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 1751310602 # number of WriteReq MSHR miss cycles
1107 system.cpu2.l1c.WriteReq_mshr_miss_latency::total 1751310602 # number of WriteReq MSHR miss cycles
1108 system.cpu2.l1c.demand_mshr_miss_latency::cpu2 4116983060 # number of demand (read+write) MSHR miss cycles
1109 system.cpu2.l1c.demand_mshr_miss_latency::total 4116983060 # number of demand (read+write) MSHR miss cycles
1110 system.cpu2.l1c.overall_mshr_miss_latency::cpu2 4116983060 # number of overall MSHR miss cycles
1111 system.cpu2.l1c.overall_mshr_miss_latency::total 4116983060 # number of overall MSHR miss cycles
1112 system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 1097675449 # number of ReadReq MSHR uncacheable cycles
1113 system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 1097675449 # number of ReadReq MSHR uncacheable cycles
1114 system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 3894001300 # number of WriteReq MSHR uncacheable cycles
1115 system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 3894001300 # number of WriteReq MSHR uncacheable cycles
1116 system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 4991676749 # number of overall MSHR uncacheable cycles
1117 system.cpu2.l1c.overall_mshr_uncacheable_latency::total 4991676749 # number of overall MSHR uncacheable cycles
1118 system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.805665 # mshr miss rate for ReadReq accesses
1119 system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.805665 # mshr miss rate for ReadReq accesses
1120 system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.955857 # mshr miss rate for WriteReq accesses
1121 system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.955857 # mshr miss rate for WriteReq accesses
1122 system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.857926 # mshr miss rate for demand accesses
1123 system.cpu2.l1c.demand_mshr_miss_rate::total 0.857926 # mshr miss rate for demand accesses
1124 system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.857926 # mshr miss rate for overall accesses
1125 system.cpu2.l1c.overall_mshr_miss_rate::total 0.857926 # mshr miss rate for overall accesses
1126 system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 65132.360287 # average ReadReq mshr miss latency
1127 system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 65132.360287 # average ReadReq mshr miss latency
1128 system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 76157.183945 # average WriteReq mshr miss latency
1129 system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 76157.183945 # average WriteReq mshr miss latency
1130 system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 69406.461217 # average overall mshr miss latency
1131 system.cpu2.l1c.demand_avg_mshr_miss_latency::total 69406.461217 # average overall mshr miss latency
1132 system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 69406.461217 # average overall mshr miss latency
1133 system.cpu2.l1c.overall_avg_mshr_miss_latency::total 69406.461217 # average overall mshr miss latency
1134 system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency
1135 system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1136 system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 inf # average WriteReq mshr uncacheable latency
1137 system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1138 system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 inf # average overall mshr uncacheable latency
1139 system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1140 system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
1141 system.cpu3.num_reads 99664 # number of read accesses completed
1142 system.cpu3.num_writes 53618 # number of write accesses completed
1143 system.cpu3.num_copies 0 # number of copy accesses completed
1144 system.cpu3.l1c.tags.replacements 22539 # number of replacements
1145 system.cpu3.l1c.tags.tagsinuse 397.521626 # Cycle average of tags in use
1146 system.cpu3.l1c.tags.total_refs 13272 # Total number of references to valid blocks.
1147 system.cpu3.l1c.tags.sampled_refs 22952 # Sample count of references to valid blocks.
1148 system.cpu3.l1c.tags.avg_refs 0.578250 # Average number of references to valid blocks.
1149 system.cpu3.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1150 system.cpu3.l1c.tags.occ_blocks::cpu3 397.521626 # Average occupied blocks per requestor
1151 system.cpu3.l1c.tags.occ_percent::cpu3 0.776409 # Average percentage of cache occupancy
1152 system.cpu3.l1c.tags.occ_percent::total 0.776409 # Average percentage of cache occupancy
1153 system.cpu3.l1c.tags.occ_task_id_blocks::1024 413 # Occupied blocks per task id
1154 system.cpu3.l1c.tags.age_task_id_blocks_1024::0 263 # Occupied blocks per task id
1155 system.cpu3.l1c.tags.age_task_id_blocks_1024::1 150 # Occupied blocks per task id
1156 system.cpu3.l1c.tags.occ_task_id_percent::1024 0.806641 # Percentage of cache occupancy per task id
1157 system.cpu3.l1c.tags.tag_accesses 332331 # Number of tag accesses
1158 system.cpu3.l1c.tags.data_accesses 332331 # Number of data accesses
1159 system.cpu3.l1c.ReadReq_hits::cpu3 8701 # number of ReadReq hits
1160 system.cpu3.l1c.ReadReq_hits::total 8701 # number of ReadReq hits
1161 system.cpu3.l1c.WriteReq_hits::cpu3 1040 # number of WriteReq hits
1162 system.cpu3.l1c.WriteReq_hits::total 1040 # number of WriteReq hits
1163 system.cpu3.l1c.demand_hits::cpu3 9741 # number of demand (read+write) hits
1164 system.cpu3.l1c.demand_hits::total 9741 # number of demand (read+write) hits
1165 system.cpu3.l1c.overall_hits::cpu3 9741 # number of overall hits
1166 system.cpu3.l1c.overall_hits::total 9741 # number of overall hits
1167 system.cpu3.l1c.ReadReq_misses::cpu3 36310 # number of ReadReq misses
1168 system.cpu3.l1c.ReadReq_misses::total 36310 # number of ReadReq misses
1169 system.cpu3.l1c.WriteReq_misses::cpu3 23079 # number of WriteReq misses
1170 system.cpu3.l1c.WriteReq_misses::total 23079 # number of WriteReq misses
1171 system.cpu3.l1c.demand_misses::cpu3 59389 # number of demand (read+write) misses
1172 system.cpu3.l1c.demand_misses::total 59389 # number of demand (read+write) misses
1173 system.cpu3.l1c.overall_misses::cpu3 59389 # number of overall misses
1174 system.cpu3.l1c.overall_misses::total 59389 # number of overall misses
1175 system.cpu3.l1c.ReadReq_miss_latency::cpu3 2444229866 # number of ReadReq miss cycles
1176 system.cpu3.l1c.ReadReq_miss_latency::total 2444229866 # number of ReadReq miss cycles
1177 system.cpu3.l1c.WriteReq_miss_latency::cpu3 1811981579 # number of WriteReq miss cycles
1178 system.cpu3.l1c.WriteReq_miss_latency::total 1811981579 # number of WriteReq miss cycles
1179 system.cpu3.l1c.demand_miss_latency::cpu3 4256211445 # number of demand (read+write) miss cycles
1180 system.cpu3.l1c.demand_miss_latency::total 4256211445 # number of demand (read+write) miss cycles
1181 system.cpu3.l1c.overall_miss_latency::cpu3 4256211445 # number of overall miss cycles
1182 system.cpu3.l1c.overall_miss_latency::total 4256211445 # number of overall miss cycles
1183 system.cpu3.l1c.ReadReq_accesses::cpu3 45011 # number of ReadReq accesses(hits+misses)
1184 system.cpu3.l1c.ReadReq_accesses::total 45011 # number of ReadReq accesses(hits+misses)
1185 system.cpu3.l1c.WriteReq_accesses::cpu3 24119 # number of WriteReq accesses(hits+misses)
1186 system.cpu3.l1c.WriteReq_accesses::total 24119 # number of WriteReq accesses(hits+misses)
1187 system.cpu3.l1c.demand_accesses::cpu3 69130 # number of demand (read+write) accesses
1188 system.cpu3.l1c.demand_accesses::total 69130 # number of demand (read+write) accesses
1189 system.cpu3.l1c.overall_accesses::cpu3 69130 # number of overall (read+write) accesses
1190 system.cpu3.l1c.overall_accesses::total 69130 # number of overall (read+write) accesses
1191 system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.806692 # miss rate for ReadReq accesses
1192 system.cpu3.l1c.ReadReq_miss_rate::total 0.806692 # miss rate for ReadReq accesses
1193 system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.956880 # miss rate for WriteReq accesses
1194 system.cpu3.l1c.WriteReq_miss_rate::total 0.956880 # miss rate for WriteReq accesses
1195 system.cpu3.l1c.demand_miss_rate::cpu3 0.859092 # miss rate for demand accesses
1196 system.cpu3.l1c.demand_miss_rate::total 0.859092 # miss rate for demand accesses
1197 system.cpu3.l1c.overall_miss_rate::cpu3 0.859092 # miss rate for overall accesses
1198 system.cpu3.l1c.overall_miss_rate::total 0.859092 # miss rate for overall accesses
1199 system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 67315.611842 # average ReadReq miss latency
1200 system.cpu3.l1c.ReadReq_avg_miss_latency::total 67315.611842 # average ReadReq miss latency
1201 system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 78512.135664 # average WriteReq miss latency
1202 system.cpu3.l1c.WriteReq_avg_miss_latency::total 78512.135664 # average WriteReq miss latency
1203 system.cpu3.l1c.demand_avg_miss_latency::cpu3 71666.662934 # average overall miss latency
1204 system.cpu3.l1c.demand_avg_miss_latency::total 71666.662934 # average overall miss latency
1205 system.cpu3.l1c.overall_avg_miss_latency::cpu3 71666.662934 # average overall miss latency
1206 system.cpu3.l1c.overall_avg_miss_latency::total 71666.662934 # average overall miss latency
1207 system.cpu3.l1c.blocked_cycles::no_mshrs 2167444 # number of cycles access was blocked
1208 system.cpu3.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
1209 system.cpu3.l1c.blocked::no_mshrs 59346 # number of cycles access was blocked
1210 system.cpu3.l1c.blocked::no_targets 0 # number of cycles access was blocked
1211 system.cpu3.l1c.avg_blocked_cycles::no_mshrs 36.522158 # average number of cycles each access was blocked
1212 system.cpu3.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1213 system.cpu3.l1c.fast_writes 0 # number of fast writes performed
1214 system.cpu3.l1c.cache_copies 0 # number of cache copies performed
1215 system.cpu3.l1c.writebacks::writebacks 9755 # number of writebacks
1216 system.cpu3.l1c.writebacks::total 9755 # number of writebacks
1217 system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36310 # number of ReadReq MSHR misses
1218 system.cpu3.l1c.ReadReq_mshr_misses::total 36310 # number of ReadReq MSHR misses
1219 system.cpu3.l1c.WriteReq_mshr_misses::cpu3 23079 # number of WriteReq MSHR misses
1220 system.cpu3.l1c.WriteReq_mshr_misses::total 23079 # number of WriteReq MSHR misses
1221 system.cpu3.l1c.demand_mshr_misses::cpu3 59389 # number of demand (read+write) MSHR misses
1222 system.cpu3.l1c.demand_mshr_misses::total 59389 # number of demand (read+write) MSHR misses
1223 system.cpu3.l1c.overall_mshr_misses::cpu3 59389 # number of overall MSHR misses
1224 system.cpu3.l1c.overall_mshr_misses::total 59389 # number of overall MSHR misses
1225 system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 2367603538 # number of ReadReq MSHR miss cycles
1226 system.cpu3.l1c.ReadReq_mshr_miss_latency::total 2367603538 # number of ReadReq MSHR miss cycles
1227 system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 1763687167 # number of WriteReq MSHR miss cycles
1228 system.cpu3.l1c.WriteReq_mshr_miss_latency::total 1763687167 # number of WriteReq MSHR miss cycles
1229 system.cpu3.l1c.demand_mshr_miss_latency::cpu3 4131290705 # number of demand (read+write) MSHR miss cycles
1230 system.cpu3.l1c.demand_mshr_miss_latency::total 4131290705 # number of demand (read+write) MSHR miss cycles
1231 system.cpu3.l1c.overall_mshr_miss_latency::cpu3 4131290705 # number of overall MSHR miss cycles
1232 system.cpu3.l1c.overall_mshr_miss_latency::total 4131290705 # number of overall MSHR miss cycles
1233 system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 1080268673 # number of ReadReq MSHR uncacheable cycles
1234 system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 1080268673 # number of ReadReq MSHR uncacheable cycles
1235 system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 3893349735 # number of WriteReq MSHR uncacheable cycles
1236 system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 3893349735 # number of WriteReq MSHR uncacheable cycles
1237 system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 4973618408 # number of overall MSHR uncacheable cycles
1238 system.cpu3.l1c.overall_mshr_uncacheable_latency::total 4973618408 # number of overall MSHR uncacheable cycles
1239 system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.806692 # mshr miss rate for ReadReq accesses
1240 system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.806692 # mshr miss rate for ReadReq accesses
1241 system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.956880 # mshr miss rate for WriteReq accesses
1242 system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.956880 # mshr miss rate for WriteReq accesses
1243 system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.859092 # mshr miss rate for demand accesses
1244 system.cpu3.l1c.demand_mshr_miss_rate::total 0.859092 # mshr miss rate for demand accesses
1245 system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.859092 # mshr miss rate for overall accesses
1246 system.cpu3.l1c.overall_mshr_miss_rate::total 0.859092 # mshr miss rate for overall accesses
1247 system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 65205.275076 # average ReadReq mshr miss latency
1248 system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 65205.275076 # average ReadReq mshr miss latency
1249 system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 76419.566142 # average WriteReq mshr miss latency
1250 system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 76419.566142 # average WriteReq mshr miss latency
1251 system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 69563.230649 # average overall mshr miss latency
1252 system.cpu3.l1c.demand_avg_mshr_miss_latency::total 69563.230649 # average overall mshr miss latency
1253 system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 69563.230649 # average overall mshr miss latency
1254 system.cpu3.l1c.overall_avg_mshr_miss_latency::total 69563.230649 # average overall mshr miss latency
1255 system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 inf # average ReadReq mshr uncacheable latency
1256 system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1257 system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 inf # average WriteReq mshr uncacheable latency
1258 system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1259 system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 inf # average overall mshr uncacheable latency
1260 system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1261 system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
1262 system.cpu4.num_reads 99015 # number of read accesses completed
1263 system.cpu4.num_writes 53820 # number of write accesses completed
1264 system.cpu4.num_copies 0 # number of copy accesses completed
1265 system.cpu4.l1c.tags.replacements 22084 # number of replacements
1266 system.cpu4.l1c.tags.tagsinuse 396.195798 # Cycle average of tags in use
1267 system.cpu4.l1c.tags.total_refs 13300 # Total number of references to valid blocks.
1268 system.cpu4.l1c.tags.sampled_refs 22488 # Sample count of references to valid blocks.
1269 system.cpu4.l1c.tags.avg_refs 0.591427 # Average number of references to valid blocks.
1270 system.cpu4.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1271 system.cpu4.l1c.tags.occ_blocks::cpu4 396.195798 # Average occupied blocks per requestor
1272 system.cpu4.l1c.tags.occ_percent::cpu4 0.773820 # Average percentage of cache occupancy
1273 system.cpu4.l1c.tags.occ_percent::total 0.773820 # Average percentage of cache occupancy
1274 system.cpu4.l1c.tags.occ_task_id_blocks::1024 404 # Occupied blocks per task id
1275 system.cpu4.l1c.tags.age_task_id_blocks_1024::0 265 # Occupied blocks per task id
1276 system.cpu4.l1c.tags.age_task_id_blocks_1024::1 139 # Occupied blocks per task id
1277 system.cpu4.l1c.tags.occ_task_id_percent::1024 0.789062 # Percentage of cache occupancy per task id
1278 system.cpu4.l1c.tags.tag_accesses 330427 # Number of tag accesses
1279 system.cpu4.l1c.tags.data_accesses 330427 # Number of data accesses
1280 system.cpu4.l1c.ReadReq_hits::cpu4 8669 # number of ReadReq hits
1281 system.cpu4.l1c.ReadReq_hits::total 8669 # number of ReadReq hits
1282 system.cpu4.l1c.WriteReq_hits::cpu4 1045 # number of WriteReq hits
1283 system.cpu4.l1c.WriteReq_hits::total 1045 # number of WriteReq hits
1284 system.cpu4.l1c.demand_hits::cpu4 9714 # number of demand (read+write) hits
1285 system.cpu4.l1c.demand_hits::total 9714 # number of demand (read+write) hits
1286 system.cpu4.l1c.overall_hits::cpu4 9714 # number of overall hits
1287 system.cpu4.l1c.overall_hits::total 9714 # number of overall hits
1288 system.cpu4.l1c.ReadReq_misses::cpu4 35948 # number of ReadReq misses
1289 system.cpu4.l1c.ReadReq_misses::total 35948 # number of ReadReq misses
1290 system.cpu4.l1c.WriteReq_misses::cpu4 23093 # number of WriteReq misses
1291 system.cpu4.l1c.WriteReq_misses::total 23093 # number of WriteReq misses
1292 system.cpu4.l1c.demand_misses::cpu4 59041 # number of demand (read+write) misses
1293 system.cpu4.l1c.demand_misses::total 59041 # number of demand (read+write) misses
1294 system.cpu4.l1c.overall_misses::cpu4 59041 # number of overall misses
1295 system.cpu4.l1c.overall_misses::total 59041 # number of overall misses
1296 system.cpu4.l1c.ReadReq_miss_latency::cpu4 2417278257 # number of ReadReq miss cycles
1297 system.cpu4.l1c.ReadReq_miss_latency::total 2417278257 # number of ReadReq miss cycles
1298 system.cpu4.l1c.WriteReq_miss_latency::cpu4 1822150466 # number of WriteReq miss cycles
1299 system.cpu4.l1c.WriteReq_miss_latency::total 1822150466 # number of WriteReq miss cycles
1300 system.cpu4.l1c.demand_miss_latency::cpu4 4239428723 # number of demand (read+write) miss cycles
1301 system.cpu4.l1c.demand_miss_latency::total 4239428723 # number of demand (read+write) miss cycles
1302 system.cpu4.l1c.overall_miss_latency::cpu4 4239428723 # number of overall miss cycles
1303 system.cpu4.l1c.overall_miss_latency::total 4239428723 # number of overall miss cycles
1304 system.cpu4.l1c.ReadReq_accesses::cpu4 44617 # number of ReadReq accesses(hits+misses)
1305 system.cpu4.l1c.ReadReq_accesses::total 44617 # number of ReadReq accesses(hits+misses)
1306 system.cpu4.l1c.WriteReq_accesses::cpu4 24138 # number of WriteReq accesses(hits+misses)
1307 system.cpu4.l1c.WriteReq_accesses::total 24138 # number of WriteReq accesses(hits+misses)
1308 system.cpu4.l1c.demand_accesses::cpu4 68755 # number of demand (read+write) accesses
1309 system.cpu4.l1c.demand_accesses::total 68755 # number of demand (read+write) accesses
1310 system.cpu4.l1c.overall_accesses::cpu4 68755 # number of overall (read+write) accesses
1311 system.cpu4.l1c.overall_accesses::total 68755 # number of overall (read+write) accesses
1312 system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.805702 # miss rate for ReadReq accesses
1313 system.cpu4.l1c.ReadReq_miss_rate::total 0.805702 # miss rate for ReadReq accesses
1314 system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.956707 # miss rate for WriteReq accesses
1315 system.cpu4.l1c.WriteReq_miss_rate::total 0.956707 # miss rate for WriteReq accesses
1316 system.cpu4.l1c.demand_miss_rate::cpu4 0.858716 # miss rate for demand accesses
1317 system.cpu4.l1c.demand_miss_rate::total 0.858716 # miss rate for demand accesses
1318 system.cpu4.l1c.overall_miss_rate::cpu4 0.858716 # miss rate for overall accesses
1319 system.cpu4.l1c.overall_miss_rate::total 0.858716 # miss rate for overall accesses
1320 system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 67243.748108 # average ReadReq miss latency
1321 system.cpu4.l1c.ReadReq_avg_miss_latency::total 67243.748108 # average ReadReq miss latency
1322 system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 78904.883125 # average WriteReq miss latency
1323 system.cpu4.l1c.WriteReq_avg_miss_latency::total 78904.883125 # average WriteReq miss latency
1324 system.cpu4.l1c.demand_avg_miss_latency::cpu4 71804.825850 # average overall miss latency
1325 system.cpu4.l1c.demand_avg_miss_latency::total 71804.825850 # average overall miss latency
1326 system.cpu4.l1c.overall_avg_miss_latency::cpu4 71804.825850 # average overall miss latency
1327 system.cpu4.l1c.overall_avg_miss_latency::total 71804.825850 # average overall miss latency
1328 system.cpu4.l1c.blocked_cycles::no_mshrs 2163506 # number of cycles access was blocked
1329 system.cpu4.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
1330 system.cpu4.l1c.blocked::no_mshrs 58921 # number of cycles access was blocked
1331 system.cpu4.l1c.blocked::no_targets 0 # number of cycles access was blocked
1332 system.cpu4.l1c.avg_blocked_cycles::no_mshrs 36.718759 # average number of cycles each access was blocked
1333 system.cpu4.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1334 system.cpu4.l1c.fast_writes 0 # number of fast writes performed
1335 system.cpu4.l1c.cache_copies 0 # number of cache copies performed
1336 system.cpu4.l1c.writebacks::writebacks 9586 # number of writebacks
1337 system.cpu4.l1c.writebacks::total 9586 # number of writebacks
1338 system.cpu4.l1c.ReadReq_mshr_misses::cpu4 35948 # number of ReadReq MSHR misses
1339 system.cpu4.l1c.ReadReq_mshr_misses::total 35948 # number of ReadReq MSHR misses
1340 system.cpu4.l1c.WriteReq_mshr_misses::cpu4 23093 # number of WriteReq MSHR misses
1341 system.cpu4.l1c.WriteReq_mshr_misses::total 23093 # number of WriteReq MSHR misses
1342 system.cpu4.l1c.demand_mshr_misses::cpu4 59041 # number of demand (read+write) MSHR misses
1343 system.cpu4.l1c.demand_mshr_misses::total 59041 # number of demand (read+write) MSHR misses
1344 system.cpu4.l1c.overall_mshr_misses::cpu4 59041 # number of overall MSHR misses
1345 system.cpu4.l1c.overall_mshr_misses::total 59041 # number of overall MSHR misses
1346 system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 2341432849 # number of ReadReq MSHR miss cycles
1347 system.cpu4.l1c.ReadReq_mshr_miss_latency::total 2341432849 # number of ReadReq MSHR miss cycles
1348 system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 1773798174 # number of WriteReq MSHR miss cycles
1349 system.cpu4.l1c.WriteReq_mshr_miss_latency::total 1773798174 # number of WriteReq MSHR miss cycles
1350 system.cpu4.l1c.demand_mshr_miss_latency::cpu4 4115231023 # number of demand (read+write) MSHR miss cycles
1351 system.cpu4.l1c.demand_mshr_miss_latency::total 4115231023 # number of demand (read+write) MSHR miss cycles
1352 system.cpu4.l1c.overall_mshr_miss_latency::cpu4 4115231023 # number of overall MSHR miss cycles
1353 system.cpu4.l1c.overall_mshr_miss_latency::total 4115231023 # number of overall MSHR miss cycles
1354 system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 1089200967 # number of ReadReq MSHR uncacheable cycles
1355 system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 1089200967 # number of ReadReq MSHR uncacheable cycles
1356 system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 3986639198 # number of WriteReq MSHR uncacheable cycles
1357 system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 3986639198 # number of WriteReq MSHR uncacheable cycles
1358 system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 5075840165 # number of overall MSHR uncacheable cycles
1359 system.cpu4.l1c.overall_mshr_uncacheable_latency::total 5075840165 # number of overall MSHR uncacheable cycles
1360 system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.805702 # mshr miss rate for ReadReq accesses
1361 system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.805702 # mshr miss rate for ReadReq accesses
1362 system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.956707 # mshr miss rate for WriteReq accesses
1363 system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.956707 # mshr miss rate for WriteReq accesses
1364 system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.858716 # mshr miss rate for demand accesses
1365 system.cpu4.l1c.demand_mshr_miss_rate::total 0.858716 # mshr miss rate for demand accesses
1366 system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.858716 # mshr miss rate for overall accesses
1367 system.cpu4.l1c.overall_mshr_miss_rate::total 0.858716 # mshr miss rate for overall accesses
1368 system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 65133.883637 # average ReadReq mshr miss latency
1369 system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 65133.883637 # average ReadReq mshr miss latency
1370 system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 76811.075824 # average WriteReq mshr miss latency
1371 system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 76811.075824 # average WriteReq mshr miss latency
1372 system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 69701.241900 # average overall mshr miss latency
1373 system.cpu4.l1c.demand_avg_mshr_miss_latency::total 69701.241900 # average overall mshr miss latency
1374 system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 69701.241900 # average overall mshr miss latency
1375 system.cpu4.l1c.overall_avg_mshr_miss_latency::total 69701.241900 # average overall mshr miss latency
1376 system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 inf # average ReadReq mshr uncacheable latency
1377 system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1378 system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 inf # average WriteReq mshr uncacheable latency
1379 system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1380 system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 inf # average overall mshr uncacheable latency
1381 system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1382 system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
1383 system.cpu5.num_reads 99463 # number of read accesses completed
1384 system.cpu5.num_writes 53761 # number of write accesses completed
1385 system.cpu5.num_copies 0 # number of copy accesses completed
1386 system.cpu5.l1c.tags.replacements 22236 # number of replacements
1387 system.cpu5.l1c.tags.tagsinuse 396.818591 # Cycle average of tags in use
1388 system.cpu5.l1c.tags.total_refs 13326 # Total number of references to valid blocks.
1389 system.cpu5.l1c.tags.sampled_refs 22643 # Sample count of references to valid blocks.
1390 system.cpu5.l1c.tags.avg_refs 0.588526 # Average number of references to valid blocks.
1391 system.cpu5.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1392 system.cpu5.l1c.tags.occ_blocks::cpu5 396.818591 # Average occupied blocks per requestor
1393 system.cpu5.l1c.tags.occ_percent::cpu5 0.775036 # Average percentage of cache occupancy
1394 system.cpu5.l1c.tags.occ_percent::total 0.775036 # Average percentage of cache occupancy
1395 system.cpu5.l1c.tags.occ_task_id_blocks::1024 407 # Occupied blocks per task id
1396 system.cpu5.l1c.tags.age_task_id_blocks_1024::0 275 # Occupied blocks per task id
1397 system.cpu5.l1c.tags.age_task_id_blocks_1024::1 132 # Occupied blocks per task id
1398 system.cpu5.l1c.tags.occ_task_id_percent::1024 0.794922 # Percentage of cache occupancy per task id
1399 system.cpu5.l1c.tags.tag_accesses 332464 # Number of tag accesses
1400 system.cpu5.l1c.tags.data_accesses 332464 # Number of data accesses
1401 system.cpu5.l1c.ReadReq_hits::cpu5 8698 # number of ReadReq hits
1402 system.cpu5.l1c.ReadReq_hits::total 8698 # number of ReadReq hits
1403 system.cpu5.l1c.WriteReq_hits::cpu5 1095 # number of WriteReq hits
1404 system.cpu5.l1c.WriteReq_hits::total 1095 # number of WriteReq hits
1405 system.cpu5.l1c.demand_hits::cpu5 9793 # number of demand (read+write) hits
1406 system.cpu5.l1c.demand_hits::total 9793 # number of demand (read+write) hits
1407 system.cpu5.l1c.overall_hits::cpu5 9793 # number of overall hits
1408 system.cpu5.l1c.overall_hits::total 9793 # number of overall hits
1409 system.cpu5.l1c.ReadReq_misses::cpu5 36190 # number of ReadReq misses
1410 system.cpu5.l1c.ReadReq_misses::total 36190 # number of ReadReq misses
1411 system.cpu5.l1c.WriteReq_misses::cpu5 23188 # number of WriteReq misses
1412 system.cpu5.l1c.WriteReq_misses::total 23188 # number of WriteReq misses
1413 system.cpu5.l1c.demand_misses::cpu5 59378 # number of demand (read+write) misses
1414 system.cpu5.l1c.demand_misses::total 59378 # number of demand (read+write) misses
1415 system.cpu5.l1c.overall_misses::cpu5 59378 # number of overall misses
1416 system.cpu5.l1c.overall_misses::total 59378 # number of overall misses
1417 system.cpu5.l1c.ReadReq_miss_latency::cpu5 2440787473 # number of ReadReq miss cycles
1418 system.cpu5.l1c.ReadReq_miss_latency::total 2440787473 # number of ReadReq miss cycles
1419 system.cpu5.l1c.WriteReq_miss_latency::cpu5 1818333892 # number of WriteReq miss cycles
1420 system.cpu5.l1c.WriteReq_miss_latency::total 1818333892 # number of WriteReq miss cycles
1421 system.cpu5.l1c.demand_miss_latency::cpu5 4259121365 # number of demand (read+write) miss cycles
1422 system.cpu5.l1c.demand_miss_latency::total 4259121365 # number of demand (read+write) miss cycles
1423 system.cpu5.l1c.overall_miss_latency::cpu5 4259121365 # number of overall miss cycles
1424 system.cpu5.l1c.overall_miss_latency::total 4259121365 # number of overall miss cycles
1425 system.cpu5.l1c.ReadReq_accesses::cpu5 44888 # number of ReadReq accesses(hits+misses)
1426 system.cpu5.l1c.ReadReq_accesses::total 44888 # number of ReadReq accesses(hits+misses)
1427 system.cpu5.l1c.WriteReq_accesses::cpu5 24283 # number of WriteReq accesses(hits+misses)
1428 system.cpu5.l1c.WriteReq_accesses::total 24283 # number of WriteReq accesses(hits+misses)
1429 system.cpu5.l1c.demand_accesses::cpu5 69171 # number of demand (read+write) accesses
1430 system.cpu5.l1c.demand_accesses::total 69171 # number of demand (read+write) accesses
1431 system.cpu5.l1c.overall_accesses::cpu5 69171 # number of overall (read+write) accesses
1432 system.cpu5.l1c.overall_accesses::total 69171 # number of overall (read+write) accesses
1433 system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.806229 # miss rate for ReadReq accesses
1434 system.cpu5.l1c.ReadReq_miss_rate::total 0.806229 # miss rate for ReadReq accesses
1435 system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.954907 # miss rate for WriteReq accesses
1436 system.cpu5.l1c.WriteReq_miss_rate::total 0.954907 # miss rate for WriteReq accesses
1437 system.cpu5.l1c.demand_miss_rate::cpu5 0.858423 # miss rate for demand accesses
1438 system.cpu5.l1c.demand_miss_rate::total 0.858423 # miss rate for demand accesses
1439 system.cpu5.l1c.overall_miss_rate::cpu5 0.858423 # miss rate for overall accesses
1440 system.cpu5.l1c.overall_miss_rate::total 0.858423 # miss rate for overall accesses
1441 system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 67443.699171 # average ReadReq miss latency
1442 system.cpu5.l1c.ReadReq_avg_miss_latency::total 67443.699171 # average ReadReq miss latency
1443 system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 78417.021390 # average WriteReq miss latency
1444 system.cpu5.l1c.WriteReq_avg_miss_latency::total 78417.021390 # average WriteReq miss latency
1445 system.cpu5.l1c.demand_avg_miss_latency::cpu5 71728.946159 # average overall miss latency
1446 system.cpu5.l1c.demand_avg_miss_latency::total 71728.946159 # average overall miss latency
1447 system.cpu5.l1c.overall_avg_miss_latency::cpu5 71728.946159 # average overall miss latency
1448 system.cpu5.l1c.overall_avg_miss_latency::total 71728.946159 # average overall miss latency
1449 system.cpu5.l1c.blocked_cycles::no_mshrs 2173855 # number of cycles access was blocked
1450 system.cpu5.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
1451 system.cpu5.l1c.blocked::no_mshrs 59485 # number of cycles access was blocked
1452 system.cpu5.l1c.blocked::no_targets 0 # number of cycles access was blocked
1453 system.cpu5.l1c.avg_blocked_cycles::no_mshrs 36.544591 # average number of cycles each access was blocked
1454 system.cpu5.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1455 system.cpu5.l1c.fast_writes 0 # number of fast writes performed
1456 system.cpu5.l1c.cache_copies 0 # number of cache copies performed
1457 system.cpu5.l1c.writebacks::writebacks 9794 # number of writebacks
1458 system.cpu5.l1c.writebacks::total 9794 # number of writebacks
1459 system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36190 # number of ReadReq MSHR misses
1460 system.cpu5.l1c.ReadReq_mshr_misses::total 36190 # number of ReadReq MSHR misses
1461 system.cpu5.l1c.WriteReq_mshr_misses::cpu5 23188 # number of WriteReq MSHR misses
1462 system.cpu5.l1c.WriteReq_mshr_misses::total 23188 # number of WriteReq MSHR misses
1463 system.cpu5.l1c.demand_mshr_misses::cpu5 59378 # number of demand (read+write) MSHR misses
1464 system.cpu5.l1c.demand_mshr_misses::total 59378 # number of demand (read+write) MSHR misses
1465 system.cpu5.l1c.overall_mshr_misses::cpu5 59378 # number of overall MSHR misses
1466 system.cpu5.l1c.overall_mshr_misses::total 59378 # number of overall MSHR misses
1467 system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 2364411063 # number of ReadReq MSHR miss cycles
1468 system.cpu5.l1c.ReadReq_mshr_miss_latency::total 2364411063 # number of ReadReq MSHR miss cycles
1469 system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 1769767596 # number of WriteReq MSHR miss cycles
1470 system.cpu5.l1c.WriteReq_mshr_miss_latency::total 1769767596 # number of WriteReq MSHR miss cycles
1471 system.cpu5.l1c.demand_mshr_miss_latency::cpu5 4134178659 # number of demand (read+write) MSHR miss cycles
1472 system.cpu5.l1c.demand_mshr_miss_latency::total 4134178659 # number of demand (read+write) MSHR miss cycles
1473 system.cpu5.l1c.overall_mshr_miss_latency::cpu5 4134178659 # number of overall MSHR miss cycles
1474 system.cpu5.l1c.overall_mshr_miss_latency::total 4134178659 # number of overall MSHR miss cycles
1475 system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 1083354468 # number of ReadReq MSHR uncacheable cycles
1476 system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 1083354468 # number of ReadReq MSHR uncacheable cycles
1477 system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 3885222198 # number of WriteReq MSHR uncacheable cycles
1478 system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 3885222198 # number of WriteReq MSHR uncacheable cycles
1479 system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 4968576666 # number of overall MSHR uncacheable cycles
1480 system.cpu5.l1c.overall_mshr_uncacheable_latency::total 4968576666 # number of overall MSHR uncacheable cycles
1481 system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.806229 # mshr miss rate for ReadReq accesses
1482 system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.806229 # mshr miss rate for ReadReq accesses
1483 system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.954907 # mshr miss rate for WriteReq accesses
1484 system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.954907 # mshr miss rate for WriteReq accesses
1485 system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.858423 # mshr miss rate for demand accesses
1486 system.cpu5.l1c.demand_mshr_miss_rate::total 0.858423 # mshr miss rate for demand accesses
1487 system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.858423 # mshr miss rate for overall accesses
1488 system.cpu5.l1c.overall_mshr_miss_rate::total 0.858423 # mshr miss rate for overall accesses
1489 system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 65333.270600 # average ReadReq mshr miss latency
1490 system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 65333.270600 # average ReadReq mshr miss latency
1491 system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 76322.563222 # average WriteReq mshr miss latency
1492 system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 76322.563222 # average WriteReq mshr miss latency
1493 system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 69624.754269 # average overall mshr miss latency
1494 system.cpu5.l1c.demand_avg_mshr_miss_latency::total 69624.754269 # average overall mshr miss latency
1495 system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 69624.754269 # average overall mshr miss latency
1496 system.cpu5.l1c.overall_avg_mshr_miss_latency::total 69624.754269 # average overall mshr miss latency
1497 system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 inf # average ReadReq mshr uncacheable latency
1498 system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1499 system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 inf # average WriteReq mshr uncacheable latency
1500 system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1501 system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 inf # average overall mshr uncacheable latency
1502 system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1503 system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
1504 system.cpu6.num_reads 99150 # number of read accesses completed
1505 system.cpu6.num_writes 53258 # number of write accesses completed
1506 system.cpu6.num_copies 0 # number of copy accesses completed
1507 system.cpu6.l1c.tags.replacements 22399 # number of replacements
1508 system.cpu6.l1c.tags.tagsinuse 397.638402 # Cycle average of tags in use
1509 system.cpu6.l1c.tags.total_refs 13152 # Total number of references to valid blocks.
1510 system.cpu6.l1c.tags.sampled_refs 22779 # Sample count of references to valid blocks.
1511 system.cpu6.l1c.tags.avg_refs 0.577374 # Average number of references to valid blocks.
1512 system.cpu6.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1513 system.cpu6.l1c.tags.occ_blocks::cpu6 397.638402 # Average occupied blocks per requestor
1514 system.cpu6.l1c.tags.occ_percent::cpu6 0.776638 # Average percentage of cache occupancy
1515 system.cpu6.l1c.tags.occ_percent::total 0.776638 # Average percentage of cache occupancy
1516 system.cpu6.l1c.tags.occ_task_id_blocks::1024 380 # Occupied blocks per task id
1517 system.cpu6.l1c.tags.age_task_id_blocks_1024::0 246 # Occupied blocks per task id
1518 system.cpu6.l1c.tags.age_task_id_blocks_1024::1 134 # Occupied blocks per task id
1519 system.cpu6.l1c.tags.occ_task_id_percent::1024 0.742188 # Percentage of cache occupancy per task id
1520 system.cpu6.l1c.tags.tag_accesses 330920 # Number of tag accesses
1521 system.cpu6.l1c.tags.data_accesses 330920 # Number of data accesses
1522 system.cpu6.l1c.ReadReq_hits::cpu6 8542 # number of ReadReq hits
1523 system.cpu6.l1c.ReadReq_hits::total 8542 # number of ReadReq hits
1524 system.cpu6.l1c.WriteReq_hits::cpu6 1117 # number of WriteReq hits
1525 system.cpu6.l1c.WriteReq_hits::total 1117 # number of WriteReq hits
1526 system.cpu6.l1c.demand_hits::cpu6 9659 # number of demand (read+write) hits
1527 system.cpu6.l1c.demand_hits::total 9659 # number of demand (read+write) hits
1528 system.cpu6.l1c.overall_hits::cpu6 9659 # number of overall hits
1529 system.cpu6.l1c.overall_hits::total 9659 # number of overall hits
1530 system.cpu6.l1c.ReadReq_misses::cpu6 36110 # number of ReadReq misses
1531 system.cpu6.l1c.ReadReq_misses::total 36110 # number of ReadReq misses
1532 system.cpu6.l1c.WriteReq_misses::cpu6 23056 # number of WriteReq misses
1533 system.cpu6.l1c.WriteReq_misses::total 23056 # number of WriteReq misses
1534 system.cpu6.l1c.demand_misses::cpu6 59166 # number of demand (read+write) misses
1535 system.cpu6.l1c.demand_misses::total 59166 # number of demand (read+write) misses
1536 system.cpu6.l1c.overall_misses::cpu6 59166 # number of overall misses
1537 system.cpu6.l1c.overall_misses::total 59166 # number of overall misses
1538 system.cpu6.l1c.ReadReq_miss_latency::cpu6 2440095733 # number of ReadReq miss cycles
1539 system.cpu6.l1c.ReadReq_miss_latency::total 2440095733 # number of ReadReq miss cycles
1540 system.cpu6.l1c.WriteReq_miss_latency::cpu6 1804973992 # number of WriteReq miss cycles
1541 system.cpu6.l1c.WriteReq_miss_latency::total 1804973992 # number of WriteReq miss cycles
1542 system.cpu6.l1c.demand_miss_latency::cpu6 4245069725 # number of demand (read+write) miss cycles
1543 system.cpu6.l1c.demand_miss_latency::total 4245069725 # number of demand (read+write) miss cycles
1544 system.cpu6.l1c.overall_miss_latency::cpu6 4245069725 # number of overall miss cycles
1545 system.cpu6.l1c.overall_miss_latency::total 4245069725 # number of overall miss cycles
1546 system.cpu6.l1c.ReadReq_accesses::cpu6 44652 # number of ReadReq accesses(hits+misses)
1547 system.cpu6.l1c.ReadReq_accesses::total 44652 # number of ReadReq accesses(hits+misses)
1548 system.cpu6.l1c.WriteReq_accesses::cpu6 24173 # number of WriteReq accesses(hits+misses)
1549 system.cpu6.l1c.WriteReq_accesses::total 24173 # number of WriteReq accesses(hits+misses)
1550 system.cpu6.l1c.demand_accesses::cpu6 68825 # number of demand (read+write) accesses
1551 system.cpu6.l1c.demand_accesses::total 68825 # number of demand (read+write) accesses
1552 system.cpu6.l1c.overall_accesses::cpu6 68825 # number of overall (read+write) accesses
1553 system.cpu6.l1c.overall_accesses::total 68825 # number of overall (read+write) accesses
1554 system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.808698 # miss rate for ReadReq accesses
1555 system.cpu6.l1c.ReadReq_miss_rate::total 0.808698 # miss rate for ReadReq accesses
1556 system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.953791 # miss rate for WriteReq accesses
1557 system.cpu6.l1c.WriteReq_miss_rate::total 0.953791 # miss rate for WriteReq accesses
1558 system.cpu6.l1c.demand_miss_rate::cpu6 0.859659 # miss rate for demand accesses
1559 system.cpu6.l1c.demand_miss_rate::total 0.859659 # miss rate for demand accesses
1560 system.cpu6.l1c.overall_miss_rate::cpu6 0.859659 # miss rate for overall accesses
1561 system.cpu6.l1c.overall_miss_rate::total 0.859659 # miss rate for overall accesses
1562 system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 67573.961036 # average ReadReq miss latency
1563 system.cpu6.l1c.ReadReq_avg_miss_latency::total 67573.961036 # average ReadReq miss latency
1564 system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 78286.519431 # average WriteReq miss latency
1565 system.cpu6.l1c.WriteReq_avg_miss_latency::total 78286.519431 # average WriteReq miss latency
1566 system.cpu6.l1c.demand_avg_miss_latency::cpu6 71748.465757 # average overall miss latency
1567 system.cpu6.l1c.demand_avg_miss_latency::total 71748.465757 # average overall miss latency
1568 system.cpu6.l1c.overall_avg_miss_latency::cpu6 71748.465757 # average overall miss latency
1569 system.cpu6.l1c.overall_avg_miss_latency::total 71748.465757 # average overall miss latency
1570 system.cpu6.l1c.blocked_cycles::no_mshrs 2172077 # number of cycles access was blocked
1571 system.cpu6.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
1572 system.cpu6.l1c.blocked::no_mshrs 59435 # number of cycles access was blocked
1573 system.cpu6.l1c.blocked::no_targets 0 # number of cycles access was blocked
1574 system.cpu6.l1c.avg_blocked_cycles::no_mshrs 36.545419 # average number of cycles each access was blocked
1575 system.cpu6.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1576 system.cpu6.l1c.fast_writes 0 # number of fast writes performed
1577 system.cpu6.l1c.cache_copies 0 # number of cache copies performed
1578 system.cpu6.l1c.writebacks::writebacks 9755 # number of writebacks
1579 system.cpu6.l1c.writebacks::total 9755 # number of writebacks
1580 system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36110 # number of ReadReq MSHR misses
1581 system.cpu6.l1c.ReadReq_mshr_misses::total 36110 # number of ReadReq MSHR misses
1582 system.cpu6.l1c.WriteReq_mshr_misses::cpu6 23056 # number of WriteReq MSHR misses
1583 system.cpu6.l1c.WriteReq_mshr_misses::total 23056 # number of WriteReq MSHR misses
1584 system.cpu6.l1c.demand_mshr_misses::cpu6 59166 # number of demand (read+write) MSHR misses
1585 system.cpu6.l1c.demand_mshr_misses::total 59166 # number of demand (read+write) MSHR misses
1586 system.cpu6.l1c.overall_mshr_misses::cpu6 59166 # number of overall MSHR misses
1587 system.cpu6.l1c.overall_mshr_misses::total 59166 # number of overall MSHR misses
1588 system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 2363759609 # number of ReadReq MSHR miss cycles
1589 system.cpu6.l1c.ReadReq_mshr_miss_latency::total 2363759609 # number of ReadReq MSHR miss cycles
1590 system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 1756697682 # number of WriteReq MSHR miss cycles
1591 system.cpu6.l1c.WriteReq_mshr_miss_latency::total 1756697682 # number of WriteReq MSHR miss cycles
1592 system.cpu6.l1c.demand_mshr_miss_latency::cpu6 4120457291 # number of demand (read+write) MSHR miss cycles
1593 system.cpu6.l1c.demand_mshr_miss_latency::total 4120457291 # number of demand (read+write) MSHR miss cycles
1594 system.cpu6.l1c.overall_mshr_miss_latency::cpu6 4120457291 # number of overall MSHR miss cycles
1595 system.cpu6.l1c.overall_mshr_miss_latency::total 4120457291 # number of overall MSHR miss cycles
1596 system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 1098306924 # number of ReadReq MSHR uncacheable cycles
1597 system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 1098306924 # number of ReadReq MSHR uncacheable cycles
1598 system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 3880453768 # number of WriteReq MSHR uncacheable cycles
1599 system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 3880453768 # number of WriteReq MSHR uncacheable cycles
1600 system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 4978760692 # number of overall MSHR uncacheable cycles
1601 system.cpu6.l1c.overall_mshr_uncacheable_latency::total 4978760692 # number of overall MSHR uncacheable cycles
1602 system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.808698 # mshr miss rate for ReadReq accesses
1603 system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.808698 # mshr miss rate for ReadReq accesses
1604 system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.953791 # mshr miss rate for WriteReq accesses
1605 system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.953791 # mshr miss rate for WriteReq accesses
1606 system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.859659 # mshr miss rate for demand accesses
1607 system.cpu6.l1c.demand_mshr_miss_rate::total 0.859659 # mshr miss rate for demand accesses
1608 system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.859659 # mshr miss rate for overall accesses
1609 system.cpu6.l1c.overall_mshr_miss_rate::total 0.859659 # mshr miss rate for overall accesses
1610 system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 65459.972556 # average ReadReq mshr miss latency
1611 system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 65459.972556 # average ReadReq mshr miss latency
1612 system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 76192.647554 # average WriteReq mshr miss latency
1613 system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 76192.647554 # average WriteReq mshr miss latency
1614 system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 69642.316381 # average overall mshr miss latency
1615 system.cpu6.l1c.demand_avg_mshr_miss_latency::total 69642.316381 # average overall mshr miss latency
1616 system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 69642.316381 # average overall mshr miss latency
1617 system.cpu6.l1c.overall_avg_mshr_miss_latency::total 69642.316381 # average overall mshr miss latency
1618 system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 inf # average ReadReq mshr uncacheable latency
1619 system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1620 system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 inf # average WriteReq mshr uncacheable latency
1621 system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1622 system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 inf # average overall mshr uncacheable latency
1623 system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1624 system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
1625 system.cpu7.num_reads 99292 # number of read accesses completed
1626 system.cpu7.num_writes 53734 # number of write accesses completed
1627 system.cpu7.num_copies 0 # number of copy accesses completed
1628 system.cpu7.l1c.tags.replacements 22176 # number of replacements
1629 system.cpu7.l1c.tags.tagsinuse 397.484138 # Cycle average of tags in use
1630 system.cpu7.l1c.tags.total_refs 13353 # Total number of references to valid blocks.
1631 system.cpu7.l1c.tags.sampled_refs 22564 # Sample count of references to valid blocks.
1632 system.cpu7.l1c.tags.avg_refs 0.591783 # Average number of references to valid blocks.
1633 system.cpu7.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1634 system.cpu7.l1c.tags.occ_blocks::cpu7 397.484138 # Average occupied blocks per requestor
1635 system.cpu7.l1c.tags.occ_percent::cpu7 0.776336 # Average percentage of cache occupancy
1636 system.cpu7.l1c.tags.occ_percent::total 0.776336 # Average percentage of cache occupancy
1637 system.cpu7.l1c.tags.occ_task_id_blocks::1024 388 # Occupied blocks per task id
1638 system.cpu7.l1c.tags.age_task_id_blocks_1024::0 261 # Occupied blocks per task id
1639 system.cpu7.l1c.tags.age_task_id_blocks_1024::1 127 # Occupied blocks per task id
1640 system.cpu7.l1c.tags.occ_task_id_percent::1024 0.757812 # Percentage of cache occupancy per task id
1641 system.cpu7.l1c.tags.tag_accesses 330932 # Number of tag accesses
1642 system.cpu7.l1c.tags.data_accesses 330932 # Number of data accesses
1643 system.cpu7.l1c.ReadReq_hits::cpu7 8693 # number of ReadReq hits
1644 system.cpu7.l1c.ReadReq_hits::total 8693 # number of ReadReq hits
1645 system.cpu7.l1c.WriteReq_hits::cpu7 1154 # number of WriteReq hits
1646 system.cpu7.l1c.WriteReq_hits::total 1154 # number of WriteReq hits
1647 system.cpu7.l1c.demand_hits::cpu7 9847 # number of demand (read+write) hits
1648 system.cpu7.l1c.demand_hits::total 9847 # number of demand (read+write) hits
1649 system.cpu7.l1c.overall_hits::cpu7 9847 # number of overall hits
1650 system.cpu7.l1c.overall_hits::total 9847 # number of overall hits
1651 system.cpu7.l1c.ReadReq_misses::cpu7 36097 # number of ReadReq misses
1652 system.cpu7.l1c.ReadReq_misses::total 36097 # number of ReadReq misses
1653 system.cpu7.l1c.WriteReq_misses::cpu7 22922 # number of WriteReq misses
1654 system.cpu7.l1c.WriteReq_misses::total 22922 # number of WriteReq misses
1655 system.cpu7.l1c.demand_misses::cpu7 59019 # number of demand (read+write) misses
1656 system.cpu7.l1c.demand_misses::total 59019 # number of demand (read+write) misses
1657 system.cpu7.l1c.overall_misses::cpu7 59019 # number of overall misses
1658 system.cpu7.l1c.overall_misses::total 59019 # number of overall misses
1659 system.cpu7.l1c.ReadReq_miss_latency::cpu7 2444006416 # number of ReadReq miss cycles
1660 system.cpu7.l1c.ReadReq_miss_latency::total 2444006416 # number of ReadReq miss cycles
1661 system.cpu7.l1c.WriteReq_miss_latency::cpu7 1801319117 # number of WriteReq miss cycles
1662 system.cpu7.l1c.WriteReq_miss_latency::total 1801319117 # number of WriteReq miss cycles
1663 system.cpu7.l1c.demand_miss_latency::cpu7 4245325533 # number of demand (read+write) miss cycles
1664 system.cpu7.l1c.demand_miss_latency::total 4245325533 # number of demand (read+write) miss cycles
1665 system.cpu7.l1c.overall_miss_latency::cpu7 4245325533 # number of overall miss cycles
1666 system.cpu7.l1c.overall_miss_latency::total 4245325533 # number of overall miss cycles
1667 system.cpu7.l1c.ReadReq_accesses::cpu7 44790 # number of ReadReq accesses(hits+misses)
1668 system.cpu7.l1c.ReadReq_accesses::total 44790 # number of ReadReq accesses(hits+misses)
1669 system.cpu7.l1c.WriteReq_accesses::cpu7 24076 # number of WriteReq accesses(hits+misses)
1670 system.cpu7.l1c.WriteReq_accesses::total 24076 # number of WriteReq accesses(hits+misses)
1671 system.cpu7.l1c.demand_accesses::cpu7 68866 # number of demand (read+write) accesses
1672 system.cpu7.l1c.demand_accesses::total 68866 # number of demand (read+write) accesses
1673 system.cpu7.l1c.overall_accesses::cpu7 68866 # number of overall (read+write) accesses
1674 system.cpu7.l1c.overall_accesses::total 68866 # number of overall (read+write) accesses
1675 system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.805916 # miss rate for ReadReq accesses
1676 system.cpu7.l1c.ReadReq_miss_rate::total 0.805916 # miss rate for ReadReq accesses
1677 system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.952068 # miss rate for WriteReq accesses
1678 system.cpu7.l1c.WriteReq_miss_rate::total 0.952068 # miss rate for WriteReq accesses
1679 system.cpu7.l1c.demand_miss_rate::cpu7 0.857012 # miss rate for demand accesses
1680 system.cpu7.l1c.demand_miss_rate::total 0.857012 # miss rate for demand accesses
1681 system.cpu7.l1c.overall_miss_rate::cpu7 0.857012 # miss rate for overall accesses
1682 system.cpu7.l1c.overall_miss_rate::total 0.857012 # miss rate for overall accesses
1683 system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 67706.635344 # average ReadReq miss latency
1684 system.cpu7.l1c.ReadReq_avg_miss_latency::total 67706.635344 # average ReadReq miss latency
1685 system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 78584.727205 # average WriteReq miss latency
1686 system.cpu7.l1c.WriteReq_avg_miss_latency::total 78584.727205 # average WriteReq miss latency
1687 system.cpu7.l1c.demand_avg_miss_latency::cpu7 71931.505668 # average overall miss latency
1688 system.cpu7.l1c.demand_avg_miss_latency::total 71931.505668 # average overall miss latency
1689 system.cpu7.l1c.overall_avg_miss_latency::cpu7 71931.505668 # average overall miss latency
1690 system.cpu7.l1c.overall_avg_miss_latency::total 71931.505668 # average overall miss latency
1691 system.cpu7.l1c.blocked_cycles::no_mshrs 2180293 # number of cycles access was blocked
1692 system.cpu7.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
1693 system.cpu7.l1c.blocked::no_mshrs 59208 # number of cycles access was blocked
1694 system.cpu7.l1c.blocked::no_targets 0 # number of cycles access was blocked
1695 system.cpu7.l1c.avg_blocked_cycles::no_mshrs 36.824297 # average number of cycles each access was blocked
1696 system.cpu7.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1697 system.cpu7.l1c.fast_writes 0 # number of fast writes performed
1698 system.cpu7.l1c.cache_copies 0 # number of cache copies performed
1699 system.cpu7.l1c.writebacks::writebacks 9569 # number of writebacks
1700 system.cpu7.l1c.writebacks::total 9569 # number of writebacks
1701 system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36097 # number of ReadReq MSHR misses
1702 system.cpu7.l1c.ReadReq_mshr_misses::total 36097 # number of ReadReq MSHR misses
1703 system.cpu7.l1c.WriteReq_mshr_misses::cpu7 22922 # number of WriteReq MSHR misses
1704 system.cpu7.l1c.WriteReq_mshr_misses::total 22922 # number of WriteReq MSHR misses
1705 system.cpu7.l1c.demand_mshr_misses::cpu7 59019 # number of demand (read+write) MSHR misses
1706 system.cpu7.l1c.demand_mshr_misses::total 59019 # number of demand (read+write) MSHR misses
1707 system.cpu7.l1c.overall_mshr_misses::cpu7 59019 # number of overall MSHR misses
1708 system.cpu7.l1c.overall_mshr_misses::total 59019 # number of overall MSHR misses
1709 system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 2367752098 # number of ReadReq MSHR miss cycles
1710 system.cpu7.l1c.ReadReq_mshr_miss_latency::total 2367752098 # number of ReadReq MSHR miss cycles
1711 system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 1753332745 # number of WriteReq MSHR miss cycles
1712 system.cpu7.l1c.WriteReq_mshr_miss_latency::total 1753332745 # number of WriteReq MSHR miss cycles
1713 system.cpu7.l1c.demand_mshr_miss_latency::cpu7 4121084843 # number of demand (read+write) MSHR miss cycles
1714 system.cpu7.l1c.demand_mshr_miss_latency::total 4121084843 # number of demand (read+write) MSHR miss cycles
1715 system.cpu7.l1c.overall_mshr_miss_latency::cpu7 4121084843 # number of overall MSHR miss cycles
1716 system.cpu7.l1c.overall_mshr_miss_latency::total 4121084843 # number of overall MSHR miss cycles
1717 system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 1099641500 # number of ReadReq MSHR uncacheable cycles
1718 system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 1099641500 # number of ReadReq MSHR uncacheable cycles
1719 system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 3936158285 # number of WriteReq MSHR uncacheable cycles
1720 system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 3936158285 # number of WriteReq MSHR uncacheable cycles
1721 system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 5035799785 # number of overall MSHR uncacheable cycles
1722 system.cpu7.l1c.overall_mshr_uncacheable_latency::total 5035799785 # number of overall MSHR uncacheable cycles
1723 system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.805916 # mshr miss rate for ReadReq accesses
1724 system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.805916 # mshr miss rate for ReadReq accesses
1725 system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.952068 # mshr miss rate for WriteReq accesses
1726 system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.952068 # mshr miss rate for WriteReq accesses
1727 system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.857012 # mshr miss rate for demand accesses
1728 system.cpu7.l1c.demand_mshr_miss_rate::total 0.857012 # mshr miss rate for demand accesses
1729 system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.857012 # mshr miss rate for overall accesses
1730 system.cpu7.l1c.overall_mshr_miss_rate::total 0.857012 # mshr miss rate for overall accesses
1731 system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 65594.151813 # average ReadReq mshr miss latency
1732 system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 65594.151813 # average ReadReq mshr miss latency
1733 system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 76491.263633 # average WriteReq mshr miss latency
1734 system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 76491.263633 # average WriteReq mshr miss latency
1735 system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 69826.409173 # average overall mshr miss latency
1736 system.cpu7.l1c.demand_avg_mshr_miss_latency::total 69826.409173 # average overall mshr miss latency
1737 system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 69826.409173 # average overall mshr miss latency
1738 system.cpu7.l1c.overall_avg_mshr_miss_latency::total 69826.409173 # average overall mshr miss latency
1739 system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 inf # average ReadReq mshr uncacheable latency
1740 system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1741 system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 inf # average WriteReq mshr uncacheable latency
1742 system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1743 system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 inf # average overall mshr uncacheable latency
1744 system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1745 system.cpu7.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
1747 ---------- End Simulation Statistics ----------
projects / gem5.git / blob