2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.134742 # Number of seconds simulated
4 sim_ticks 134741611500 # Number of ticks simulated
5 final_tick 134741611500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 947641 # Simulator instruction rate (inst/s)
8 host_op_rate 947641 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 1445388793 # Simulator tick rate (ticks/s)
10 host_mem_usage 301064 # Number of bytes of host memory used
11 host_seconds 93.22 # Real time elapsed on the host
12 sim_insts 88340673 # Number of instructions simulated
13 sim_ops 88340673 # Number of ops (including micro ops) simulated
14 system.voltage_domain.voltage 1 # Voltage in Volts
15 system.clk_domain.clock 1000 # Clock period in ticks
16 system.physmem.bytes_read::cpu.inst 367360 # Number of bytes read from this memory
17 system.physmem.bytes_read::cpu.data 10138112 # Number of bytes read from this memory
18 system.physmem.bytes_read::total 10505472 # Number of bytes read from this memory
19 system.physmem.bytes_inst_read::cpu.inst 367360 # Number of instructions bytes read from this memory
20 system.physmem.bytes_inst_read::total 367360 # Number of instructions bytes read from this memory
21 system.physmem.bytes_written::writebacks 7320448 # Number of bytes written to this memory
22 system.physmem.bytes_written::total 7320448 # Number of bytes written to this memory
23 system.physmem.num_reads::cpu.inst 5740 # Number of read requests responded to by this memory
24 system.physmem.num_reads::cpu.data 158408 # Number of read requests responded to by this memory
25 system.physmem.num_reads::total 164148 # Number of read requests responded to by this memory
26 system.physmem.num_writes::writebacks 114382 # Number of write requests responded to by this memory
27 system.physmem.num_writes::total 114382 # Number of write requests responded to by this memory
28 system.physmem.bw_read::cpu.inst 2726403 # Total read bandwidth from this memory (bytes/s)
29 system.physmem.bw_read::cpu.data 75241137 # Total read bandwidth from this memory (bytes/s)
30 system.physmem.bw_read::total 77967540 # Total read bandwidth from this memory (bytes/s)
31 system.physmem.bw_inst_read::cpu.inst 2726403 # Instruction read bandwidth from this memory (bytes/s)
32 system.physmem.bw_inst_read::total 2726403 # Instruction read bandwidth from this memory (bytes/s)
33 system.physmem.bw_write::writebacks 54329527 # Write bandwidth from this memory (bytes/s)
34 system.physmem.bw_write::total 54329527 # Write bandwidth from this memory (bytes/s)
35 system.physmem.bw_total::writebacks 54329527 # Total bandwidth to/from this memory (bytes/s)
36 system.physmem.bw_total::cpu.inst 2726403 # Total bandwidth to/from this memory (bytes/s)
37 system.physmem.bw_total::cpu.data 75241137 # Total bandwidth to/from this memory (bytes/s)
38 system.physmem.bw_total::total 132297067 # Total bandwidth to/from this memory (bytes/s)
39 system.cpu_clk_domain.clock 500 # Clock period in ticks
40 system.cpu.dtb.fetch_hits 0 # ITB hits
41 system.cpu.dtb.fetch_misses 0 # ITB misses
42 system.cpu.dtb.fetch_acv 0 # ITB acv
43 system.cpu.dtb.fetch_accesses 0 # ITB accesses
44 system.cpu.dtb.read_hits 20276638 # DTB read hits
45 system.cpu.dtb.read_misses 90148 # DTB read misses
46 system.cpu.dtb.read_acv 0 # DTB read access violations
47 system.cpu.dtb.read_accesses 20366786 # DTB read accesses
48 system.cpu.dtb.write_hits 14613377 # DTB write hits
49 system.cpu.dtb.write_misses 7252 # DTB write misses
50 system.cpu.dtb.write_acv 0 # DTB write access violations
51 system.cpu.dtb.write_accesses 14620629 # DTB write accesses
52 system.cpu.dtb.data_hits 34890015 # DTB hits
53 system.cpu.dtb.data_misses 97400 # DTB misses
54 system.cpu.dtb.data_acv 0 # DTB access violations
55 system.cpu.dtb.data_accesses 34987415 # DTB accesses
56 system.cpu.itb.fetch_hits 88438074 # ITB hits
57 system.cpu.itb.fetch_misses 3934 # ITB misses
58 system.cpu.itb.fetch_acv 0 # ITB acv
59 system.cpu.itb.fetch_accesses 88442008 # ITB accesses
60 system.cpu.itb.read_hits 0 # DTB read hits
61 system.cpu.itb.read_misses 0 # DTB read misses
62 system.cpu.itb.read_acv 0 # DTB read access violations
63 system.cpu.itb.read_accesses 0 # DTB read accesses
64 system.cpu.itb.write_hits 0 # DTB write hits
65 system.cpu.itb.write_misses 0 # DTB write misses
66 system.cpu.itb.write_acv 0 # DTB write access violations
67 system.cpu.itb.write_accesses 0 # DTB write accesses
68 system.cpu.itb.data_hits 0 # DTB hits
69 system.cpu.itb.data_misses 0 # DTB misses
70 system.cpu.itb.data_acv 0 # DTB access violations
71 system.cpu.itb.data_accesses 0 # DTB accesses
72 system.cpu.workload.num_syscalls 4583 # Number of system calls
73 system.cpu.numCycles 269483223 # number of cpu cycles simulated
74 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
75 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
76 system.cpu.committedInsts 88340673 # Number of instructions committed
77 system.cpu.committedOps 88340673 # Number of ops (including micro ops) committed
78 system.cpu.num_int_alu_accesses 78039444 # Number of integer alu accesses
79 system.cpu.num_fp_alu_accesses 267757 # Number of float alu accesses
80 system.cpu.num_func_calls 3321606 # number of times a function call or return occured
81 system.cpu.num_conditional_control_insts 8920848 # number of instructions that are conditional controls
82 system.cpu.num_int_insts 78039444 # number of integer instructions
83 system.cpu.num_fp_insts 267757 # number of float instructions
84 system.cpu.num_int_register_reads 105931758 # number of times the integer registers were read
85 system.cpu.num_int_register_writes 52319251 # number of times the integer registers were written
86 system.cpu.num_fp_register_reads 229023 # number of times the floating registers were read
87 system.cpu.num_fp_register_writes 227630 # number of times the floating registers were written
88 system.cpu.num_mem_refs 34987415 # number of memory refs
89 system.cpu.num_load_insts 20366786 # Number of load instructions
90 system.cpu.num_store_insts 14620629 # Number of store instructions
91 system.cpu.num_idle_cycles 0 # Number of idle cycles
92 system.cpu.num_busy_cycles 269483223 # Number of busy cycles
93 system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
94 system.cpu.idle_fraction 0 # Percentage of idle cycles
95 system.cpu.Branches 13754477 # Number of branches fetched
96 system.cpu.op_class::No_OpClass 8748916 9.89% 9.89% # Class of executed instruction
97 system.cpu.op_class::IntAlu 44394799 50.20% 60.09% # Class of executed instruction
98 system.cpu.op_class::IntMult 41101 0.05% 60.14% # Class of executed instruction
99 system.cpu.op_class::IntDiv 0 0.00% 60.14% # Class of executed instruction
100 system.cpu.op_class::FloatAdd 114304 0.13% 60.27% # Class of executed instruction
101 system.cpu.op_class::FloatCmp 84 0.00% 60.27% # Class of executed instruction
102 system.cpu.op_class::FloatCvt 113640 0.13% 60.40% # Class of executed instruction
103 system.cpu.op_class::FloatMult 50 0.00% 60.40% # Class of executed instruction
104 system.cpu.op_class::FloatDiv 37764 0.04% 60.44% # Class of executed instruction
105 system.cpu.op_class::FloatSqrt 0 0.00% 60.44% # Class of executed instruction
106 system.cpu.op_class::SimdAdd 0 0.00% 60.44% # Class of executed instruction
107 system.cpu.op_class::SimdAddAcc 0 0.00% 60.44% # Class of executed instruction
108 system.cpu.op_class::SimdAlu 0 0.00% 60.44% # Class of executed instruction
109 system.cpu.op_class::SimdCmp 0 0.00% 60.44% # Class of executed instruction
110 system.cpu.op_class::SimdCvt 0 0.00% 60.44% # Class of executed instruction
111 system.cpu.op_class::SimdMisc 0 0.00% 60.44% # Class of executed instruction
112 system.cpu.op_class::SimdMult 0 0.00% 60.44% # Class of executed instruction
113 system.cpu.op_class::SimdMultAcc 0 0.00% 60.44% # Class of executed instruction
114 system.cpu.op_class::SimdShift 0 0.00% 60.44% # Class of executed instruction
115 system.cpu.op_class::SimdShiftAcc 0 0.00% 60.44% # Class of executed instruction
116 system.cpu.op_class::SimdSqrt 0 0.00% 60.44% # Class of executed instruction
117 system.cpu.op_class::SimdFloatAdd 0 0.00% 60.44% # Class of executed instruction
118 system.cpu.op_class::SimdFloatAlu 0 0.00% 60.44% # Class of executed instruction
119 system.cpu.op_class::SimdFloatCmp 0 0.00% 60.44% # Class of executed instruction
120 system.cpu.op_class::SimdFloatCvt 0 0.00% 60.44% # Class of executed instruction
121 system.cpu.op_class::SimdFloatDiv 0 0.00% 60.44% # Class of executed instruction
122 system.cpu.op_class::SimdFloatMisc 0 0.00% 60.44% # Class of executed instruction
123 system.cpu.op_class::SimdFloatMult 0 0.00% 60.44% # Class of executed instruction
124 system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.44% # Class of executed instruction
125 system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.44% # Class of executed instruction
126 system.cpu.op_class::MemRead 20366786 23.03% 83.47% # Class of executed instruction
127 system.cpu.op_class::MemWrite 14620629 16.53% 100.00% # Class of executed instruction
128 system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
129 system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
130 system.cpu.op_class::total 88438073 # Class of executed instruction
131 system.cpu.dcache.tags.replacements 200248 # number of replacements
132 system.cpu.dcache.tags.tagsinuse 4078.397630 # Cycle average of tags in use
133 system.cpu.dcache.tags.total_refs 34685671 # Total number of references to valid blocks.
134 system.cpu.dcache.tags.sampled_refs 204344 # Sample count of references to valid blocks.
135 system.cpu.dcache.tags.avg_refs 169.741568 # Average number of references to valid blocks.
136 system.cpu.dcache.tags.warmup_cycle 983457500 # Cycle when the warmup percentage was hit.
137 system.cpu.dcache.tags.occ_blocks::cpu.data 4078.397630 # Average occupied blocks per requestor
138 system.cpu.dcache.tags.occ_percent::cpu.data 0.995703 # Average percentage of cache occupancy
139 system.cpu.dcache.tags.occ_percent::total 0.995703 # Average percentage of cache occupancy
140 system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
141 system.cpu.dcache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id
142 system.cpu.dcache.tags.age_task_id_blocks_1024::1 454 # Occupied blocks per task id
143 system.cpu.dcache.tags.age_task_id_blocks_1024::2 3595 # Occupied blocks per task id
144 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
145 system.cpu.dcache.tags.tag_accesses 69984374 # Number of tag accesses
146 system.cpu.dcache.tags.data_accesses 69984374 # Number of data accesses
147 system.cpu.dcache.ReadReq_hits::cpu.data 20215872 # number of ReadReq hits
148 system.cpu.dcache.ReadReq_hits::total 20215872 # number of ReadReq hits
149 system.cpu.dcache.WriteReq_hits::cpu.data 14469799 # number of WriteReq hits
150 system.cpu.dcache.WriteReq_hits::total 14469799 # number of WriteReq hits
151 system.cpu.dcache.demand_hits::cpu.data 34685671 # number of demand (read+write) hits
152 system.cpu.dcache.demand_hits::total 34685671 # number of demand (read+write) hits
153 system.cpu.dcache.overall_hits::cpu.data 34685671 # number of overall hits
154 system.cpu.dcache.overall_hits::total 34685671 # number of overall hits
155 system.cpu.dcache.ReadReq_misses::cpu.data 60766 # number of ReadReq misses
156 system.cpu.dcache.ReadReq_misses::total 60766 # number of ReadReq misses
157 system.cpu.dcache.WriteReq_misses::cpu.data 143578 # number of WriteReq misses
158 system.cpu.dcache.WriteReq_misses::total 143578 # number of WriteReq misses
159 system.cpu.dcache.demand_misses::cpu.data 204344 # number of demand (read+write) misses
160 system.cpu.dcache.demand_misses::total 204344 # number of demand (read+write) misses
161 system.cpu.dcache.overall_misses::cpu.data 204344 # number of overall misses
162 system.cpu.dcache.overall_misses::total 204344 # number of overall misses
163 system.cpu.dcache.ReadReq_miss_latency::cpu.data 2138978000 # number of ReadReq miss cycles
164 system.cpu.dcache.ReadReq_miss_latency::total 2138978000 # number of ReadReq miss cycles
165 system.cpu.dcache.WriteReq_miss_latency::cpu.data 8279807000 # number of WriteReq miss cycles
166 system.cpu.dcache.WriteReq_miss_latency::total 8279807000 # number of WriteReq miss cycles
167 system.cpu.dcache.demand_miss_latency::cpu.data 10418785000 # number of demand (read+write) miss cycles
168 system.cpu.dcache.demand_miss_latency::total 10418785000 # number of demand (read+write) miss cycles
169 system.cpu.dcache.overall_miss_latency::cpu.data 10418785000 # number of overall miss cycles
170 system.cpu.dcache.overall_miss_latency::total 10418785000 # number of overall miss cycles
171 system.cpu.dcache.ReadReq_accesses::cpu.data 20276638 # number of ReadReq accesses(hits+misses)
172 system.cpu.dcache.ReadReq_accesses::total 20276638 # number of ReadReq accesses(hits+misses)
173 system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses)
174 system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses)
175 system.cpu.dcache.demand_accesses::cpu.data 34890015 # number of demand (read+write) accesses
176 system.cpu.dcache.demand_accesses::total 34890015 # number of demand (read+write) accesses
177 system.cpu.dcache.overall_accesses::cpu.data 34890015 # number of overall (read+write) accesses
178 system.cpu.dcache.overall_accesses::total 34890015 # number of overall (read+write) accesses
179 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002997 # miss rate for ReadReq accesses
180 system.cpu.dcache.ReadReq_miss_rate::total 0.002997 # miss rate for ReadReq accesses
181 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009825 # miss rate for WriteReq accesses
182 system.cpu.dcache.WriteReq_miss_rate::total 0.009825 # miss rate for WriteReq accesses
183 system.cpu.dcache.demand_miss_rate::cpu.data 0.005857 # miss rate for demand accesses
184 system.cpu.dcache.demand_miss_rate::total 0.005857 # miss rate for demand accesses
185 system.cpu.dcache.overall_miss_rate::cpu.data 0.005857 # miss rate for overall accesses
186 system.cpu.dcache.overall_miss_rate::total 0.005857 # miss rate for overall accesses
187 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35200.243557 # average ReadReq miss latency
188 system.cpu.dcache.ReadReq_avg_miss_latency::total 35200.243557 # average ReadReq miss latency
189 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 57667.657998 # average WriteReq miss latency
190 system.cpu.dcache.WriteReq_avg_miss_latency::total 57667.657998 # average WriteReq miss latency
191 system.cpu.dcache.demand_avg_miss_latency::cpu.data 50986.498258 # average overall miss latency
192 system.cpu.dcache.demand_avg_miss_latency::total 50986.498258 # average overall miss latency
193 system.cpu.dcache.overall_avg_miss_latency::cpu.data 50986.498258 # average overall miss latency
194 system.cpu.dcache.overall_avg_miss_latency::total 50986.498258 # average overall miss latency
195 system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
196 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
197 system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
198 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
199 system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
200 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
201 system.cpu.dcache.fast_writes 0 # number of fast writes performed
202 system.cpu.dcache.cache_copies 0 # number of cache copies performed
203 system.cpu.dcache.writebacks::writebacks 168278 # number of writebacks
204 system.cpu.dcache.writebacks::total 168278 # number of writebacks
205 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 60766 # number of ReadReq MSHR misses
206 system.cpu.dcache.ReadReq_mshr_misses::total 60766 # number of ReadReq MSHR misses
207 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143578 # number of WriteReq MSHR misses
208 system.cpu.dcache.WriteReq_mshr_misses::total 143578 # number of WriteReq MSHR misses
209 system.cpu.dcache.demand_mshr_misses::cpu.data 204344 # number of demand (read+write) MSHR misses
210 system.cpu.dcache.demand_mshr_misses::total 204344 # number of demand (read+write) MSHR misses
211 system.cpu.dcache.overall_mshr_misses::cpu.data 204344 # number of overall MSHR misses
212 system.cpu.dcache.overall_mshr_misses::total 204344 # number of overall MSHR misses
213 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2078212000 # number of ReadReq MSHR miss cycles
214 system.cpu.dcache.ReadReq_mshr_miss_latency::total 2078212000 # number of ReadReq MSHR miss cycles
215 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8136229000 # number of WriteReq MSHR miss cycles
216 system.cpu.dcache.WriteReq_mshr_miss_latency::total 8136229000 # number of WriteReq MSHR miss cycles
217 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10214441000 # number of demand (read+write) MSHR miss cycles
218 system.cpu.dcache.demand_mshr_miss_latency::total 10214441000 # number of demand (read+write) MSHR miss cycles
219 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10214441000 # number of overall MSHR miss cycles
220 system.cpu.dcache.overall_mshr_miss_latency::total 10214441000 # number of overall MSHR miss cycles
221 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002997 # mshr miss rate for ReadReq accesses
222 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002997 # mshr miss rate for ReadReq accesses
223 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009825 # mshr miss rate for WriteReq accesses
224 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009825 # mshr miss rate for WriteReq accesses
225 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for demand accesses
226 system.cpu.dcache.demand_mshr_miss_rate::total 0.005857 # mshr miss rate for demand accesses
227 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for overall accesses
228 system.cpu.dcache.overall_mshr_miss_rate::total 0.005857 # mshr miss rate for overall accesses
229 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34200.243557 # average ReadReq mshr miss latency
230 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34200.243557 # average ReadReq mshr miss latency
231 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56667.657998 # average WriteReq mshr miss latency
232 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56667.657998 # average WriteReq mshr miss latency
233 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49986.498258 # average overall mshr miss latency
234 system.cpu.dcache.demand_avg_mshr_miss_latency::total 49986.498258 # average overall mshr miss latency
235 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49986.498258 # average overall mshr miss latency
236 system.cpu.dcache.overall_avg_mshr_miss_latency::total 49986.498258 # average overall mshr miss latency
237 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
238 system.cpu.icache.tags.replacements 74391 # number of replacements
239 system.cpu.icache.tags.tagsinuse 1870.507754 # Cycle average of tags in use
240 system.cpu.icache.tags.total_refs 88361638 # Total number of references to valid blocks.
241 system.cpu.icache.tags.sampled_refs 76436 # Sample count of references to valid blocks.
242 system.cpu.icache.tags.avg_refs 1156.021220 # Average number of references to valid blocks.
243 system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
244 system.cpu.icache.tags.occ_blocks::cpu.inst 1870.507754 # Average occupied blocks per requestor
245 system.cpu.icache.tags.occ_percent::cpu.inst 0.913334 # Average percentage of cache occupancy
246 system.cpu.icache.tags.occ_percent::total 0.913334 # Average percentage of cache occupancy
247 system.cpu.icache.tags.occ_task_id_blocks::1024 2045 # Occupied blocks per task id
248 system.cpu.icache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id
249 system.cpu.icache.tags.age_task_id_blocks_1024::1 109 # Occupied blocks per task id
250 system.cpu.icache.tags.age_task_id_blocks_1024::3 191 # Occupied blocks per task id
251 system.cpu.icache.tags.age_task_id_blocks_1024::4 1708 # Occupied blocks per task id
252 system.cpu.icache.tags.occ_task_id_percent::1024 0.998535 # Percentage of cache occupancy per task id
253 system.cpu.icache.tags.tag_accesses 176952584 # Number of tag accesses
254 system.cpu.icache.tags.data_accesses 176952584 # Number of data accesses
255 system.cpu.icache.ReadReq_hits::cpu.inst 88361638 # number of ReadReq hits
256 system.cpu.icache.ReadReq_hits::total 88361638 # number of ReadReq hits
257 system.cpu.icache.demand_hits::cpu.inst 88361638 # number of demand (read+write) hits
258 system.cpu.icache.demand_hits::total 88361638 # number of demand (read+write) hits
259 system.cpu.icache.overall_hits::cpu.inst 88361638 # number of overall hits
260 system.cpu.icache.overall_hits::total 88361638 # number of overall hits
261 system.cpu.icache.ReadReq_misses::cpu.inst 76436 # number of ReadReq misses
262 system.cpu.icache.ReadReq_misses::total 76436 # number of ReadReq misses
263 system.cpu.icache.demand_misses::cpu.inst 76436 # number of demand (read+write) misses
264 system.cpu.icache.demand_misses::total 76436 # number of demand (read+write) misses
265 system.cpu.icache.overall_misses::cpu.inst 76436 # number of overall misses
266 system.cpu.icache.overall_misses::total 76436 # number of overall misses
267 system.cpu.icache.ReadReq_miss_latency::cpu.inst 1275518500 # number of ReadReq miss cycles
268 system.cpu.icache.ReadReq_miss_latency::total 1275518500 # number of ReadReq miss cycles
269 system.cpu.icache.demand_miss_latency::cpu.inst 1275518500 # number of demand (read+write) miss cycles
270 system.cpu.icache.demand_miss_latency::total 1275518500 # number of demand (read+write) miss cycles
271 system.cpu.icache.overall_miss_latency::cpu.inst 1275518500 # number of overall miss cycles
272 system.cpu.icache.overall_miss_latency::total 1275518500 # number of overall miss cycles
273 system.cpu.icache.ReadReq_accesses::cpu.inst 88438074 # number of ReadReq accesses(hits+misses)
274 system.cpu.icache.ReadReq_accesses::total 88438074 # number of ReadReq accesses(hits+misses)
275 system.cpu.icache.demand_accesses::cpu.inst 88438074 # number of demand (read+write) accesses
276 system.cpu.icache.demand_accesses::total 88438074 # number of demand (read+write) accesses
277 system.cpu.icache.overall_accesses::cpu.inst 88438074 # number of overall (read+write) accesses
278 system.cpu.icache.overall_accesses::total 88438074 # number of overall (read+write) accesses
279 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000864 # miss rate for ReadReq accesses
280 system.cpu.icache.ReadReq_miss_rate::total 0.000864 # miss rate for ReadReq accesses
281 system.cpu.icache.demand_miss_rate::cpu.inst 0.000864 # miss rate for demand accesses
282 system.cpu.icache.demand_miss_rate::total 0.000864 # miss rate for demand accesses
283 system.cpu.icache.overall_miss_rate::cpu.inst 0.000864 # miss rate for overall accesses
284 system.cpu.icache.overall_miss_rate::total 0.000864 # miss rate for overall accesses
285 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16687.405149 # average ReadReq miss latency
286 system.cpu.icache.ReadReq_avg_miss_latency::total 16687.405149 # average ReadReq miss latency
287 system.cpu.icache.demand_avg_miss_latency::cpu.inst 16687.405149 # average overall miss latency
288 system.cpu.icache.demand_avg_miss_latency::total 16687.405149 # average overall miss latency
289 system.cpu.icache.overall_avg_miss_latency::cpu.inst 16687.405149 # average overall miss latency
290 system.cpu.icache.overall_avg_miss_latency::total 16687.405149 # average overall miss latency
291 system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
292 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
293 system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
294 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
295 system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
296 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
297 system.cpu.icache.fast_writes 0 # number of fast writes performed
298 system.cpu.icache.cache_copies 0 # number of cache copies performed
299 system.cpu.icache.writebacks::writebacks 74391 # number of writebacks
300 system.cpu.icache.writebacks::total 74391 # number of writebacks
301 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 76436 # number of ReadReq MSHR misses
302 system.cpu.icache.ReadReq_mshr_misses::total 76436 # number of ReadReq MSHR misses
303 system.cpu.icache.demand_mshr_misses::cpu.inst 76436 # number of demand (read+write) MSHR misses
304 system.cpu.icache.demand_mshr_misses::total 76436 # number of demand (read+write) MSHR misses
305 system.cpu.icache.overall_mshr_misses::cpu.inst 76436 # number of overall MSHR misses
306 system.cpu.icache.overall_mshr_misses::total 76436 # number of overall MSHR misses
307 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1199082500 # number of ReadReq MSHR miss cycles
308 system.cpu.icache.ReadReq_mshr_miss_latency::total 1199082500 # number of ReadReq MSHR miss cycles
309 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1199082500 # number of demand (read+write) MSHR miss cycles
310 system.cpu.icache.demand_mshr_miss_latency::total 1199082500 # number of demand (read+write) MSHR miss cycles
311 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1199082500 # number of overall MSHR miss cycles
312 system.cpu.icache.overall_mshr_miss_latency::total 1199082500 # number of overall MSHR miss cycles
313 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000864 # mshr miss rate for ReadReq accesses
314 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000864 # mshr miss rate for ReadReq accesses
315 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000864 # mshr miss rate for demand accesses
316 system.cpu.icache.demand_mshr_miss_rate::total 0.000864 # mshr miss rate for demand accesses
317 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000864 # mshr miss rate for overall accesses
318 system.cpu.icache.overall_mshr_miss_rate::total 0.000864 # mshr miss rate for overall accesses
319 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15687.405149 # average ReadReq mshr miss latency
320 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15687.405149 # average ReadReq mshr miss latency
321 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15687.405149 # average overall mshr miss latency
322 system.cpu.icache.demand_avg_mshr_miss_latency::total 15687.405149 # average overall mshr miss latency
323 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15687.405149 # average overall mshr miss latency
324 system.cpu.icache.overall_avg_mshr_miss_latency::total 15687.405149 # average overall mshr miss latency
325 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
326 system.cpu.l2cache.tags.replacements 131998 # number of replacements
327 system.cpu.l2cache.tags.tagsinuse 30708.485304 # Cycle average of tags in use
328 system.cpu.l2cache.tags.total_refs 247404 # Total number of references to valid blocks.
329 system.cpu.l2cache.tags.sampled_refs 164074 # Sample count of references to valid blocks.
330 system.cpu.l2cache.tags.avg_refs 1.507881 # Average number of references to valid blocks.
331 system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
332 system.cpu.l2cache.tags.occ_blocks::writebacks 27397.900187 # Average occupied blocks per requestor
333 system.cpu.l2cache.tags.occ_blocks::cpu.inst 1667.759999 # Average occupied blocks per requestor
334 system.cpu.l2cache.tags.occ_blocks::cpu.data 1642.825119 # Average occupied blocks per requestor
335 system.cpu.l2cache.tags.occ_percent::writebacks 0.836118 # Average percentage of cache occupancy
336 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.050896 # Average percentage of cache occupancy
337 system.cpu.l2cache.tags.occ_percent::cpu.data 0.050135 # Average percentage of cache occupancy
338 system.cpu.l2cache.tags.occ_percent::total 0.937149 # Average percentage of cache occupancy
339 system.cpu.l2cache.tags.occ_task_id_blocks::1024 32076 # Occupied blocks per task id
340 system.cpu.l2cache.tags.age_task_id_blocks_1024::0 143 # Occupied blocks per task id
341 system.cpu.l2cache.tags.age_task_id_blocks_1024::1 731 # Occupied blocks per task id
342 system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9441 # Occupied blocks per task id
343 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 21639 # Occupied blocks per task id
344 system.cpu.l2cache.tags.age_task_id_blocks_1024::4 122 # Occupied blocks per task id
345 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.978882 # Percentage of cache occupancy per task id
346 system.cpu.l2cache.tags.tag_accesses 4751004 # Number of tag accesses
347 system.cpu.l2cache.tags.data_accesses 4751004 # Number of data accesses
348 system.cpu.l2cache.WritebackDirty_hits::writebacks 168278 # number of WritebackDirty hits
349 system.cpu.l2cache.WritebackDirty_hits::total 168278 # number of WritebackDirty hits
350 system.cpu.l2cache.WritebackClean_hits::writebacks 74391 # number of WritebackClean hits
351 system.cpu.l2cache.WritebackClean_hits::total 74391 # number of WritebackClean hits
352 system.cpu.l2cache.ReadExReq_hits::cpu.data 12696 # number of ReadExReq hits
353 system.cpu.l2cache.ReadExReq_hits::total 12696 # number of ReadExReq hits
354 system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 70696 # number of ReadCleanReq hits
355 system.cpu.l2cache.ReadCleanReq_hits::total 70696 # number of ReadCleanReq hits
356 system.cpu.l2cache.ReadSharedReq_hits::cpu.data 33240 # number of ReadSharedReq hits
357 system.cpu.l2cache.ReadSharedReq_hits::total 33240 # number of ReadSharedReq hits
358 system.cpu.l2cache.demand_hits::cpu.inst 70696 # number of demand (read+write) hits
359 system.cpu.l2cache.demand_hits::cpu.data 45936 # number of demand (read+write) hits
360 system.cpu.l2cache.demand_hits::total 116632 # number of demand (read+write) hits
361 system.cpu.l2cache.overall_hits::cpu.inst 70696 # number of overall hits
362 system.cpu.l2cache.overall_hits::cpu.data 45936 # number of overall hits
363 system.cpu.l2cache.overall_hits::total 116632 # number of overall hits
364 system.cpu.l2cache.ReadExReq_misses::cpu.data 130882 # number of ReadExReq misses
365 system.cpu.l2cache.ReadExReq_misses::total 130882 # number of ReadExReq misses
366 system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 5740 # number of ReadCleanReq misses
367 system.cpu.l2cache.ReadCleanReq_misses::total 5740 # number of ReadCleanReq misses
368 system.cpu.l2cache.ReadSharedReq_misses::cpu.data 27526 # number of ReadSharedReq misses
369 system.cpu.l2cache.ReadSharedReq_misses::total 27526 # number of ReadSharedReq misses
370 system.cpu.l2cache.demand_misses::cpu.inst 5740 # number of demand (read+write) misses
371 system.cpu.l2cache.demand_misses::cpu.data 158408 # number of demand (read+write) misses
372 system.cpu.l2cache.demand_misses::total 164148 # number of demand (read+write) misses
373 system.cpu.l2cache.overall_misses::cpu.inst 5740 # number of overall misses
374 system.cpu.l2cache.overall_misses::cpu.data 158408 # number of overall misses
375 system.cpu.l2cache.overall_misses::total 164148 # number of overall misses
376 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7787542500 # number of ReadExReq miss cycles
377 system.cpu.l2cache.ReadExReq_miss_latency::total 7787542500 # number of ReadExReq miss cycles
378 system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 341866000 # number of ReadCleanReq miss cycles
379 system.cpu.l2cache.ReadCleanReq_miss_latency::total 341866000 # number of ReadCleanReq miss cycles
380 system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1637990000 # number of ReadSharedReq miss cycles
381 system.cpu.l2cache.ReadSharedReq_miss_latency::total 1637990000 # number of ReadSharedReq miss cycles
382 system.cpu.l2cache.demand_miss_latency::cpu.inst 341866000 # number of demand (read+write) miss cycles
383 system.cpu.l2cache.demand_miss_latency::cpu.data 9425532500 # number of demand (read+write) miss cycles
384 system.cpu.l2cache.demand_miss_latency::total 9767398500 # number of demand (read+write) miss cycles
385 system.cpu.l2cache.overall_miss_latency::cpu.inst 341866000 # number of overall miss cycles
386 system.cpu.l2cache.overall_miss_latency::cpu.data 9425532500 # number of overall miss cycles
387 system.cpu.l2cache.overall_miss_latency::total 9767398500 # number of overall miss cycles
388 system.cpu.l2cache.WritebackDirty_accesses::writebacks 168278 # number of WritebackDirty accesses(hits+misses)
389 system.cpu.l2cache.WritebackDirty_accesses::total 168278 # number of WritebackDirty accesses(hits+misses)
390 system.cpu.l2cache.WritebackClean_accesses::writebacks 74391 # number of WritebackClean accesses(hits+misses)
391 system.cpu.l2cache.WritebackClean_accesses::total 74391 # number of WritebackClean accesses(hits+misses)
392 system.cpu.l2cache.ReadExReq_accesses::cpu.data 143578 # number of ReadExReq accesses(hits+misses)
393 system.cpu.l2cache.ReadExReq_accesses::total 143578 # number of ReadExReq accesses(hits+misses)
394 system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 76436 # number of ReadCleanReq accesses(hits+misses)
395 system.cpu.l2cache.ReadCleanReq_accesses::total 76436 # number of ReadCleanReq accesses(hits+misses)
396 system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 60766 # number of ReadSharedReq accesses(hits+misses)
397 system.cpu.l2cache.ReadSharedReq_accesses::total 60766 # number of ReadSharedReq accesses(hits+misses)
398 system.cpu.l2cache.demand_accesses::cpu.inst 76436 # number of demand (read+write) accesses
399 system.cpu.l2cache.demand_accesses::cpu.data 204344 # number of demand (read+write) accesses
400 system.cpu.l2cache.demand_accesses::total 280780 # number of demand (read+write) accesses
401 system.cpu.l2cache.overall_accesses::cpu.inst 76436 # number of overall (read+write) accesses
402 system.cpu.l2cache.overall_accesses::cpu.data 204344 # number of overall (read+write) accesses
403 system.cpu.l2cache.overall_accesses::total 280780 # number of overall (read+write) accesses
404 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.911574 # miss rate for ReadExReq accesses
405 system.cpu.l2cache.ReadExReq_miss_rate::total 0.911574 # miss rate for ReadExReq accesses
406 system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.075096 # miss rate for ReadCleanReq accesses
407 system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.075096 # miss rate for ReadCleanReq accesses
408 system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.452984 # miss rate for ReadSharedReq accesses
409 system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.452984 # miss rate for ReadSharedReq accesses
410 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.075096 # miss rate for demand accesses
411 system.cpu.l2cache.demand_miss_rate::cpu.data 0.775203 # miss rate for demand accesses
412 system.cpu.l2cache.demand_miss_rate::total 0.584614 # miss rate for demand accesses
413 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.075096 # miss rate for overall accesses
414 system.cpu.l2cache.overall_miss_rate::cpu.data 0.775203 # miss rate for overall accesses
415 system.cpu.l2cache.overall_miss_rate::total 0.584614 # miss rate for overall accesses
416 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.485170 # average ReadExReq miss latency
417 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.485170 # average ReadExReq miss latency
418 system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59558.536585 # average ReadCleanReq miss latency
419 system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59558.536585 # average ReadCleanReq miss latency
420 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59507.011553 # average ReadSharedReq miss latency
421 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59507.011553 # average ReadSharedReq miss latency
422 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59558.536585 # average overall miss latency
423 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59501.619236 # average overall miss latency
424 system.cpu.l2cache.demand_avg_miss_latency::total 59503.609547 # average overall miss latency
425 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59558.536585 # average overall miss latency
426 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59501.619236 # average overall miss latency
427 system.cpu.l2cache.overall_avg_miss_latency::total 59503.609547 # average overall miss latency
428 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
429 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
430 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
431 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
432 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
433 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
434 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
435 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
436 system.cpu.l2cache.writebacks::writebacks 114382 # number of writebacks
437 system.cpu.l2cache.writebacks::total 114382 # number of writebacks
438 system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 105 # number of CleanEvict MSHR misses
439 system.cpu.l2cache.CleanEvict_mshr_misses::total 105 # number of CleanEvict MSHR misses
440 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130882 # number of ReadExReq MSHR misses
441 system.cpu.l2cache.ReadExReq_mshr_misses::total 130882 # number of ReadExReq MSHR misses
442 system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 5740 # number of ReadCleanReq MSHR misses
443 system.cpu.l2cache.ReadCleanReq_mshr_misses::total 5740 # number of ReadCleanReq MSHR misses
444 system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 27526 # number of ReadSharedReq MSHR misses
445 system.cpu.l2cache.ReadSharedReq_mshr_misses::total 27526 # number of ReadSharedReq MSHR misses
446 system.cpu.l2cache.demand_mshr_misses::cpu.inst 5740 # number of demand (read+write) MSHR misses
447 system.cpu.l2cache.demand_mshr_misses::cpu.data 158408 # number of demand (read+write) MSHR misses
448 system.cpu.l2cache.demand_mshr_misses::total 164148 # number of demand (read+write) MSHR misses
449 system.cpu.l2cache.overall_mshr_misses::cpu.inst 5740 # number of overall MSHR misses
450 system.cpu.l2cache.overall_mshr_misses::cpu.data 158408 # number of overall MSHR misses
451 system.cpu.l2cache.overall_mshr_misses::total 164148 # number of overall MSHR misses
452 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6478722500 # number of ReadExReq MSHR miss cycles
453 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6478722500 # number of ReadExReq MSHR miss cycles
454 system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 284466000 # number of ReadCleanReq MSHR miss cycles
455 system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 284466000 # number of ReadCleanReq MSHR miss cycles
456 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1362730000 # number of ReadSharedReq MSHR miss cycles
457 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1362730000 # number of ReadSharedReq MSHR miss cycles
458 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 284466000 # number of demand (read+write) MSHR miss cycles
459 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7841452500 # number of demand (read+write) MSHR miss cycles
460 system.cpu.l2cache.demand_mshr_miss_latency::total 8125918500 # number of demand (read+write) MSHR miss cycles
461 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 284466000 # number of overall MSHR miss cycles
462 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7841452500 # number of overall MSHR miss cycles
463 system.cpu.l2cache.overall_mshr_miss_latency::total 8125918500 # number of overall MSHR miss cycles
464 system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
465 system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
466 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911574 # mshr miss rate for ReadExReq accesses
467 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911574 # mshr miss rate for ReadExReq accesses
468 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.075096 # mshr miss rate for ReadCleanReq accesses
469 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.075096 # mshr miss rate for ReadCleanReq accesses
470 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.452984 # mshr miss rate for ReadSharedReq accesses
471 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.452984 # mshr miss rate for ReadSharedReq accesses
472 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.075096 # mshr miss rate for demand accesses
473 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.775203 # mshr miss rate for demand accesses
474 system.cpu.l2cache.demand_mshr_miss_rate::total 0.584614 # mshr miss rate for demand accesses
475 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.075096 # mshr miss rate for overall accesses
476 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.775203 # mshr miss rate for overall accesses
477 system.cpu.l2cache.overall_mshr_miss_rate::total 0.584614 # mshr miss rate for overall accesses
478 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.485170 # average ReadExReq mshr miss latency
479 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.485170 # average ReadExReq mshr miss latency
480 system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49558.536585 # average ReadCleanReq mshr miss latency
481 system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49558.536585 # average ReadCleanReq mshr miss latency
482 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49507.011553 # average ReadSharedReq mshr miss latency
483 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49507.011553 # average ReadSharedReq mshr miss latency
484 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49558.536585 # average overall mshr miss latency
485 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49501.619236 # average overall mshr miss latency
486 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49503.609547 # average overall mshr miss latency
487 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49558.536585 # average overall mshr miss latency
488 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49501.619236 # average overall mshr miss latency
489 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49503.609547 # average overall mshr miss latency
490 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
491 system.cpu.toL2Bus.snoop_filter.tot_requests 555419 # Total number of requests made to the snoop filter.
492 system.cpu.toL2Bus.snoop_filter.hit_single_requests 274639 # Number of requests hitting in the snoop filter with a single holder of the requested data.
493 system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
494 system.cpu.toL2Bus.snoop_filter.tot_snoops 3875 # Total number of snoops made to the snoop filter.
495 system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3875 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
496 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
497 system.cpu.toL2Bus.trans_dist::ReadResp 137202 # Transaction distribution
498 system.cpu.toL2Bus.trans_dist::WritebackDirty 282660 # Transaction distribution
499 system.cpu.toL2Bus.trans_dist::WritebackClean 74391 # Transaction distribution
500 system.cpu.toL2Bus.trans_dist::CleanEvict 49586 # Transaction distribution
501 system.cpu.toL2Bus.trans_dist::ReadExReq 143578 # Transaction distribution
502 system.cpu.toL2Bus.trans_dist::ReadExResp 143578 # Transaction distribution
503 system.cpu.toL2Bus.trans_dist::ReadCleanReq 76436 # Transaction distribution
504 system.cpu.toL2Bus.trans_dist::ReadSharedReq 60766 # Transaction distribution
505 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 227263 # Packet count per connected master and slave (bytes)
506 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 608936 # Packet count per connected master and slave (bytes)
507 system.cpu.toL2Bus.pkt_count::total 836199 # Packet count per connected master and slave (bytes)
508 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9652928 # Cumulative packet size per connected master and slave (bytes)
509 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23847808 # Cumulative packet size per connected master and slave (bytes)
510 system.cpu.toL2Bus.pkt_size::total 33500736 # Cumulative packet size per connected master and slave (bytes)
511 system.cpu.toL2Bus.snoops 131998 # Total snoops (count)
512 system.cpu.toL2Bus.snoop_fanout::samples 412778 # Request fanout histogram
513 system.cpu.toL2Bus.snoop_fanout::mean 0.009388 # Request fanout histogram
514 system.cpu.toL2Bus.snoop_fanout::stdev 0.096434 # Request fanout histogram
515 system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
516 system.cpu.toL2Bus.snoop_fanout::0 408903 99.06% 99.06% # Request fanout histogram
517 system.cpu.toL2Bus.snoop_fanout::1 3875 0.94% 100.00% # Request fanout histogram
518 system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
519 system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
520 system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
521 system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
522 system.cpu.toL2Bus.snoop_fanout::total 412778 # Request fanout histogram
523 system.cpu.toL2Bus.reqLayer0.occupancy 520378500 # Layer occupancy (ticks)
524 system.cpu.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%)
525 system.cpu.toL2Bus.respLayer0.occupancy 114654000 # Layer occupancy (ticks)
526 system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
527 system.cpu.toL2Bus.respLayer1.occupancy 306516000 # Layer occupancy (ticks)
528 system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
529 system.membus.trans_dist::ReadResp 33266 # Transaction distribution
530 system.membus.trans_dist::WritebackDirty 114382 # Transaction distribution
531 system.membus.trans_dist::CleanEvict 13845 # Transaction distribution
532 system.membus.trans_dist::ReadExReq 130882 # Transaction distribution
533 system.membus.trans_dist::ReadExResp 130882 # Transaction distribution
534 system.membus.trans_dist::ReadSharedReq 33266 # Transaction distribution
535 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 456523 # Packet count per connected master and slave (bytes)
536 system.membus.pkt_count::total 456523 # Packet count per connected master and slave (bytes)
537 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17825920 # Cumulative packet size per connected master and slave (bytes)
538 system.membus.pkt_size::total 17825920 # Cumulative packet size per connected master and slave (bytes)
539 system.membus.snoops 0 # Total snoops (count)
540 system.membus.snoop_fanout::samples 292375 # Request fanout histogram
541 system.membus.snoop_fanout::mean 0 # Request fanout histogram
542 system.membus.snoop_fanout::stdev 0 # Request fanout histogram
543 system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
544 system.membus.snoop_fanout::0 292375 100.00% 100.00% # Request fanout histogram
545 system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
546 system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
547 system.membus.snoop_fanout::min_value 0 # Request fanout histogram
548 system.membus.snoop_fanout::max_value 0 # Request fanout histogram
549 system.membus.snoop_fanout::total 292375 # Request fanout histogram
550 system.membus.reqLayer0.occupancy 750324500 # Layer occupancy (ticks)
551 system.membus.reqLayer0.utilization 0.6 # Layer utilization (%)
552 system.membus.respLayer1.occupancy 820740000 # Layer occupancy (ticks)
553 system.membus.respLayer1.utilization 0.6 # Layer utilization (%)
555 ---------- End Simulation Statistics ----------
projects / gem5.git / blob