tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 eventq_index=0
   5 full_system=false
   6 sim_quantum=0
   7 time_sync_enable=false
   8 time_sync_period=100000000000
   9 time_sync_spin_threshold=100000000
  10
  11 [system]
  12 type=System
  13 children=clk_domain cpu dvfs_handler membus monitor physmem
  14 boot_osflags=a
  15 cache_line_size=64
  16 clk_domain=system.clk_domain
  17 eventq_index=0
  18 exit_on_work_items=false
  19 init_param=0
  20 kernel=
  21 kernel_addr_check=true
  22 load_addr_mask=1099511627775
  23 load_offset=0
  24 mem_mode=timing
  25 mem_ranges=
  26 memories=system.physmem
  27 mmap_using_noreserve=false
  28 multi_thread=false
  29 num_work_ids=16
  30 readfile=
  31 symbolfile=
  32 work_begin_ckpt_count=0
  33 work_begin_cpu_id_exit=-1
  34 work_begin_exit_count=0
  35 work_cpus_ckpt_count=0
  36 work_end_ckpt_count=0
  37 work_end_exit_count=0
  38 work_item_id=-1
  39 system_port=system.membus.slave[1]
  40
  41 [system.clk_domain]
  42 type=SrcClockDomain
  43 children=voltage_domain
  44 clock=1000
  45 domain_id=-1
  46 eventq_index=0
  47 init_perf_level=0
  48 voltage_domain=system.clk_domain.voltage_domain
  49
  50 [system.clk_domain.voltage_domain]
  51 type=VoltageDomain
  52 eventq_index=0
  53 voltage=1.000000
  54
  55 [system.cpu]
  56 type=TrafficGen
  57 clk_domain=system.clk_domain
  58 config_file=tests/quick/se/70.tgen/tgen-dram-ctrl.cfg
  59 elastic_req=false
  60 eventq_index=0
  61 system=system
  62 port=system.monitor.slave
  63
  64 [system.dvfs_handler]
  65 type=DVFSHandler
  66 domains=
  67 enable=false
  68 eventq_index=0
  69 sys_clk_domain=system.clk_domain
  70 transition_latency=100000000
  71
  72 [system.membus]
  73 type=NoncoherentXBar
  74 clk_domain=system.clk_domain
  75 eventq_index=0
  76 forward_latency=1
  77 frontend_latency=2
  78 response_latency=2
  79 use_default_range=false
  80 width=16
  81 master=system.physmem.port
  82 slave=system.monitor.master system.system_port
  83
  84 [system.monitor]
  85 type=CommMonitor
  86 bandwidth_bins=20
  87 burst_length_bins=20
  88 clk_domain=system.clk_domain
  89 disable_addr_dists=true
  90 disable_bandwidth_hists=false
  91 disable_burst_length_hists=false
  92 disable_itt_dists=false
  93 disable_latency_hists=false
  94 disable_outstanding_hists=false
  95 disable_transaction_hists=false
  96 eventq_index=0
  97 itt_bins=20
  98 itt_max_bin=100000
  99 latency_bins=20
 100 outstanding_bins=20
 101 read_addr_mask=18446744073709551615
 102 sample_period=1000000000
 103 system=system
 104 transaction_bins=20
 105 write_addr_mask=18446744073709551615
 106 master=system.membus.slave[0]
 107 slave=system.cpu.port
 108
 109 [system.physmem]
 110 type=DRAMCtrl
 111 IDD0=0.075000
 112 IDD02=0.000000
 113 IDD2N=0.050000
 114 IDD2N2=0.000000
 115 IDD2P0=0.000000
 116 IDD2P02=0.000000
 117 IDD2P1=0.000000
 118 IDD2P12=0.000000
 119 IDD3N=0.057000
 120 IDD3N2=0.000000
 121 IDD3P0=0.000000
 122 IDD3P02=0.000000
 123 IDD3P1=0.000000
 124 IDD3P12=0.000000
 125 IDD4R=0.187000
 126 IDD4R2=0.000000
 127 IDD4W=0.165000
 128 IDD4W2=0.000000
 129 IDD5=0.220000
 130 IDD52=0.000000
 131 IDD6=0.000000
 132 IDD62=0.000000
 133 VDD=1.500000
 134 VDD2=0.000000
 135 activation_limit=4
 136 addr_mapping=RoRaBaCoCh
 137 bank_groups_per_rank=0
 138 banks_per_rank=8
 139 burst_length=8
 140 channels=1
 141 clk_domain=system.clk_domain
 142 conf_table_reported=true
 143 device_bus_width=8
 144 device_rowbuffer_size=1024
 145 device_size=536870912
 146 devices_per_rank=8
 147 dll=true
 148 eventq_index=0
 149 in_addr_map=true
 150 max_accesses_per_row=16
 151 mem_sched_policy=frfcfs
 152 min_writes_per_switch=16
 153 null=false
 154 page_policy=open_adaptive
 155 range=0:134217727
 156 ranks_per_channel=2
 157 read_buffer_size=32
 158 static_backend_latency=10000
 159 static_frontend_latency=10000
 160 tBURST=5000
 161 tCCD_L=0
 162 tCK=1250
 163 tCL=13750
 164 tCS=2500
 165 tRAS=35000
 166 tRCD=13750
 167 tREFI=7800000
 168 tRFC=260000
 169 tRP=13750
 170 tRRD=6000
 171 tRRD_L=0
 172 tRTP=7500
 173 tRTW=2500
 174 tWR=15000
 175 tWTR=7500
 176 tXAW=30000
 177 tXP=0
 178 tXPDLL=0
 179 tXS=0
 180 tXSDLL=0
 181 write_buffer_size=64
 182 write_high_thresh_perc=85
 183 write_low_thresh_perc=50
 184 port=system.membus.master[0]
 185