tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 full_system=false
   5 time_sync_enable=false
   6 time_sync_period=100000000000
   7 time_sync_spin_threshold=100000000
   8
   9 [system]
  10 type=System
  11 children=clk_domain cpu membus monitor physmem
  12 boot_osflags=a
  13 cache_line_size=64
  14 clk_domain=system.clk_domain
  15 init_param=0
  16 kernel=
  17 load_addr_mask=1099511627775
  18 mem_mode=timing
  19 mem_ranges=
  20 memories=system.physmem
  21 num_work_ids=16
  22 readfile=
  23 symbolfile=
  24 work_begin_ckpt_count=0
  25 work_begin_cpu_id_exit=-1
  26 work_begin_exit_count=0
  27 work_cpus_ckpt_count=0
  28 work_end_ckpt_count=0
  29 work_end_exit_count=0
  30 work_item_id=-1
  31 system_port=system.membus.slave[1]
  32
  33 [system.clk_domain]
  34 type=SrcClockDomain
  35 children=voltage_domain
  36 clock=1000
  37 voltage_domain=system.clk_domain.voltage_domain
  38
  39 [system.clk_domain.voltage_domain]
  40 type=VoltageDomain
  41 voltage=1.000000
  42
  43 [system.cpu]
  44 type=TrafficGen
  45 clk_domain=system.clk_domain
  46 config_file=tests/quick/se/70.tgen/tgen-simple-dram.cfg
  47 elastic_req=false
  48 system=system
  49 port=system.monitor.slave
  50
  51 [system.membus]
  52 type=NoncoherentBus
  53 clk_domain=system.clk_domain
  54 header_cycles=1
  55 use_default_range=false
  56 width=16
  57 master=system.physmem.port
  58 slave=system.monitor.master system.system_port
  59
  60 [system.monitor]
  61 type=CommMonitor
  62 bandwidth_bins=20
  63 burst_length_bins=20
  64 clk_domain=system.clk_domain
  65 disable_addr_dists=true
  66 disable_bandwidth_hists=false
  67 disable_burst_length_hists=false
  68 disable_itt_dists=false
  69 disable_latency_hists=false
  70 disable_outstanding_hists=false
  71 disable_transaction_hists=false
  72 itt_bins=20
  73 itt_max_bin=100000
  74 latency_bins=20
  75 outstanding_bins=20
  76 read_addr_mask=18446744073709551615
  77 sample_period=1000000000
  78 trace_file=
  79 transaction_bins=20
  80 write_addr_mask=18446744073709551615
  81 master=system.membus.slave[0]
  82 slave=system.cpu.port
  83
  84 [system.physmem]
  85 type=SimpleDRAM
  86 activation_limit=4
  87 addr_mapping=RaBaChCo
  88 banks_per_rank=8
  89 burst_length=8
  90 channels=1
  91 clk_domain=system.clk_domain
  92 conf_table_reported=true
  93 device_bus_width=8
  94 device_rowbuffer_size=1024
  95 devices_per_rank=8
  96 in_addr_map=true
  97 mem_sched_policy=frfcfs
  98 null=false
  99 page_policy=open
 100 range=0:134217727
 101 ranks_per_channel=2
 102 read_buffer_size=32
 103 static_backend_latency=10000
 104 static_frontend_latency=10000
 105 tBURST=5000
 106 tCL=13750
 107 tRCD=13750
 108 tREFI=7800000
 109 tRFC=300000
 110 tRP=13750
 111 tWTR=7500
 112 tXAW=40000
 113 write_buffer_size=32
 114 write_thresh_perc=70
 115 port=system.membus.master[0]
 116