tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 eventq_index=0
   5 full_system=false
   6 sim_quantum=0
   7 time_sync_enable=false
   8 time_sync_period=100000000000
   9 time_sync_spin_threshold=100000000
  10
  11 [system]
  12 type=System
  13 children=clk_domain cpu membus monitor physmem
  14 boot_osflags=a
  15 cache_line_size=64
  16 clk_domain=system.clk_domain
  17 eventq_index=0
  18 init_param=0
  19 kernel=
  20 load_addr_mask=1099511627775
  21 mem_mode=timing
  22 mem_ranges=
  23 memories=system.physmem
  24 num_work_ids=16
  25 readfile=
  26 symbolfile=
  27 work_begin_ckpt_count=0
  28 work_begin_cpu_id_exit=-1
  29 work_begin_exit_count=0
  30 work_cpus_ckpt_count=0
  31 work_end_ckpt_count=0
  32 work_end_exit_count=0
  33 work_item_id=-1
  34 system_port=system.membus.slave[1]
  35
  36 [system.clk_domain]
  37 type=SrcClockDomain
  38 children=voltage_domain
  39 clock=1000
  40 eventq_index=0
  41 voltage_domain=system.clk_domain.voltage_domain
  42
  43 [system.clk_domain.voltage_domain]
  44 type=VoltageDomain
  45 eventq_index=0
  46 voltage=1.000000
  47
  48 [system.cpu]
  49 type=TrafficGen
  50 clk_domain=system.clk_domain
  51 config_file=tests/quick/se/70.tgen/tgen-simple-dram.cfg
  52 elastic_req=false
  53 eventq_index=0
  54 system=system
  55 port=system.monitor.slave
  56
  57 [system.membus]
  58 type=NoncoherentBus
  59 clk_domain=system.clk_domain
  60 eventq_index=0
  61 header_cycles=1
  62 use_default_range=false
  63 width=16
  64 master=system.physmem.port
  65 slave=system.monitor.master system.system_port
  66
  67 [system.monitor]
  68 type=CommMonitor
  69 bandwidth_bins=20
  70 burst_length_bins=20
  71 clk_domain=system.clk_domain
  72 disable_addr_dists=true
  73 disable_bandwidth_hists=false
  74 disable_burst_length_hists=false
  75 disable_itt_dists=false
  76 disable_latency_hists=false
  77 disable_outstanding_hists=false
  78 disable_transaction_hists=false
  79 eventq_index=0
  80 itt_bins=20
  81 itt_max_bin=100000
  82 latency_bins=20
  83 outstanding_bins=20
  84 read_addr_mask=18446744073709551615
  85 sample_period=1000000000
  86 trace_file=
  87 transaction_bins=20
  88 write_addr_mask=18446744073709551615
  89 master=system.membus.slave[0]
  90 slave=system.cpu.port
  91
  92 [system.physmem]
  93 type=SimpleDRAM
  94 activation_limit=4
  95 addr_mapping=RaBaChCo
  96 banks_per_rank=8
  97 burst_length=8
  98 channels=1
  99 clk_domain=system.clk_domain
 100 conf_table_reported=true
 101 device_bus_width=8
 102 device_rowbuffer_size=1024
 103 devices_per_rank=8
 104 eventq_index=0
 105 in_addr_map=true
 106 mem_sched_policy=frfcfs
 107 null=false
 108 page_policy=open
 109 range=0:134217727
 110 ranks_per_channel=2
 111 read_buffer_size=32
 112 static_backend_latency=10000
 113 static_frontend_latency=10000
 114 tBURST=5000
 115 tCL=13750
 116 tRAS=35000
 117 tRCD=13750
 118 tREFI=7800000
 119 tRFC=300000
 120 tRP=13750
 121 tRRD=6250
 122 tWTR=7500
 123 tXAW=40000
 124 write_buffer_size=32
 125 write_high_thresh_perc=70
 126 write_low_thresh_perc=0
 127 port=system.membus.master[0]
 128