tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/simout

   1 Redirecting stdout to build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-mem/simout
   2 Redirecting stderr to build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-mem/simerr
   3 gem5 Simulator System.  http://gem5.org
   4 gem5 is copyrighted software; use the --copyright option for details.
   5
   6 gem5 compiled Sep 22 2013 05:53:51
   7 gem5 started Sep 22 2013 05:53:54
   8 gem5 executing on zizzer
   9 command line: build/NULL/gem5.opt -d build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-mem -re tests/run.py build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-mem
  10 Global frequency set at 1000000000000 ticks per second
  11 info: Entering event queue @ 0.  Starting simulation...
  12 Exiting @ tick 100000000000 because simulate() limit reached