stats: update stats to after GPU checkin
[gem5.git] / tests / quick / se / 70.twolf / ref / alpha / tru64 / simple-timing / config.ini
1 [root]
2 type=Root
3 children=system
4 eventq_index=0
5 full_system=false
6 sim_quantum=0
7 time_sync_enable=false
8 time_sync_period=100000000000
9 time_sync_spin_threshold=100000000
10
11 [system]
12 type=System
13 children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
14 boot_osflags=a
15 cache_line_size=64
16 clk_domain=system.clk_domain
17 eventq_index=0
18 exit_on_work_items=false
19 init_param=0
20 kernel=
21 kernel_addr_check=true
22 load_addr_mask=1099511627775
23 load_offset=0
24 mem_mode=timing
25 mem_ranges=
26 memories=system.physmem
27 mmap_using_noreserve=false
28 multi_thread=false
29 num_work_ids=16
30 readfile=
31 symbolfile=
32 work_begin_ckpt_count=0
33 work_begin_cpu_id_exit=-1
34 work_begin_exit_count=0
35 work_cpus_ckpt_count=0
36 work_end_ckpt_count=0
37 work_end_exit_count=0
38 work_item_id=-1
39 system_port=system.membus.slave[0]
40
41 [system.clk_domain]
42 type=SrcClockDomain
43 clock=1000
44 domain_id=-1
45 eventq_index=0
46 init_perf_level=0
47 voltage_domain=system.voltage_domain
48
49 [system.cpu]
50 type=TimingSimpleCPU
51 children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
52 branchPred=Null
53 checker=Null
54 clk_domain=system.cpu_clk_domain
55 cpu_id=0
56 do_checkpoint_insts=true
57 do_quiesce=true
58 do_statistics_insts=true
59 dtb=system.cpu.dtb
60 eventq_index=0
61 function_trace=false
62 function_trace_start=0
63 interrupts=system.cpu.interrupts
64 isa=system.cpu.isa
65 itb=system.cpu.itb
66 max_insts_all_threads=0
67 max_insts_any_thread=0
68 max_loads_all_threads=0
69 max_loads_any_thread=0
70 numThreads=1
71 profile=0
72 progress_interval=0
73 simpoint_start_insts=
74 socket_id=0
75 switched_out=false
76 system=system
77 tracer=system.cpu.tracer
78 workload=system.cpu.workload
79 dcache_port=system.cpu.dcache.cpu_side
80 icache_port=system.cpu.icache.cpu_side
81
82 [system.cpu.dcache]
83 type=Cache
84 children=tags
85 addr_ranges=0:18446744073709551615
86 assoc=2
87 clk_domain=system.cpu_clk_domain
88 clusivity=mostly_incl
89 demand_mshr_reserve=1
90 eventq_index=0
91 forward_snoops=true
92 hit_latency=2
93 is_read_only=false
94 max_miss_count=0
95 mshrs=4
96 prefetch_on_access=false
97 prefetcher=Null
98 response_latency=2
99 sequential_access=false
100 size=262144
101 system=system
102 tags=system.cpu.dcache.tags
103 tgts_per_mshr=20
104 write_buffers=8
105 writeback_clean=false
106 cpu_side=system.cpu.dcache_port
107 mem_side=system.cpu.toL2Bus.slave[1]
108
109 [system.cpu.dcache.tags]
110 type=LRU
111 assoc=2
112 block_size=64
113 clk_domain=system.cpu_clk_domain
114 eventq_index=0
115 hit_latency=2
116 sequential_access=false
117 size=262144
118
119 [system.cpu.dtb]
120 type=AlphaTLB
121 eventq_index=0
122 size=64
123
124 [system.cpu.icache]
125 type=Cache
126 children=tags
127 addr_ranges=0:18446744073709551615
128 assoc=2
129 clk_domain=system.cpu_clk_domain
130 clusivity=mostly_incl
131 demand_mshr_reserve=1
132 eventq_index=0
133 forward_snoops=true
134 hit_latency=2
135 is_read_only=true
136 max_miss_count=0
137 mshrs=4
138 prefetch_on_access=false
139 prefetcher=Null
140 response_latency=2
141 sequential_access=false
142 size=131072
143 system=system
144 tags=system.cpu.icache.tags
145 tgts_per_mshr=20
146 write_buffers=8
147 writeback_clean=true
148 cpu_side=system.cpu.icache_port
149 mem_side=system.cpu.toL2Bus.slave[0]
150
151 [system.cpu.icache.tags]
152 type=LRU
153 assoc=2
154 block_size=64
155 clk_domain=system.cpu_clk_domain
156 eventq_index=0
157 hit_latency=2
158 sequential_access=false
159 size=131072
160
161 [system.cpu.interrupts]
162 type=AlphaInterrupts
163 eventq_index=0
164
165 [system.cpu.isa]
166 type=AlphaISA
167 eventq_index=0
168 system=system
169
170 [system.cpu.itb]
171 type=AlphaTLB
172 eventq_index=0
173 size=48
174
175 [system.cpu.l2cache]
176 type=Cache
177 children=tags
178 addr_ranges=0:18446744073709551615
179 assoc=8
180 clk_domain=system.cpu_clk_domain
181 clusivity=mostly_incl
182 demand_mshr_reserve=1
183 eventq_index=0
184 forward_snoops=true
185 hit_latency=20
186 is_read_only=false
187 max_miss_count=0
188 mshrs=20
189 prefetch_on_access=false
190 prefetcher=Null
191 response_latency=20
192 sequential_access=false
193 size=2097152
194 system=system
195 tags=system.cpu.l2cache.tags
196 tgts_per_mshr=12
197 write_buffers=8
198 writeback_clean=false
199 cpu_side=system.cpu.toL2Bus.master[0]
200 mem_side=system.membus.slave[1]
201
202 [system.cpu.l2cache.tags]
203 type=LRU
204 assoc=8
205 block_size=64
206 clk_domain=system.cpu_clk_domain
207 eventq_index=0
208 hit_latency=20
209 sequential_access=false
210 size=2097152
211
212 [system.cpu.toL2Bus]
213 type=CoherentXBar
214 children=snoop_filter
215 clk_domain=system.cpu_clk_domain
216 eventq_index=0
217 forward_latency=0
218 frontend_latency=1
219 response_latency=1
220 snoop_filter=system.cpu.toL2Bus.snoop_filter
221 snoop_response_latency=1
222 system=system
223 use_default_range=false
224 width=32
225 master=system.cpu.l2cache.cpu_side
226 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
227
228 [system.cpu.toL2Bus.snoop_filter]
229 type=SnoopFilter
230 eventq_index=0
231 lookup_latency=0
232 max_capacity=8388608
233 system=system
234
235 [system.cpu.tracer]
236 type=ExeTracer
237 eventq_index=0
238
239 [system.cpu.workload]
240 type=LiveProcess
241 cmd=twolf smred
242 cwd=build/ALPHA/tests/opt/quick/se/70.twolf/alpha/tru64/simple-timing
243 drivers=
244 egid=100
245 env=
246 errout=cerr
247 euid=100
248 eventq_index=0
249 executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf
250 gid=100
251 input=cin
252 kvmInSE=false
253 max_stack_size=67108864
254 output=cout
255 pid=100
256 ppid=99
257 simpoint=0
258 system=system
259 uid=100
260 useArchPT=false
261
262 [system.cpu_clk_domain]
263 type=SrcClockDomain
264 clock=500
265 domain_id=-1
266 eventq_index=0
267 init_perf_level=0
268 voltage_domain=system.voltage_domain
269
270 [system.dvfs_handler]
271 type=DVFSHandler
272 domains=
273 enable=false
274 eventq_index=0
275 sys_clk_domain=system.clk_domain
276 transition_latency=100000000
277
278 [system.membus]
279 type=CoherentXBar
280 clk_domain=system.clk_domain
281 eventq_index=0
282 forward_latency=4
283 frontend_latency=3
284 response_latency=2
285 snoop_filter=Null
286 snoop_response_latency=4
287 system=system
288 use_default_range=false
289 width=16
290 master=system.physmem.port
291 slave=system.system_port system.cpu.l2cache.mem_side
292
293 [system.physmem]
294 type=SimpleMemory
295 bandwidth=73.000000
296 clk_domain=system.clk_domain
297 conf_table_reported=true
298 eventq_index=0
299 in_addr_map=true
300 latency=30000
301 latency_var=0
302 null=false
303 range=0:134217727
304 port=system.membus.master[0]
305
306 [system.voltage_domain]
307 type=VoltageDomain
308 eventq_index=0
309 voltage=1.000000
310