2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.118763 # Number of seconds simulated
4 sim_ticks 118762761500 # Number of ticks simulated
5 final_tick 118762761500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 962338 # Simulator instruction rate (inst/s)
8 host_op_rate 962338 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 1243592305 # Simulator tick rate (ticks/s)
10 host_mem_usage 296636 # Number of bytes of host memory used
11 host_seconds 95.50 # Real time elapsed on the host
12 sim_insts 91903056 # Number of instructions simulated
13 sim_ops 91903056 # Number of ops (including micro ops) simulated
14 system.voltage_domain.voltage 1 # Voltage in Volts
15 system.clk_domain.clock 1000 # Clock period in ticks
16 system.physmem.bytes_read::cpu.inst 167744 # Number of bytes read from this memory
17 system.physmem.bytes_read::cpu.data 137216 # Number of bytes read from this memory
18 system.physmem.bytes_read::total 304960 # Number of bytes read from this memory
19 system.physmem.bytes_inst_read::cpu.inst 167744 # Number of instructions bytes read from this memory
20 system.physmem.bytes_inst_read::total 167744 # Number of instructions bytes read from this memory
21 system.physmem.num_reads::cpu.inst 2621 # Number of read requests responded to by this memory
22 system.physmem.num_reads::cpu.data 2144 # Number of read requests responded to by this memory
23 system.physmem.num_reads::total 4765 # Number of read requests responded to by this memory
24 system.physmem.bw_read::cpu.inst 1412429 # Total read bandwidth from this memory (bytes/s)
25 system.physmem.bw_read::cpu.data 1155379 # Total read bandwidth from this memory (bytes/s)
26 system.physmem.bw_read::total 2567808 # Total read bandwidth from this memory (bytes/s)
27 system.physmem.bw_inst_read::cpu.inst 1412429 # Instruction read bandwidth from this memory (bytes/s)
28 system.physmem.bw_inst_read::total 1412429 # Instruction read bandwidth from this memory (bytes/s)
29 system.physmem.bw_total::cpu.inst 1412429 # Total bandwidth to/from this memory (bytes/s)
30 system.physmem.bw_total::cpu.data 1155379 # Total bandwidth to/from this memory (bytes/s)
31 system.physmem.bw_total::total 2567808 # Total bandwidth to/from this memory (bytes/s)
32 system.cpu_clk_domain.clock 500 # Clock period in ticks
33 system.cpu.dtb.fetch_hits 0 # ITB hits
34 system.cpu.dtb.fetch_misses 0 # ITB misses
35 system.cpu.dtb.fetch_acv 0 # ITB acv
36 system.cpu.dtb.fetch_accesses 0 # ITB accesses
37 system.cpu.dtb.read_hits 19996198 # DTB read hits
38 system.cpu.dtb.read_misses 10 # DTB read misses
39 system.cpu.dtb.read_acv 0 # DTB read access violations
40 system.cpu.dtb.read_accesses 19996208 # DTB read accesses
41 system.cpu.dtb.write_hits 6501103 # DTB write hits
42 system.cpu.dtb.write_misses 23 # DTB write misses
43 system.cpu.dtb.write_acv 0 # DTB write access violations
44 system.cpu.dtb.write_accesses 6501126 # DTB write accesses
45 system.cpu.dtb.data_hits 26497301 # DTB hits
46 system.cpu.dtb.data_misses 33 # DTB misses
47 system.cpu.dtb.data_acv 0 # DTB access violations
48 system.cpu.dtb.data_accesses 26497334 # DTB accesses
49 system.cpu.itb.fetch_hits 91903090 # ITB hits
50 system.cpu.itb.fetch_misses 47 # ITB misses
51 system.cpu.itb.fetch_acv 0 # ITB acv
52 system.cpu.itb.fetch_accesses 91903137 # ITB accesses
53 system.cpu.itb.read_hits 0 # DTB read hits
54 system.cpu.itb.read_misses 0 # DTB read misses
55 system.cpu.itb.read_acv 0 # DTB read access violations
56 system.cpu.itb.read_accesses 0 # DTB read accesses
57 system.cpu.itb.write_hits 0 # DTB write hits
58 system.cpu.itb.write_misses 0 # DTB write misses
59 system.cpu.itb.write_acv 0 # DTB write access violations
60 system.cpu.itb.write_accesses 0 # DTB write accesses
61 system.cpu.itb.data_hits 0 # DTB hits
62 system.cpu.itb.data_misses 0 # DTB misses
63 system.cpu.itb.data_acv 0 # DTB access violations
64 system.cpu.itb.data_accesses 0 # DTB accesses
65 system.cpu.workload.num_syscalls 389 # Number of system calls
66 system.cpu.numCycles 237525523 # number of cpu cycles simulated
67 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
68 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
69 system.cpu.committedInsts 91903056 # Number of instructions committed
70 system.cpu.committedOps 91903056 # Number of ops (including micro ops) committed
71 system.cpu.num_int_alu_accesses 79581109 # Number of integer alu accesses
72 system.cpu.num_fp_alu_accesses 6862064 # Number of float alu accesses
73 system.cpu.num_func_calls 2059216 # number of times a function call or return occured
74 system.cpu.num_conditional_control_insts 7465012 # number of instructions that are conditional controls
75 system.cpu.num_int_insts 79581109 # number of integer instructions
76 system.cpu.num_fp_insts 6862064 # number of float instructions
77 system.cpu.num_int_register_reads 115028592 # number of times the integer registers were read
78 system.cpu.num_int_register_writes 62575473 # number of times the integer registers were written
79 system.cpu.num_fp_register_reads 6071661 # number of times the floating registers were read
80 system.cpu.num_fp_register_writes 5851888 # number of times the floating registers were written
81 system.cpu.num_mem_refs 26497334 # number of memory refs
82 system.cpu.num_load_insts 19996208 # Number of load instructions
83 system.cpu.num_store_insts 6501126 # Number of store instructions
84 system.cpu.num_idle_cycles 0 # Number of idle cycles
85 system.cpu.num_busy_cycles 237525523 # Number of busy cycles
86 system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
87 system.cpu.idle_fraction 0 # Percentage of idle cycles
88 system.cpu.Branches 10240685 # Number of branches fetched
89 system.cpu.op_class::No_OpClass 7723353 8.40% 8.40% # Class of executed instruction
90 system.cpu.op_class::IntAlu 51001454 55.49% 63.90% # Class of executed instruction
91 system.cpu.op_class::IntMult 458252 0.50% 64.40% # Class of executed instruction
92 system.cpu.op_class::IntDiv 0 0.00% 64.40% # Class of executed instruction
93 system.cpu.op_class::FloatAdd 2732553 2.97% 67.37% # Class of executed instruction
94 system.cpu.op_class::FloatCmp 104605 0.11% 67.48% # Class of executed instruction
95 system.cpu.op_class::FloatCvt 2333953 2.54% 70.02% # Class of executed instruction
96 system.cpu.op_class::FloatMult 296445 0.32% 70.35% # Class of executed instruction
97 system.cpu.op_class::FloatDiv 754822 0.82% 71.17% # Class of executed instruction
98 system.cpu.op_class::FloatSqrt 318 0.00% 71.17% # Class of executed instruction
99 system.cpu.op_class::SimdAdd 0 0.00% 71.17% # Class of executed instruction
100 system.cpu.op_class::SimdAddAcc 0 0.00% 71.17% # Class of executed instruction
101 system.cpu.op_class::SimdAlu 0 0.00% 71.17% # Class of executed instruction
102 system.cpu.op_class::SimdCmp 0 0.00% 71.17% # Class of executed instruction
103 system.cpu.op_class::SimdCvt 0 0.00% 71.17% # Class of executed instruction
104 system.cpu.op_class::SimdMisc 0 0.00% 71.17% # Class of executed instruction
105 system.cpu.op_class::SimdMult 0 0.00% 71.17% # Class of executed instruction
106 system.cpu.op_class::SimdMultAcc 0 0.00% 71.17% # Class of executed instruction
107 system.cpu.op_class::SimdShift 0 0.00% 71.17% # Class of executed instruction
108 system.cpu.op_class::SimdShiftAcc 0 0.00% 71.17% # Class of executed instruction
109 system.cpu.op_class::SimdSqrt 0 0.00% 71.17% # Class of executed instruction
110 system.cpu.op_class::SimdFloatAdd 0 0.00% 71.17% # Class of executed instruction
111 system.cpu.op_class::SimdFloatAlu 0 0.00% 71.17% # Class of executed instruction
112 system.cpu.op_class::SimdFloatCmp 0 0.00% 71.17% # Class of executed instruction
113 system.cpu.op_class::SimdFloatCvt 0 0.00% 71.17% # Class of executed instruction
114 system.cpu.op_class::SimdFloatDiv 0 0.00% 71.17% # Class of executed instruction
115 system.cpu.op_class::SimdFloatMisc 0 0.00% 71.17% # Class of executed instruction
116 system.cpu.op_class::SimdFloatMult 0 0.00% 71.17% # Class of executed instruction
117 system.cpu.op_class::SimdFloatMultAcc 0 0.00% 71.17% # Class of executed instruction
118 system.cpu.op_class::SimdFloatSqrt 0 0.00% 71.17% # Class of executed instruction
119 system.cpu.op_class::MemRead 19996208 21.76% 92.93% # Class of executed instruction
120 system.cpu.op_class::MemWrite 6501126 7.07% 100.00% # Class of executed instruction
121 system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
122 system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
123 system.cpu.op_class::total 91903089 # Class of executed instruction
124 system.cpu.dcache.tags.replacements 157 # number of replacements
125 system.cpu.dcache.tags.tagsinuse 1441.946319 # Cycle average of tags in use
126 system.cpu.dcache.tags.total_refs 26495078 # Total number of references to valid blocks.
127 system.cpu.dcache.tags.sampled_refs 2223 # Sample count of references to valid blocks.
128 system.cpu.dcache.tags.avg_refs 11918.613585 # Average number of references to valid blocks.
129 system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
130 system.cpu.dcache.tags.occ_blocks::cpu.data 1441.946319 # Average occupied blocks per requestor
131 system.cpu.dcache.tags.occ_percent::cpu.data 0.352038 # Average percentage of cache occupancy
132 system.cpu.dcache.tags.occ_percent::total 0.352038 # Average percentage of cache occupancy
133 system.cpu.dcache.tags.occ_task_id_blocks::1024 2066 # Occupied blocks per task id
134 system.cpu.dcache.tags.age_task_id_blocks_1024::0 17 # Occupied blocks per task id
135 system.cpu.dcache.tags.age_task_id_blocks_1024::1 17 # Occupied blocks per task id
136 system.cpu.dcache.tags.age_task_id_blocks_1024::2 169 # Occupied blocks per task id
137 system.cpu.dcache.tags.age_task_id_blocks_1024::3 491 # Occupied blocks per task id
138 system.cpu.dcache.tags.age_task_id_blocks_1024::4 1372 # Occupied blocks per task id
139 system.cpu.dcache.tags.occ_task_id_percent::1024 0.504395 # Percentage of cache occupancy per task id
140 system.cpu.dcache.tags.tag_accesses 52996825 # Number of tag accesses
141 system.cpu.dcache.tags.data_accesses 52996825 # Number of data accesses
142 system.cpu.dcache.ReadReq_hits::cpu.data 19995723 # number of ReadReq hits
143 system.cpu.dcache.ReadReq_hits::total 19995723 # number of ReadReq hits
144 system.cpu.dcache.WriteReq_hits::cpu.data 6499355 # number of WriteReq hits
145 system.cpu.dcache.WriteReq_hits::total 6499355 # number of WriteReq hits
146 system.cpu.dcache.demand_hits::cpu.data 26495078 # number of demand (read+write) hits
147 system.cpu.dcache.demand_hits::total 26495078 # number of demand (read+write) hits
148 system.cpu.dcache.overall_hits::cpu.data 26495078 # number of overall hits
149 system.cpu.dcache.overall_hits::total 26495078 # number of overall hits
150 system.cpu.dcache.ReadReq_misses::cpu.data 475 # number of ReadReq misses
151 system.cpu.dcache.ReadReq_misses::total 475 # number of ReadReq misses
152 system.cpu.dcache.WriteReq_misses::cpu.data 1748 # number of WriteReq misses
153 system.cpu.dcache.WriteReq_misses::total 1748 # number of WriteReq misses
154 system.cpu.dcache.demand_misses::cpu.data 2223 # number of demand (read+write) misses
155 system.cpu.dcache.demand_misses::total 2223 # number of demand (read+write) misses
156 system.cpu.dcache.overall_misses::cpu.data 2223 # number of overall misses
157 system.cpu.dcache.overall_misses::total 2223 # number of overall misses
158 system.cpu.dcache.ReadReq_miss_latency::cpu.data 26856500 # number of ReadReq miss cycles
159 system.cpu.dcache.ReadReq_miss_latency::total 26856500 # number of ReadReq miss cycles
160 system.cpu.dcache.WriteReq_miss_latency::cpu.data 107103000 # number of WriteReq miss cycles
161 system.cpu.dcache.WriteReq_miss_latency::total 107103000 # number of WriteReq miss cycles
162 system.cpu.dcache.demand_miss_latency::cpu.data 133959500 # number of demand (read+write) miss cycles
163 system.cpu.dcache.demand_miss_latency::total 133959500 # number of demand (read+write) miss cycles
164 system.cpu.dcache.overall_miss_latency::cpu.data 133959500 # number of overall miss cycles
165 system.cpu.dcache.overall_miss_latency::total 133959500 # number of overall miss cycles
166 system.cpu.dcache.ReadReq_accesses::cpu.data 19996198 # number of ReadReq accesses(hits+misses)
167 system.cpu.dcache.ReadReq_accesses::total 19996198 # number of ReadReq accesses(hits+misses)
168 system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses)
169 system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses)
170 system.cpu.dcache.demand_accesses::cpu.data 26497301 # number of demand (read+write) accesses
171 system.cpu.dcache.demand_accesses::total 26497301 # number of demand (read+write) accesses
172 system.cpu.dcache.overall_accesses::cpu.data 26497301 # number of overall (read+write) accesses
173 system.cpu.dcache.overall_accesses::total 26497301 # number of overall (read+write) accesses
174 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000024 # miss rate for ReadReq accesses
175 system.cpu.dcache.ReadReq_miss_rate::total 0.000024 # miss rate for ReadReq accesses
176 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000269 # miss rate for WriteReq accesses
177 system.cpu.dcache.WriteReq_miss_rate::total 0.000269 # miss rate for WriteReq accesses
178 system.cpu.dcache.demand_miss_rate::cpu.data 0.000084 # miss rate for demand accesses
179 system.cpu.dcache.demand_miss_rate::total 0.000084 # miss rate for demand accesses
180 system.cpu.dcache.overall_miss_rate::cpu.data 0.000084 # miss rate for overall accesses
181 system.cpu.dcache.overall_miss_rate::total 0.000084 # miss rate for overall accesses
182 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56540 # average ReadReq miss latency
183 system.cpu.dcache.ReadReq_avg_miss_latency::total 56540 # average ReadReq miss latency
184 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61271.739130 # average WriteReq miss latency
185 system.cpu.dcache.WriteReq_avg_miss_latency::total 61271.739130 # average WriteReq miss latency
186 system.cpu.dcache.demand_avg_miss_latency::cpu.data 60260.683761 # average overall miss latency
187 system.cpu.dcache.demand_avg_miss_latency::total 60260.683761 # average overall miss latency
188 system.cpu.dcache.overall_avg_miss_latency::cpu.data 60260.683761 # average overall miss latency
189 system.cpu.dcache.overall_avg_miss_latency::total 60260.683761 # average overall miss latency
190 system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
191 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
192 system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
193 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
194 system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
195 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
196 system.cpu.dcache.fast_writes 0 # number of fast writes performed
197 system.cpu.dcache.cache_copies 0 # number of cache copies performed
198 system.cpu.dcache.writebacks::writebacks 107 # number of writebacks
199 system.cpu.dcache.writebacks::total 107 # number of writebacks
200 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 475 # number of ReadReq MSHR misses
201 system.cpu.dcache.ReadReq_mshr_misses::total 475 # number of ReadReq MSHR misses
202 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1748 # number of WriteReq MSHR misses
203 system.cpu.dcache.WriteReq_mshr_misses::total 1748 # number of WriteReq MSHR misses
204 system.cpu.dcache.demand_mshr_misses::cpu.data 2223 # number of demand (read+write) MSHR misses
205 system.cpu.dcache.demand_mshr_misses::total 2223 # number of demand (read+write) MSHR misses
206 system.cpu.dcache.overall_mshr_misses::cpu.data 2223 # number of overall MSHR misses
207 system.cpu.dcache.overall_mshr_misses::total 2223 # number of overall MSHR misses
208 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26381500 # number of ReadReq MSHR miss cycles
209 system.cpu.dcache.ReadReq_mshr_miss_latency::total 26381500 # number of ReadReq MSHR miss cycles
210 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 105355000 # number of WriteReq MSHR miss cycles
211 system.cpu.dcache.WriteReq_mshr_miss_latency::total 105355000 # number of WriteReq MSHR miss cycles
212 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 131736500 # number of demand (read+write) MSHR miss cycles
213 system.cpu.dcache.demand_mshr_miss_latency::total 131736500 # number of demand (read+write) MSHR miss cycles
214 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 131736500 # number of overall MSHR miss cycles
215 system.cpu.dcache.overall_mshr_miss_latency::total 131736500 # number of overall MSHR miss cycles
216 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses
217 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses
218 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000269 # mshr miss rate for WriteReq accesses
219 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000269 # mshr miss rate for WriteReq accesses
220 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for demand accesses
221 system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses
222 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses
223 system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses
224 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 55540 # average ReadReq mshr miss latency
225 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 55540 # average ReadReq mshr miss latency
226 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60271.739130 # average WriteReq mshr miss latency
227 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60271.739130 # average WriteReq mshr miss latency
228 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 59260.683761 # average overall mshr miss latency
229 system.cpu.dcache.demand_avg_mshr_miss_latency::total 59260.683761 # average overall mshr miss latency
230 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 59260.683761 # average overall mshr miss latency
231 system.cpu.dcache.overall_avg_mshr_miss_latency::total 59260.683761 # average overall mshr miss latency
232 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
233 system.cpu.icache.tags.replacements 6681 # number of replacements
234 system.cpu.icache.tags.tagsinuse 1417.953327 # Cycle average of tags in use
235 system.cpu.icache.tags.total_refs 91894580 # Total number of references to valid blocks.
236 system.cpu.icache.tags.sampled_refs 8510 # Sample count of references to valid blocks.
237 system.cpu.icache.tags.avg_refs 10798.423032 # Average number of references to valid blocks.
238 system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
239 system.cpu.icache.tags.occ_blocks::cpu.inst 1417.953327 # Average occupied blocks per requestor
240 system.cpu.icache.tags.occ_percent::cpu.inst 0.692360 # Average percentage of cache occupancy
241 system.cpu.icache.tags.occ_percent::total 0.692360 # Average percentage of cache occupancy
242 system.cpu.icache.tags.occ_task_id_blocks::1024 1829 # Occupied blocks per task id
243 system.cpu.icache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id
244 system.cpu.icache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id
245 system.cpu.icache.tags.age_task_id_blocks_1024::2 223 # Occupied blocks per task id
246 system.cpu.icache.tags.age_task_id_blocks_1024::3 585 # Occupied blocks per task id
247 system.cpu.icache.tags.age_task_id_blocks_1024::4 953 # Occupied blocks per task id
248 system.cpu.icache.tags.occ_task_id_percent::1024 0.893066 # Percentage of cache occupancy per task id
249 system.cpu.icache.tags.tag_accesses 183814690 # Number of tag accesses
250 system.cpu.icache.tags.data_accesses 183814690 # Number of data accesses
251 system.cpu.icache.ReadReq_hits::cpu.inst 91894580 # number of ReadReq hits
252 system.cpu.icache.ReadReq_hits::total 91894580 # number of ReadReq hits
253 system.cpu.icache.demand_hits::cpu.inst 91894580 # number of demand (read+write) hits
254 system.cpu.icache.demand_hits::total 91894580 # number of demand (read+write) hits
255 system.cpu.icache.overall_hits::cpu.inst 91894580 # number of overall hits
256 system.cpu.icache.overall_hits::total 91894580 # number of overall hits
257 system.cpu.icache.ReadReq_misses::cpu.inst 8510 # number of ReadReq misses
258 system.cpu.icache.ReadReq_misses::total 8510 # number of ReadReq misses
259 system.cpu.icache.demand_misses::cpu.inst 8510 # number of demand (read+write) misses
260 system.cpu.icache.demand_misses::total 8510 # number of demand (read+write) misses
261 system.cpu.icache.overall_misses::cpu.inst 8510 # number of overall misses
262 system.cpu.icache.overall_misses::total 8510 # number of overall misses
263 system.cpu.icache.ReadReq_miss_latency::cpu.inst 239145000 # number of ReadReq miss cycles
264 system.cpu.icache.ReadReq_miss_latency::total 239145000 # number of ReadReq miss cycles
265 system.cpu.icache.demand_miss_latency::cpu.inst 239145000 # number of demand (read+write) miss cycles
266 system.cpu.icache.demand_miss_latency::total 239145000 # number of demand (read+write) miss cycles
267 system.cpu.icache.overall_miss_latency::cpu.inst 239145000 # number of overall miss cycles
268 system.cpu.icache.overall_miss_latency::total 239145000 # number of overall miss cycles
269 system.cpu.icache.ReadReq_accesses::cpu.inst 91903090 # number of ReadReq accesses(hits+misses)
270 system.cpu.icache.ReadReq_accesses::total 91903090 # number of ReadReq accesses(hits+misses)
271 system.cpu.icache.demand_accesses::cpu.inst 91903090 # number of demand (read+write) accesses
272 system.cpu.icache.demand_accesses::total 91903090 # number of demand (read+write) accesses
273 system.cpu.icache.overall_accesses::cpu.inst 91903090 # number of overall (read+write) accesses
274 system.cpu.icache.overall_accesses::total 91903090 # number of overall (read+write) accesses
275 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000093 # miss rate for ReadReq accesses
276 system.cpu.icache.ReadReq_miss_rate::total 0.000093 # miss rate for ReadReq accesses
277 system.cpu.icache.demand_miss_rate::cpu.inst 0.000093 # miss rate for demand accesses
278 system.cpu.icache.demand_miss_rate::total 0.000093 # miss rate for demand accesses
279 system.cpu.icache.overall_miss_rate::cpu.inst 0.000093 # miss rate for overall accesses
280 system.cpu.icache.overall_miss_rate::total 0.000093 # miss rate for overall accesses
281 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28101.645123 # average ReadReq miss latency
282 system.cpu.icache.ReadReq_avg_miss_latency::total 28101.645123 # average ReadReq miss latency
283 system.cpu.icache.demand_avg_miss_latency::cpu.inst 28101.645123 # average overall miss latency
284 system.cpu.icache.demand_avg_miss_latency::total 28101.645123 # average overall miss latency
285 system.cpu.icache.overall_avg_miss_latency::cpu.inst 28101.645123 # average overall miss latency
286 system.cpu.icache.overall_avg_miss_latency::total 28101.645123 # average overall miss latency
287 system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
288 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
289 system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
290 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
291 system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
292 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
293 system.cpu.icache.fast_writes 0 # number of fast writes performed
294 system.cpu.icache.cache_copies 0 # number of cache copies performed
295 system.cpu.icache.writebacks::writebacks 6681 # number of writebacks
296 system.cpu.icache.writebacks::total 6681 # number of writebacks
297 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 8510 # number of ReadReq MSHR misses
298 system.cpu.icache.ReadReq_mshr_misses::total 8510 # number of ReadReq MSHR misses
299 system.cpu.icache.demand_mshr_misses::cpu.inst 8510 # number of demand (read+write) MSHR misses
300 system.cpu.icache.demand_mshr_misses::total 8510 # number of demand (read+write) MSHR misses
301 system.cpu.icache.overall_mshr_misses::cpu.inst 8510 # number of overall MSHR misses
302 system.cpu.icache.overall_mshr_misses::total 8510 # number of overall MSHR misses
303 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 230635000 # number of ReadReq MSHR miss cycles
304 system.cpu.icache.ReadReq_mshr_miss_latency::total 230635000 # number of ReadReq MSHR miss cycles
305 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 230635000 # number of demand (read+write) MSHR miss cycles
306 system.cpu.icache.demand_mshr_miss_latency::total 230635000 # number of demand (read+write) MSHR miss cycles
307 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 230635000 # number of overall MSHR miss cycles
308 system.cpu.icache.overall_mshr_miss_latency::total 230635000 # number of overall MSHR miss cycles
309 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000093 # mshr miss rate for ReadReq accesses
310 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000093 # mshr miss rate for ReadReq accesses
311 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000093 # mshr miss rate for demand accesses
312 system.cpu.icache.demand_mshr_miss_rate::total 0.000093 # mshr miss rate for demand accesses
313 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000093 # mshr miss rate for overall accesses
314 system.cpu.icache.overall_mshr_miss_rate::total 0.000093 # mshr miss rate for overall accesses
315 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 27101.645123 # average ReadReq mshr miss latency
316 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 27101.645123 # average ReadReq mshr miss latency
317 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 27101.645123 # average overall mshr miss latency
318 system.cpu.icache.demand_avg_mshr_miss_latency::total 27101.645123 # average overall mshr miss latency
319 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27101.645123 # average overall mshr miss latency
320 system.cpu.icache.overall_avg_mshr_miss_latency::total 27101.645123 # average overall mshr miss latency
321 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
322 system.cpu.l2cache.tags.replacements 0 # number of replacements
323 system.cpu.l2cache.tags.tagsinuse 2073.923151 # Cycle average of tags in use
324 system.cpu.l2cache.tags.total_refs 12687 # Total number of references to valid blocks.
325 system.cpu.l2cache.tags.sampled_refs 3109 # Sample count of references to valid blocks.
326 system.cpu.l2cache.tags.avg_refs 4.080733 # Average number of references to valid blocks.
327 system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
328 system.cpu.l2cache.tags.occ_blocks::writebacks 17.795341 # Average occupied blocks per requestor
329 system.cpu.l2cache.tags.occ_blocks::cpu.inst 1704.894227 # Average occupied blocks per requestor
330 system.cpu.l2cache.tags.occ_blocks::cpu.data 351.233582 # Average occupied blocks per requestor
331 system.cpu.l2cache.tags.occ_percent::writebacks 0.000543 # Average percentage of cache occupancy
332 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.052029 # Average percentage of cache occupancy
333 system.cpu.l2cache.tags.occ_percent::cpu.data 0.010719 # Average percentage of cache occupancy
334 system.cpu.l2cache.tags.occ_percent::total 0.063291 # Average percentage of cache occupancy
335 system.cpu.l2cache.tags.occ_task_id_blocks::1024 3109 # Occupied blocks per task id
336 system.cpu.l2cache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id
337 system.cpu.l2cache.tags.age_task_id_blocks_1024::1 32 # Occupied blocks per task id
338 system.cpu.l2cache.tags.age_task_id_blocks_1024::2 221 # Occupied blocks per task id
339 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 703 # Occupied blocks per task id
340 system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2096 # Occupied blocks per task id
341 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.094879 # Percentage of cache occupancy per task id
342 system.cpu.l2cache.tags.tag_accesses 145425 # Number of tag accesses
343 system.cpu.l2cache.tags.data_accesses 145425 # Number of data accesses
344 system.cpu.l2cache.WritebackDirty_hits::writebacks 107 # number of WritebackDirty hits
345 system.cpu.l2cache.WritebackDirty_hits::total 107 # number of WritebackDirty hits
346 system.cpu.l2cache.WritebackClean_hits::writebacks 6681 # number of WritebackClean hits
347 system.cpu.l2cache.WritebackClean_hits::total 6681 # number of WritebackClean hits
348 system.cpu.l2cache.ReadExReq_hits::cpu.data 26 # number of ReadExReq hits
349 system.cpu.l2cache.ReadExReq_hits::total 26 # number of ReadExReq hits
350 system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 5889 # number of ReadCleanReq hits
351 system.cpu.l2cache.ReadCleanReq_hits::total 5889 # number of ReadCleanReq hits
352 system.cpu.l2cache.ReadSharedReq_hits::cpu.data 53 # number of ReadSharedReq hits
353 system.cpu.l2cache.ReadSharedReq_hits::total 53 # number of ReadSharedReq hits
354 system.cpu.l2cache.demand_hits::cpu.inst 5889 # number of demand (read+write) hits
355 system.cpu.l2cache.demand_hits::cpu.data 79 # number of demand (read+write) hits
356 system.cpu.l2cache.demand_hits::total 5968 # number of demand (read+write) hits
357 system.cpu.l2cache.overall_hits::cpu.inst 5889 # number of overall hits
358 system.cpu.l2cache.overall_hits::cpu.data 79 # number of overall hits
359 system.cpu.l2cache.overall_hits::total 5968 # number of overall hits
360 system.cpu.l2cache.ReadExReq_misses::cpu.data 1722 # number of ReadExReq misses
361 system.cpu.l2cache.ReadExReq_misses::total 1722 # number of ReadExReq misses
362 system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2621 # number of ReadCleanReq misses
363 system.cpu.l2cache.ReadCleanReq_misses::total 2621 # number of ReadCleanReq misses
364 system.cpu.l2cache.ReadSharedReq_misses::cpu.data 422 # number of ReadSharedReq misses
365 system.cpu.l2cache.ReadSharedReq_misses::total 422 # number of ReadSharedReq misses
366 system.cpu.l2cache.demand_misses::cpu.inst 2621 # number of demand (read+write) misses
367 system.cpu.l2cache.demand_misses::cpu.data 2144 # number of demand (read+write) misses
368 system.cpu.l2cache.demand_misses::total 4765 # number of demand (read+write) misses
369 system.cpu.l2cache.overall_misses::cpu.inst 2621 # number of overall misses
370 system.cpu.l2cache.overall_misses::cpu.data 2144 # number of overall misses
371 system.cpu.l2cache.overall_misses::total 4765 # number of overall misses
372 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 102460000 # number of ReadExReq miss cycles
373 system.cpu.l2cache.ReadExReq_miss_latency::total 102460000 # number of ReadExReq miss cycles
374 system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 155964000 # number of ReadCleanReq miss cycles
375 system.cpu.l2cache.ReadCleanReq_miss_latency::total 155964000 # number of ReadCleanReq miss cycles
376 system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 25110500 # number of ReadSharedReq miss cycles
377 system.cpu.l2cache.ReadSharedReq_miss_latency::total 25110500 # number of ReadSharedReq miss cycles
378 system.cpu.l2cache.demand_miss_latency::cpu.inst 155964000 # number of demand (read+write) miss cycles
379 system.cpu.l2cache.demand_miss_latency::cpu.data 127570500 # number of demand (read+write) miss cycles
380 system.cpu.l2cache.demand_miss_latency::total 283534500 # number of demand (read+write) miss cycles
381 system.cpu.l2cache.overall_miss_latency::cpu.inst 155964000 # number of overall miss cycles
382 system.cpu.l2cache.overall_miss_latency::cpu.data 127570500 # number of overall miss cycles
383 system.cpu.l2cache.overall_miss_latency::total 283534500 # number of overall miss cycles
384 system.cpu.l2cache.WritebackDirty_accesses::writebacks 107 # number of WritebackDirty accesses(hits+misses)
385 system.cpu.l2cache.WritebackDirty_accesses::total 107 # number of WritebackDirty accesses(hits+misses)
386 system.cpu.l2cache.WritebackClean_accesses::writebacks 6681 # number of WritebackClean accesses(hits+misses)
387 system.cpu.l2cache.WritebackClean_accesses::total 6681 # number of WritebackClean accesses(hits+misses)
388 system.cpu.l2cache.ReadExReq_accesses::cpu.data 1748 # number of ReadExReq accesses(hits+misses)
389 system.cpu.l2cache.ReadExReq_accesses::total 1748 # number of ReadExReq accesses(hits+misses)
390 system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 8510 # number of ReadCleanReq accesses(hits+misses)
391 system.cpu.l2cache.ReadCleanReq_accesses::total 8510 # number of ReadCleanReq accesses(hits+misses)
392 system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 475 # number of ReadSharedReq accesses(hits+misses)
393 system.cpu.l2cache.ReadSharedReq_accesses::total 475 # number of ReadSharedReq accesses(hits+misses)
394 system.cpu.l2cache.demand_accesses::cpu.inst 8510 # number of demand (read+write) accesses
395 system.cpu.l2cache.demand_accesses::cpu.data 2223 # number of demand (read+write) accesses
396 system.cpu.l2cache.demand_accesses::total 10733 # number of demand (read+write) accesses
397 system.cpu.l2cache.overall_accesses::cpu.inst 8510 # number of overall (read+write) accesses
398 system.cpu.l2cache.overall_accesses::cpu.data 2223 # number of overall (read+write) accesses
399 system.cpu.l2cache.overall_accesses::total 10733 # number of overall (read+write) accesses
400 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.985126 # miss rate for ReadExReq accesses
401 system.cpu.l2cache.ReadExReq_miss_rate::total 0.985126 # miss rate for ReadExReq accesses
402 system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.307991 # miss rate for ReadCleanReq accesses
403 system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.307991 # miss rate for ReadCleanReq accesses
404 system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.888421 # miss rate for ReadSharedReq accesses
405 system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.888421 # miss rate for ReadSharedReq accesses
406 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.307991 # miss rate for demand accesses
407 system.cpu.l2cache.demand_miss_rate::cpu.data 0.964462 # miss rate for demand accesses
408 system.cpu.l2cache.demand_miss_rate::total 0.443958 # miss rate for demand accesses
409 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.307991 # miss rate for overall accesses
410 system.cpu.l2cache.overall_miss_rate::cpu.data 0.964462 # miss rate for overall accesses
411 system.cpu.l2cache.overall_miss_rate::total 0.443958 # miss rate for overall accesses
412 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.580720 # average ReadExReq miss latency
413 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.580720 # average ReadExReq miss latency
414 system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59505.532240 # average ReadCleanReq miss latency
415 system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59505.532240 # average ReadCleanReq miss latency
416 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59503.554502 # average ReadSharedReq miss latency
417 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59503.554502 # average ReadSharedReq miss latency
418 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59505.532240 # average overall miss latency
419 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59501.166045 # average overall miss latency
420 system.cpu.l2cache.demand_avg_miss_latency::total 59503.567681 # average overall miss latency
421 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59505.532240 # average overall miss latency
422 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59501.166045 # average overall miss latency
423 system.cpu.l2cache.overall_avg_miss_latency::total 59503.567681 # average overall miss latency
424 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
425 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
426 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
427 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
428 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
429 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
430 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
431 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
432 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1722 # number of ReadExReq MSHR misses
433 system.cpu.l2cache.ReadExReq_mshr_misses::total 1722 # number of ReadExReq MSHR misses
434 system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2621 # number of ReadCleanReq MSHR misses
435 system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2621 # number of ReadCleanReq MSHR misses
436 system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 422 # number of ReadSharedReq MSHR misses
437 system.cpu.l2cache.ReadSharedReq_mshr_misses::total 422 # number of ReadSharedReq MSHR misses
438 system.cpu.l2cache.demand_mshr_misses::cpu.inst 2621 # number of demand (read+write) MSHR misses
439 system.cpu.l2cache.demand_mshr_misses::cpu.data 2144 # number of demand (read+write) MSHR misses
440 system.cpu.l2cache.demand_mshr_misses::total 4765 # number of demand (read+write) MSHR misses
441 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2621 # number of overall MSHR misses
442 system.cpu.l2cache.overall_mshr_misses::cpu.data 2144 # number of overall MSHR misses
443 system.cpu.l2cache.overall_mshr_misses::total 4765 # number of overall MSHR misses
444 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 85240000 # number of ReadExReq MSHR miss cycles
445 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 85240000 # number of ReadExReq MSHR miss cycles
446 system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 129754000 # number of ReadCleanReq MSHR miss cycles
447 system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 129754000 # number of ReadCleanReq MSHR miss cycles
448 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 20890500 # number of ReadSharedReq MSHR miss cycles
449 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 20890500 # number of ReadSharedReq MSHR miss cycles
450 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 129754000 # number of demand (read+write) MSHR miss cycles
451 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 106130500 # number of demand (read+write) MSHR miss cycles
452 system.cpu.l2cache.demand_mshr_miss_latency::total 235884500 # number of demand (read+write) MSHR miss cycles
453 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 129754000 # number of overall MSHR miss cycles
454 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 106130500 # number of overall MSHR miss cycles
455 system.cpu.l2cache.overall_mshr_miss_latency::total 235884500 # number of overall MSHR miss cycles
456 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985126 # mshr miss rate for ReadExReq accesses
457 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.985126 # mshr miss rate for ReadExReq accesses
458 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.307991 # mshr miss rate for ReadCleanReq accesses
459 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.307991 # mshr miss rate for ReadCleanReq accesses
460 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.888421 # mshr miss rate for ReadSharedReq accesses
461 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.888421 # mshr miss rate for ReadSharedReq accesses
462 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.307991 # mshr miss rate for demand accesses
463 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for demand accesses
464 system.cpu.l2cache.demand_mshr_miss_rate::total 0.443958 # mshr miss rate for demand accesses
465 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.307991 # mshr miss rate for overall accesses
466 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for overall accesses
467 system.cpu.l2cache.overall_mshr_miss_rate::total 0.443958 # mshr miss rate for overall accesses
468 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.580720 # average ReadExReq mshr miss latency
469 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.580720 # average ReadExReq mshr miss latency
470 system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49505.532240 # average ReadCleanReq mshr miss latency
471 system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49505.532240 # average ReadCleanReq mshr miss latency
472 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49503.554502 # average ReadSharedReq mshr miss latency
473 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49503.554502 # average ReadSharedReq mshr miss latency
474 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49505.532240 # average overall mshr miss latency
475 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49501.166045 # average overall mshr miss latency
476 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49503.567681 # average overall mshr miss latency
477 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49505.532240 # average overall mshr miss latency
478 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49501.166045 # average overall mshr miss latency
479 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49503.567681 # average overall mshr miss latency
480 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
481 system.cpu.toL2Bus.snoop_filter.tot_requests 17571 # Total number of requests made to the snoop filter.
482 system.cpu.toL2Bus.snoop_filter.hit_single_requests 6838 # Number of requests hitting in the snoop filter with a single holder of the requested data.
483 system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
484 system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
485 system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
486 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
487 system.cpu.toL2Bus.trans_dist::ReadResp 8985 # Transaction distribution
488 system.cpu.toL2Bus.trans_dist::WritebackDirty 107 # Transaction distribution
489 system.cpu.toL2Bus.trans_dist::WritebackClean 6681 # Transaction distribution
490 system.cpu.toL2Bus.trans_dist::CleanEvict 50 # Transaction distribution
491 system.cpu.toL2Bus.trans_dist::ReadExReq 1748 # Transaction distribution
492 system.cpu.toL2Bus.trans_dist::ReadExResp 1748 # Transaction distribution
493 system.cpu.toL2Bus.trans_dist::ReadCleanReq 8510 # Transaction distribution
494 system.cpu.toL2Bus.trans_dist::ReadSharedReq 475 # Transaction distribution
495 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23701 # Packet count per connected master and slave (bytes)
496 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4603 # Packet count per connected master and slave (bytes)
497 system.cpu.toL2Bus.pkt_count::total 28304 # Packet count per connected master and slave (bytes)
498 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 972224 # Cumulative packet size per connected master and slave (bytes)
499 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 149120 # Cumulative packet size per connected master and slave (bytes)
500 system.cpu.toL2Bus.pkt_size::total 1121344 # Cumulative packet size per connected master and slave (bytes)
501 system.cpu.toL2Bus.snoops 0 # Total snoops (count)
502 system.cpu.toL2Bus.snoop_fanout::samples 10733 # Request fanout histogram
503 system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram
504 system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
505 system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
506 system.cpu.toL2Bus.snoop_fanout::0 10733 100.00% 100.00% # Request fanout histogram
507 system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
508 system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
509 system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
510 system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
511 system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram
512 system.cpu.toL2Bus.snoop_fanout::total 10733 # Request fanout histogram
513 system.cpu.toL2Bus.reqLayer0.occupancy 15573500 # Layer occupancy (ticks)
514 system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
515 system.cpu.toL2Bus.respLayer0.occupancy 12765000 # Layer occupancy (ticks)
516 system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
517 system.cpu.toL2Bus.respLayer1.occupancy 3334500 # Layer occupancy (ticks)
518 system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
519 system.membus.trans_dist::ReadResp 3043 # Transaction distribution
520 system.membus.trans_dist::ReadExReq 1722 # Transaction distribution
521 system.membus.trans_dist::ReadExResp 1722 # Transaction distribution
522 system.membus.trans_dist::ReadSharedReq 3043 # Transaction distribution
523 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 9530 # Packet count per connected master and slave (bytes)
524 system.membus.pkt_count::total 9530 # Packet count per connected master and slave (bytes)
525 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 304960 # Cumulative packet size per connected master and slave (bytes)
526 system.membus.pkt_size::total 304960 # Cumulative packet size per connected master and slave (bytes)
527 system.membus.snoops 0 # Total snoops (count)
528 system.membus.snoop_fanout::samples 4765 # Request fanout histogram
529 system.membus.snoop_fanout::mean 0 # Request fanout histogram
530 system.membus.snoop_fanout::stdev 0 # Request fanout histogram
531 system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
532 system.membus.snoop_fanout::0 4765 100.00% 100.00% # Request fanout histogram
533 system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
534 system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
535 system.membus.snoop_fanout::min_value 0 # Request fanout histogram
536 system.membus.snoop_fanout::max_value 0 # Request fanout histogram
537 system.membus.snoop_fanout::total 4765 # Request fanout histogram
538 system.membus.reqLayer0.occupancy 4782000 # Layer occupancy (ticks)
539 system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
540 system.membus.respLayer1.occupancy 23825000 # Layer occupancy (ticks)
541 system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
543 ---------- End Simulation Statistics ----------
projects / gem5.git / blob