tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt

   1
   2 ---------- Begin Simulation Statistics ----------
   3 sim_seconds                                  0.099596
   4 sim_ticks                                 99596491500
   5 final_tick                                99596491500
   6 sim_freq                                 1000000000000
   7 host_inst_rate                                 936229
   8 host_op_rate                                   986937
   9 host_tick_rate                              541124372
  10 host_mem_usage                                 274820
  11 host_seconds                                   184.05
  12 sim_insts                                   172317410
  13 sim_ops                                     181650342
  14 system.voltage_domain.voltage                       1
  15 system.clk_domain.clock                          1000
  16 system.physmem.pwrStateResidencyTicks::UNDEFINED  99596491500
  17 system.physmem.bytes_read::cpu.inst         759440208
  18 system.physmem.bytes_read::cpu.data         110533661
  19 system.physmem.bytes_read::total            869973869
  20 system.physmem.bytes_inst_read::cpu.inst    759440208
  21 system.physmem.bytes_inst_read::total       759440208
  22 system.physmem.bytes_written::cpu.data       45252940
  23 system.physmem.bytes_written::total          45252940
  24 system.physmem.num_reads::cpu.inst          189860052
  25 system.physmem.num_reads::cpu.data           27777721
  26 system.physmem.num_reads::total             217637773
  27 system.physmem.num_writes::cpu.data          12386694
  28 system.physmem.num_writes::total             12386694
  29 system.physmem.bw_read::cpu.inst           7625170290
  30 system.physmem.bw_read::cpu.data           1109814807
  31 system.physmem.bw_read::total              8734985097
  32 system.physmem.bw_inst_read::cpu.inst      7625170290
  33 system.physmem.bw_inst_read::total         7625170290
  34 system.physmem.bw_write::cpu.data           454362792
  35 system.physmem.bw_write::total              454362792
  36 system.physmem.bw_total::cpu.inst          7625170290
  37 system.physmem.bw_total::cpu.data          1564177600
  38 system.physmem.bw_total::total             9189347890
  39 system.pwrStateResidencyTicks::UNDEFINED  99596491500
  40 system.cpu_clk_domain.clock                       500
  41 system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED  99596491500
  42 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0
  43 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0
  44 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0
  45 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0
  46 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0
  47 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0
  48 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0
  49 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0
  50 system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0
  51 system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0
  52 system.cpu.dstage2_mmu.stage2_tlb.read_hits            0
  53 system.cpu.dstage2_mmu.stage2_tlb.read_misses            0
  54 system.cpu.dstage2_mmu.stage2_tlb.write_hits            0
  55 system.cpu.dstage2_mmu.stage2_tlb.write_misses            0
  56 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0
  57 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0
  58 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0
  59 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0
  60 system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0
  61 system.cpu.dstage2_mmu.stage2_tlb.align_faults            0
  62 system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0
  63 system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0
  64 system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0
  65 system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0
  66 system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0
  67 system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
  68 system.cpu.dstage2_mmu.stage2_tlb.hits              0
  69 system.cpu.dstage2_mmu.stage2_tlb.misses            0
  70 system.cpu.dstage2_mmu.stage2_tlb.accesses            0
  71 system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED  99596491500
  72 system.cpu.dtb.walker.walks                         0
  73 system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0
  74 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0
  75 system.cpu.dtb.walker.walkRequestOrigin_Requested::total            0
  76 system.cpu.dtb.walker.walkRequestOrigin_Completed::Data            0
  77 system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0
  78 system.cpu.dtb.walker.walkRequestOrigin_Completed::total            0
  79 system.cpu.dtb.walker.walkRequestOrigin::total            0
  80 system.cpu.dtb.inst_hits                            0
  81 system.cpu.dtb.inst_misses                          0
  82 system.cpu.dtb.read_hits                            0
  83 system.cpu.dtb.read_misses                          0
  84 system.cpu.dtb.write_hits                           0
  85 system.cpu.dtb.write_misses                         0
  86 system.cpu.dtb.flush_tlb                            0
  87 system.cpu.dtb.flush_tlb_mva                        0
  88 system.cpu.dtb.flush_tlb_mva_asid                   0
  89 system.cpu.dtb.flush_tlb_asid                       0
  90 system.cpu.dtb.flush_entries                        0
  91 system.cpu.dtb.align_faults                         0
  92 system.cpu.dtb.prefetch_faults                      0
  93 system.cpu.dtb.domain_faults                        0
  94 system.cpu.dtb.perms_faults                         0
  95 system.cpu.dtb.read_accesses                        0
  96 system.cpu.dtb.write_accesses                       0
  97 system.cpu.dtb.inst_accesses                        0
  98 system.cpu.dtb.hits                                 0
  99 system.cpu.dtb.misses                               0
 100 system.cpu.dtb.accesses                             0
 101 system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED  99596491500
 102 system.cpu.istage2_mmu.stage2_tlb.walker.walks            0
 103 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0
 104 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0
 105 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0
 106 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0
 107 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0
 108 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0
 109 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0
 110 system.cpu.istage2_mmu.stage2_tlb.inst_hits            0
 111 system.cpu.istage2_mmu.stage2_tlb.inst_misses            0
 112 system.cpu.istage2_mmu.stage2_tlb.read_hits            0
 113 system.cpu.istage2_mmu.stage2_tlb.read_misses            0
 114 system.cpu.istage2_mmu.stage2_tlb.write_hits            0
 115 system.cpu.istage2_mmu.stage2_tlb.write_misses            0
 116 system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0
 117 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0
 118 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0
 119 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0
 120 system.cpu.istage2_mmu.stage2_tlb.flush_entries            0
 121 system.cpu.istage2_mmu.stage2_tlb.align_faults            0
 122 system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0
 123 system.cpu.istage2_mmu.stage2_tlb.domain_faults            0
 124 system.cpu.istage2_mmu.stage2_tlb.perms_faults            0
 125 system.cpu.istage2_mmu.stage2_tlb.read_accesses            0
 126 system.cpu.istage2_mmu.stage2_tlb.write_accesses            0
 127 system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 128 system.cpu.istage2_mmu.stage2_tlb.hits              0
 129 system.cpu.istage2_mmu.stage2_tlb.misses            0
 130 system.cpu.istage2_mmu.stage2_tlb.accesses            0
 131 system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED  99596491500
 132 system.cpu.itb.walker.walks                         0
 133 system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0
 134 system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0
 135 system.cpu.itb.walker.walkRequestOrigin_Requested::total            0
 136 system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0
 137 system.cpu.itb.walker.walkRequestOrigin_Completed::Inst            0
 138 system.cpu.itb.walker.walkRequestOrigin_Completed::total            0
 139 system.cpu.itb.walker.walkRequestOrigin::total            0
 140 system.cpu.itb.inst_hits                            0
 141 system.cpu.itb.inst_misses                          0
 142 system.cpu.itb.read_hits                            0
 143 system.cpu.itb.read_misses                          0
 144 system.cpu.itb.write_hits                           0
 145 system.cpu.itb.write_misses                         0
 146 system.cpu.itb.flush_tlb                            0
 147 system.cpu.itb.flush_tlb_mva                        0
 148 system.cpu.itb.flush_tlb_mva_asid                   0
 149 system.cpu.itb.flush_tlb_asid                       0
 150 system.cpu.itb.flush_entries                        0
 151 system.cpu.itb.align_faults                         0
 152 system.cpu.itb.prefetch_faults                      0
 153 system.cpu.itb.domain_faults                        0
 154 system.cpu.itb.perms_faults                         0
 155 system.cpu.itb.read_accesses                        0
 156 system.cpu.itb.write_accesses                       0
 157 system.cpu.itb.inst_accesses                        0
 158 system.cpu.itb.hits                                 0
 159 system.cpu.itb.misses                               0
 160 system.cpu.itb.accesses                             0
 161 system.cpu.workload.numSyscalls                   400
 162 system.cpu.pwrStateResidencyTicks::ON     99596491500
 163 system.cpu.numCycles                        199192984
 164 system.cpu.numWorkItemsStarted                      0
 165 system.cpu.numWorkItemsCompleted                    0
 166 system.cpu.committedInsts                   172317410
 167 system.cpu.committedOps                     181650342
 168 system.cpu.num_int_alu_accesses             143085668
 169 system.cpu.num_fp_alu_accesses                1752310
 170 system.cpu.num_func_calls                     3545028
 171 system.cpu.num_conditional_control_insts     32201008
 172 system.cpu.num_int_insts                    143085668
 173 system.cpu.num_fp_insts                       1752310
 174 system.cpu.num_int_register_reads           238310719
 175 system.cpu.num_int_register_writes           98192342
 176 system.cpu.num_fp_register_reads              2822225
 177 system.cpu.num_fp_register_writes             2378039
 178 system.cpu.num_cc_register_reads            543309970
 179 system.cpu.num_cc_register_writes           190815535
 180 system.cpu.num_mem_refs                      40540779
 181 system.cpu.num_load_insts                    27896144
 182 system.cpu.num_store_insts                   12644635
 183 system.cpu.num_idle_cycles                          0
 184 system.cpu.num_busy_cycles                  199192984
 185 system.cpu.not_idle_fraction                        1
 186 system.cpu.idle_fraction                            0
 187 system.cpu.Branches                          40300312
 188 system.cpu.op_class::No_OpClass                     0      0.00%      0.00%
 189 system.cpu.op_class::IntAlu                 138988213     76.51%     76.51%
 190 system.cpu.op_class::IntMult                   908940      0.50%     77.01%
 191 system.cpu.op_class::IntDiv                         0      0.00%     77.01%
 192 system.cpu.op_class::FloatAdd                       0      0.00%     77.01%
 193 system.cpu.op_class::FloatCmp                       0      0.00%     77.01%
 194 system.cpu.op_class::FloatCvt                       0      0.00%     77.01%
 195 system.cpu.op_class::FloatMult                      0      0.00%     77.01%
 196 system.cpu.op_class::FloatMultAcc                   0      0.00%     77.01%
 197 system.cpu.op_class::FloatDiv                       0      0.00%     77.01%
 198 system.cpu.op_class::FloatMisc                      0      0.00%     77.01%
 199 system.cpu.op_class::FloatSqrt                      0      0.00%     77.01%
 200 system.cpu.op_class::SimdAdd                        0      0.00%     77.01%
 201 system.cpu.op_class::SimdAddAcc                     0      0.00%     77.01%
 202 system.cpu.op_class::SimdAlu                        0      0.00%     77.01%
 203 system.cpu.op_class::SimdCmp                        0      0.00%     77.01%
 204 system.cpu.op_class::SimdCvt                        0      0.00%     77.01%
 205 system.cpu.op_class::SimdMisc                       0      0.00%     77.01%
 206 system.cpu.op_class::SimdMult                       0      0.00%     77.01%
 207 system.cpu.op_class::SimdMultAcc                    0      0.00%     77.01%
 208 system.cpu.op_class::SimdShift                      0      0.00%     77.01%
 209 system.cpu.op_class::SimdShiftAcc                   0      0.00%     77.01%
 210 system.cpu.op_class::SimdSqrt                       0      0.00%     77.01%
 211 system.cpu.op_class::SimdFloatAdd               32754      0.02%     77.03%
 212 system.cpu.op_class::SimdFloatAlu                   0      0.00%     77.03%
 213 system.cpu.op_class::SimdFloatCmp              154829      0.09%     77.12%
 214 system.cpu.op_class::SimdFloatCvt              238880      0.13%     77.25%
 215 system.cpu.op_class::SimdFloatDiv               76016      0.04%     77.29%
 216 system.cpu.op_class::SimdFloatMisc             437591      0.24%     77.53%
 217 system.cpu.op_class::SimdFloatMult             200806      0.11%     77.64%
 218 system.cpu.op_class::SimdFloatMultAcc           71617      0.04%     77.68%
 219 system.cpu.op_class::SimdFloatSqrt                318      0.00%     77.68%
 220 system.cpu.op_class::MemRead                 27348059     15.06%     92.74%
 221 system.cpu.op_class::MemWrite                12498389      6.88%     99.62%
 222 system.cpu.op_class::FloatMemRead              548085      0.30%     99.92%
 223 system.cpu.op_class::FloatMemWrite             146246      0.08%    100.00%
 224 system.cpu.op_class::IprAccess                      0      0.00%    100.00%
 225 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00%
 226 system.cpu.op_class::total                  181650743
 227 system.membus.snoop_filter.tot_requests             0
 228 system.membus.snoop_filter.hit_single_requests            0
 229 system.membus.snoop_filter.hit_multi_requests            0
 230 system.membus.snoop_filter.tot_snoops               0
 231 system.membus.snoop_filter.hit_single_snoops            0
 232 system.membus.snoop_filter.hit_multi_snoops            0
 233 system.membus.pwrStateResidencyTicks::UNDEFINED  99596491500
 234 system.membus.trans_dist::ReadReq           217614903
 235 system.membus.trans_dist::ReadResp          217637310
 236 system.membus.trans_dist::WriteReq           12364287
 237 system.membus.trans_dist::WriteResp          12364287
 238 system.membus.trans_dist::SoftPFReq               463
 239 system.membus.trans_dist::SoftPFResp              463
 240 system.membus.trans_dist::LoadLockedReq         22407
 241 system.membus.trans_dist::StoreCondReq          22407
 242 system.membus.trans_dist::StoreCondResp         22407
 243 system.membus.pkt_count_system.cpu.icache_port::system.physmem.port    379720104
 244 system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port     80328830
 245 system.membus.pkt_count::total              460048934
 246 system.membus.pkt_size_system.cpu.icache_port::system.physmem.port    759440208
 247 system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port    155786601
 248 system.membus.pkt_size::total               915226809
 249 system.membus.snoops                                0
 250 system.membus.snoopTraffic                          0
 251 system.membus.snoop_fanout::samples         230024467
 252 system.membus.snoop_fanout::mean                    0
 253 system.membus.snoop_fanout::stdev                   0
 254 system.membus.snoop_fanout::underflows              0      0.00%      0.00%
 255 system.membus.snoop_fanout::0               230024467    100.00%    100.00%
 256 system.membus.snoop_fanout::1                       0      0.00%    100.00%
 257 system.membus.snoop_fanout::overflows               0      0.00%    100.00%
 258 system.membus.snoop_fanout::min_value               0
 259 system.membus.snoop_fanout::max_value               0
 260 system.membus.snoop_fanout::total           230024467
 261
 262 ---------- End Simulation Statistics   ----------