2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.099596 # Number of seconds simulated
4 sim_ticks 99596491500 # Number of ticks simulated
5 final_tick 99596491500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 1150155 # Simulator instruction rate (inst/s)
8 host_op_rate 1212449 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 664769571 # Simulator tick rate (ticks/s)
10 host_mem_usage 303552 # Number of bytes of host memory used
11 host_seconds 149.82 # Real time elapsed on the host
12 sim_insts 172317410 # Number of instructions simulated
13 sim_ops 181650342 # Number of ops (including micro ops) simulated
14 system.voltage_domain.voltage 1 # Voltage in Volts
15 system.clk_domain.clock 1000 # Clock period in ticks
16 system.physmem.bytes_read::cpu.inst 759440208 # Number of bytes read from this memory
17 system.physmem.bytes_read::cpu.data 110533661 # Number of bytes read from this memory
18 system.physmem.bytes_read::total 869973869 # Number of bytes read from this memory
19 system.physmem.bytes_inst_read::cpu.inst 759440208 # Number of instructions bytes read from this memory
20 system.physmem.bytes_inst_read::total 759440208 # Number of instructions bytes read from this memory
21 system.physmem.bytes_written::cpu.data 45252940 # Number of bytes written to this memory
22 system.physmem.bytes_written::total 45252940 # Number of bytes written to this memory
23 system.physmem.num_reads::cpu.inst 189860052 # Number of read requests responded to by this memory
24 system.physmem.num_reads::cpu.data 27777721 # Number of read requests responded to by this memory
25 system.physmem.num_reads::total 217637773 # Number of read requests responded to by this memory
26 system.physmem.num_writes::cpu.data 12386694 # Number of write requests responded to by this memory
27 system.physmem.num_writes::total 12386694 # Number of write requests responded to by this memory
28 system.physmem.bw_read::cpu.inst 7625170290 # Total read bandwidth from this memory (bytes/s)
29 system.physmem.bw_read::cpu.data 1109814807 # Total read bandwidth from this memory (bytes/s)
30 system.physmem.bw_read::total 8734985097 # Total read bandwidth from this memory (bytes/s)
31 system.physmem.bw_inst_read::cpu.inst 7625170290 # Instruction read bandwidth from this memory (bytes/s)
32 system.physmem.bw_inst_read::total 7625170290 # Instruction read bandwidth from this memory (bytes/s)
33 system.physmem.bw_write::cpu.data 454362792 # Write bandwidth from this memory (bytes/s)
34 system.physmem.bw_write::total 454362792 # Write bandwidth from this memory (bytes/s)
35 system.physmem.bw_total::cpu.inst 7625170290 # Total bandwidth to/from this memory (bytes/s)
36 system.physmem.bw_total::cpu.data 1564177600 # Total bandwidth to/from this memory (bytes/s)
37 system.physmem.bw_total::total 9189347890 # Total bandwidth to/from this memory (bytes/s)
38 system.cpu_clk_domain.clock 500 # Clock period in ticks
39 system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
40 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
41 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
42 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
43 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
44 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
45 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
46 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
47 system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
48 system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
49 system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
50 system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
51 system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
52 system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
53 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
54 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
55 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
56 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
57 system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
58 system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
59 system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
60 system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
61 system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
62 system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
63 system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
64 system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
65 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
66 system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
67 system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
68 system.cpu.dtb.walker.walks 0 # Table walker walks requested
69 system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
70 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
71 system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
72 system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
73 system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
74 system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
75 system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
76 system.cpu.dtb.inst_hits 0 # ITB inst hits
77 system.cpu.dtb.inst_misses 0 # ITB inst misses
78 system.cpu.dtb.read_hits 0 # DTB read hits
79 system.cpu.dtb.read_misses 0 # DTB read misses
80 system.cpu.dtb.write_hits 0 # DTB write hits
81 system.cpu.dtb.write_misses 0 # DTB write misses
82 system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
83 system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
84 system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
85 system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
86 system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
87 system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
88 system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
89 system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
90 system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
91 system.cpu.dtb.read_accesses 0 # DTB read accesses
92 system.cpu.dtb.write_accesses 0 # DTB write accesses
93 system.cpu.dtb.inst_accesses 0 # ITB inst accesses
94 system.cpu.dtb.hits 0 # DTB hits
95 system.cpu.dtb.misses 0 # DTB misses
96 system.cpu.dtb.accesses 0 # DTB accesses
97 system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
98 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
99 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
100 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
101 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
102 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
103 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
104 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
105 system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
106 system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
107 system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
108 system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
109 system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
110 system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
111 system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
112 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
113 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
114 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
115 system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
116 system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
117 system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
118 system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
119 system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
120 system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
121 system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
122 system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
123 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
124 system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
125 system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
126 system.cpu.itb.walker.walks 0 # Table walker walks requested
127 system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
128 system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
129 system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
130 system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
131 system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
132 system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
133 system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
134 system.cpu.itb.inst_hits 0 # ITB inst hits
135 system.cpu.itb.inst_misses 0 # ITB inst misses
136 system.cpu.itb.read_hits 0 # DTB read hits
137 system.cpu.itb.read_misses 0 # DTB read misses
138 system.cpu.itb.write_hits 0 # DTB write hits
139 system.cpu.itb.write_misses 0 # DTB write misses
140 system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
141 system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
142 system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
143 system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
144 system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
145 system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
146 system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
147 system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
148 system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
149 system.cpu.itb.read_accesses 0 # DTB read accesses
150 system.cpu.itb.write_accesses 0 # DTB write accesses
151 system.cpu.itb.inst_accesses 0 # ITB inst accesses
152 system.cpu.itb.hits 0 # DTB hits
153 system.cpu.itb.misses 0 # DTB misses
154 system.cpu.itb.accesses 0 # DTB accesses
155 system.cpu.workload.num_syscalls 400 # Number of system calls
156 system.cpu.numCycles 199192984 # number of cpu cycles simulated
157 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
158 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
159 system.cpu.committedInsts 172317410 # Number of instructions committed
160 system.cpu.committedOps 181650342 # Number of ops (including micro ops) committed
161 system.cpu.num_int_alu_accesses 143085668 # Number of integer alu accesses
162 system.cpu.num_fp_alu_accesses 1752310 # Number of float alu accesses
163 system.cpu.num_func_calls 3545028 # number of times a function call or return occured
164 system.cpu.num_conditional_control_insts 32201008 # number of instructions that are conditional controls
165 system.cpu.num_int_insts 143085668 # number of integer instructions
166 system.cpu.num_fp_insts 1752310 # number of float instructions
167 system.cpu.num_int_register_reads 241970171 # number of times the integer registers were read
168 system.cpu.num_int_register_writes 98192342 # number of times the integer registers were written
169 system.cpu.num_fp_register_reads 2822225 # number of times the floating registers were read
170 system.cpu.num_fp_register_writes 2378039 # number of times the floating registers were written
171 system.cpu.num_cc_register_reads 543309970 # number of times the CC registers were read
172 system.cpu.num_cc_register_writes 190815535 # number of times the CC registers were written
173 system.cpu.num_mem_refs 40540779 # number of memory refs
174 system.cpu.num_load_insts 27896144 # Number of load instructions
175 system.cpu.num_store_insts 12644635 # Number of store instructions
176 system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
177 system.cpu.num_busy_cycles 199192983.998000 # Number of busy cycles
178 system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
179 system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
180 system.cpu.Branches 40300312 # Number of branches fetched
181 system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
182 system.cpu.op_class::IntAlu 138988213 76.51% 76.51% # Class of executed instruction
183 system.cpu.op_class::IntMult 908940 0.50% 77.01% # Class of executed instruction
184 system.cpu.op_class::IntDiv 0 0.00% 77.01% # Class of executed instruction
185 system.cpu.op_class::FloatAdd 0 0.00% 77.01% # Class of executed instruction
186 system.cpu.op_class::FloatCmp 0 0.00% 77.01% # Class of executed instruction
187 system.cpu.op_class::FloatCvt 0 0.00% 77.01% # Class of executed instruction
188 system.cpu.op_class::FloatMult 0 0.00% 77.01% # Class of executed instruction
189 system.cpu.op_class::FloatDiv 0 0.00% 77.01% # Class of executed instruction
190 system.cpu.op_class::FloatSqrt 0 0.00% 77.01% # Class of executed instruction
191 system.cpu.op_class::SimdAdd 0 0.00% 77.01% # Class of executed instruction
192 system.cpu.op_class::SimdAddAcc 0 0.00% 77.01% # Class of executed instruction
193 system.cpu.op_class::SimdAlu 0 0.00% 77.01% # Class of executed instruction
194 system.cpu.op_class::SimdCmp 0 0.00% 77.01% # Class of executed instruction
195 system.cpu.op_class::SimdCvt 0 0.00% 77.01% # Class of executed instruction
196 system.cpu.op_class::SimdMisc 0 0.00% 77.01% # Class of executed instruction
197 system.cpu.op_class::SimdMult 0 0.00% 77.01% # Class of executed instruction
198 system.cpu.op_class::SimdMultAcc 0 0.00% 77.01% # Class of executed instruction
199 system.cpu.op_class::SimdShift 0 0.00% 77.01% # Class of executed instruction
200 system.cpu.op_class::SimdShiftAcc 0 0.00% 77.01% # Class of executed instruction
201 system.cpu.op_class::SimdSqrt 0 0.00% 77.01% # Class of executed instruction
202 system.cpu.op_class::SimdFloatAdd 32754 0.02% 77.03% # Class of executed instruction
203 system.cpu.op_class::SimdFloatAlu 0 0.00% 77.03% # Class of executed instruction
204 system.cpu.op_class::SimdFloatCmp 154829 0.09% 77.12% # Class of executed instruction
205 system.cpu.op_class::SimdFloatCvt 238880 0.13% 77.25% # Class of executed instruction
206 system.cpu.op_class::SimdFloatDiv 76016 0.04% 77.29% # Class of executed instruction
207 system.cpu.op_class::SimdFloatMisc 437591 0.24% 77.53% # Class of executed instruction
208 system.cpu.op_class::SimdFloatMult 200806 0.11% 77.64% # Class of executed instruction
209 system.cpu.op_class::SimdFloatMultAcc 71617 0.04% 77.68% # Class of executed instruction
210 system.cpu.op_class::SimdFloatSqrt 318 0.00% 77.68% # Class of executed instruction
211 system.cpu.op_class::MemRead 27896144 15.36% 93.04% # Class of executed instruction
212 system.cpu.op_class::MemWrite 12644635 6.96% 100.00% # Class of executed instruction
213 system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
214 system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
215 system.cpu.op_class::total 181650743 # Class of executed instruction
216 system.membus.trans_dist::ReadReq 217614903 # Transaction distribution
217 system.membus.trans_dist::ReadResp 217637310 # Transaction distribution
218 system.membus.trans_dist::WriteReq 12364287 # Transaction distribution
219 system.membus.trans_dist::WriteResp 12364287 # Transaction distribution
220 system.membus.trans_dist::SoftPFReq 463 # Transaction distribution
221 system.membus.trans_dist::SoftPFResp 463 # Transaction distribution
222 system.membus.trans_dist::LoadLockedReq 22407 # Transaction distribution
223 system.membus.trans_dist::StoreCondReq 22407 # Transaction distribution
224 system.membus.trans_dist::StoreCondResp 22407 # Transaction distribution
225 system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 379720104 # Packet count per connected master and slave (bytes)
226 system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 80328830 # Packet count per connected master and slave (bytes)
227 system.membus.pkt_count::total 460048934 # Packet count per connected master and slave (bytes)
228 system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 759440208 # Cumulative packet size per connected master and slave (bytes)
229 system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 155786601 # Cumulative packet size per connected master and slave (bytes)
230 system.membus.pkt_size::total 915226809 # Cumulative packet size per connected master and slave (bytes)
231 system.membus.snoops 0 # Total snoops (count)
232 system.membus.snoop_fanout::samples 230024467 # Request fanout histogram
233 system.membus.snoop_fanout::mean 0.825391 # Request fanout histogram
234 system.membus.snoop_fanout::stdev 0.379633 # Request fanout histogram
235 system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
236 system.membus.snoop_fanout::0 40164415 17.46% 17.46% # Request fanout histogram
237 system.membus.snoop_fanout::1 189860052 82.54% 100.00% # Request fanout histogram
238 system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
239 system.membus.snoop_fanout::min_value 0 # Request fanout histogram
240 system.membus.snoop_fanout::max_value 1 # Request fanout histogram
241 system.membus.snoop_fanout::total 230024467 # Request fanout histogram
243 ---------- End Simulation Statistics ----------
projects / gem5.git / blob