2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.270600 # Number of seconds simulated
4 sim_ticks 270599529500 # Number of ticks simulated
5 final_tick 270599529500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 819670 # Simulator instruction rate (inst/s)
8 host_op_rate 819671 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 1146593662 # Simulator tick rate (ticks/s)
10 host_mem_usage 296444 # Number of bytes of host memory used
11 host_seconds 236.00 # Real time elapsed on the host
12 sim_insts 193444518 # Number of instructions simulated
13 sim_ops 193444756 # Number of ops (including micro ops) simulated
14 system.voltage_domain.voltage 1 # Voltage in Volts
15 system.clk_domain.clock 1000 # Clock period in ticks
16 system.physmem.bytes_read::cpu.inst 230208 # Number of bytes read from this memory
17 system.physmem.bytes_read::cpu.data 100864 # Number of bytes read from this memory
18 system.physmem.bytes_read::total 331072 # Number of bytes read from this memory
19 system.physmem.bytes_inst_read::cpu.inst 230208 # Number of instructions bytes read from this memory
20 system.physmem.bytes_inst_read::total 230208 # Number of instructions bytes read from this memory
21 system.physmem.num_reads::cpu.inst 3597 # Number of read requests responded to by this memory
22 system.physmem.num_reads::cpu.data 1576 # Number of read requests responded to by this memory
23 system.physmem.num_reads::total 5173 # Number of read requests responded to by this memory
24 system.physmem.bw_read::cpu.inst 850733 # Total read bandwidth from this memory (bytes/s)
25 system.physmem.bw_read::cpu.data 372743 # Total read bandwidth from this memory (bytes/s)
26 system.physmem.bw_read::total 1223476 # Total read bandwidth from this memory (bytes/s)
27 system.physmem.bw_inst_read::cpu.inst 850733 # Instruction read bandwidth from this memory (bytes/s)
28 system.physmem.bw_inst_read::total 850733 # Instruction read bandwidth from this memory (bytes/s)
29 system.physmem.bw_total::cpu.inst 850733 # Total bandwidth to/from this memory (bytes/s)
30 system.physmem.bw_total::cpu.data 372743 # Total bandwidth to/from this memory (bytes/s)
31 system.physmem.bw_total::total 1223476 # Total bandwidth to/from this memory (bytes/s)
32 system.cpu_clk_domain.clock 500 # Clock period in ticks
33 system.cpu.workload.num_syscalls 401 # Number of system calls
34 system.cpu.numCycles 541199059 # number of cpu cycles simulated
35 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
36 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
37 system.cpu.committedInsts 193444518 # Number of instructions committed
38 system.cpu.committedOps 193444756 # Number of ops (including micro ops) committed
39 system.cpu.num_int_alu_accesses 167974806 # Number of integer alu accesses
40 system.cpu.num_fp_alu_accesses 1970372 # Number of float alu accesses
41 system.cpu.num_func_calls 1957920 # number of times a function call or return occured
42 system.cpu.num_conditional_control_insts 8665106 # number of instructions that are conditional controls
43 system.cpu.num_int_insts 167974806 # number of integer instructions
44 system.cpu.num_fp_insts 1970372 # number of float instructions
45 system.cpu.num_int_register_reads 352617941 # number of times the integer registers were read
46 system.cpu.num_int_register_writes 163060123 # number of times the integer registers were written
47 system.cpu.num_fp_register_reads 3181089 # number of times the floating registers were read
48 system.cpu.num_fp_register_writes 2974850 # number of times the floating registers were written
49 system.cpu.num_mem_refs 76733958 # number of memory refs
50 system.cpu.num_load_insts 57735091 # Number of load instructions
51 system.cpu.num_store_insts 18998867 # Number of store instructions
52 system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
53 system.cpu.num_busy_cycles 541199058.998000 # Number of busy cycles
54 system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
55 system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
56 system.cpu.Branches 15132745 # Number of branches fetched
57 system.cpu.op_class::No_OpClass 13329871 6.89% 6.89% # Class of executed instruction
58 system.cpu.op_class::IntAlu 102506896 52.99% 59.88% # Class of executed instruction
59 system.cpu.op_class::IntMult 0 0.00% 59.88% # Class of executed instruction
60 system.cpu.op_class::IntDiv 0 0.00% 59.88% # Class of executed instruction
61 system.cpu.op_class::FloatAdd 875036 0.45% 60.33% # Class of executed instruction
62 system.cpu.op_class::FloatCmp 0 0.00% 60.33% # Class of executed instruction
63 system.cpu.op_class::FloatCvt 0 0.00% 60.33% # Class of executed instruction
64 system.cpu.op_class::FloatMult 0 0.00% 60.33% # Class of executed instruction
65 system.cpu.op_class::FloatDiv 0 0.00% 60.33% # Class of executed instruction
66 system.cpu.op_class::FloatSqrt 0 0.00% 60.33% # Class of executed instruction
67 system.cpu.op_class::SimdAdd 0 0.00% 60.33% # Class of executed instruction
68 system.cpu.op_class::SimdAddAcc 0 0.00% 60.33% # Class of executed instruction
69 system.cpu.op_class::SimdAlu 0 0.00% 60.33% # Class of executed instruction
70 system.cpu.op_class::SimdCmp 0 0.00% 60.33% # Class of executed instruction
71 system.cpu.op_class::SimdCvt 0 0.00% 60.33% # Class of executed instruction
72 system.cpu.op_class::SimdMisc 0 0.00% 60.33% # Class of executed instruction
73 system.cpu.op_class::SimdMult 0 0.00% 60.33% # Class of executed instruction
74 system.cpu.op_class::SimdMultAcc 0 0.00% 60.33% # Class of executed instruction
75 system.cpu.op_class::SimdShift 0 0.00% 60.33% # Class of executed instruction
76 system.cpu.op_class::SimdShiftAcc 0 0.00% 60.33% # Class of executed instruction
77 system.cpu.op_class::SimdSqrt 0 0.00% 60.33% # Class of executed instruction
78 system.cpu.op_class::SimdFloatAdd 0 0.00% 60.33% # Class of executed instruction
79 system.cpu.op_class::SimdFloatAlu 0 0.00% 60.33% # Class of executed instruction
80 system.cpu.op_class::SimdFloatCmp 0 0.00% 60.33% # Class of executed instruction
81 system.cpu.op_class::SimdFloatCvt 0 0.00% 60.33% # Class of executed instruction
82 system.cpu.op_class::SimdFloatDiv 0 0.00% 60.33% # Class of executed instruction
83 system.cpu.op_class::SimdFloatMisc 0 0.00% 60.33% # Class of executed instruction
84 system.cpu.op_class::SimdFloatMult 0 0.00% 60.33% # Class of executed instruction
85 system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.33% # Class of executed instruction
86 system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.33% # Class of executed instruction
87 system.cpu.op_class::MemRead 57735103 29.85% 90.18% # Class of executed instruction
88 system.cpu.op_class::MemWrite 18998867 9.82% 100.00% # Class of executed instruction
89 system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
90 system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
91 system.cpu.op_class::total 193445773 # Class of executed instruction
92 system.cpu.dcache.tags.replacements 2 # number of replacements
93 system.cpu.dcache.tags.tagsinuse 1237.159344 # Cycle average of tags in use
94 system.cpu.dcache.tags.total_refs 76732337 # Total number of references to valid blocks.
95 system.cpu.dcache.tags.sampled_refs 1576 # Sample count of references to valid blocks.
96 system.cpu.dcache.tags.avg_refs 48688.031091 # Average number of references to valid blocks.
97 system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
98 system.cpu.dcache.tags.occ_blocks::cpu.data 1237.159344 # Average occupied blocks per requestor
99 system.cpu.dcache.tags.occ_percent::cpu.data 0.302041 # Average percentage of cache occupancy
100 system.cpu.dcache.tags.occ_percent::total 0.302041 # Average percentage of cache occupancy
101 system.cpu.dcache.tags.occ_task_id_blocks::1024 1574 # Occupied blocks per task id
102 system.cpu.dcache.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id
103 system.cpu.dcache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id
104 system.cpu.dcache.tags.age_task_id_blocks_1024::2 39 # Occupied blocks per task id
105 system.cpu.dcache.tags.age_task_id_blocks_1024::3 271 # Occupied blocks per task id
106 system.cpu.dcache.tags.age_task_id_blocks_1024::4 1237 # Occupied blocks per task id
107 system.cpu.dcache.tags.occ_task_id_percent::1024 0.384277 # Percentage of cache occupancy per task id
108 system.cpu.dcache.tags.tag_accesses 153469402 # Number of tag accesses
109 system.cpu.dcache.tags.data_accesses 153469402 # Number of data accesses
110 system.cpu.dcache.ReadReq_hits::cpu.data 57734570 # number of ReadReq hits
111 system.cpu.dcache.ReadReq_hits::total 57734570 # number of ReadReq hits
112 system.cpu.dcache.WriteReq_hits::cpu.data 18975362 # number of WriteReq hits
113 system.cpu.dcache.WriteReq_hits::total 18975362 # number of WriteReq hits
114 system.cpu.dcache.SwapReq_hits::cpu.data 22405 # number of SwapReq hits
115 system.cpu.dcache.SwapReq_hits::total 22405 # number of SwapReq hits
116 system.cpu.dcache.demand_hits::cpu.data 76709932 # number of demand (read+write) hits
117 system.cpu.dcache.demand_hits::total 76709932 # number of demand (read+write) hits
118 system.cpu.dcache.overall_hits::cpu.data 76709932 # number of overall hits
119 system.cpu.dcache.overall_hits::total 76709932 # number of overall hits
120 system.cpu.dcache.ReadReq_misses::cpu.data 498 # number of ReadReq misses
121 system.cpu.dcache.ReadReq_misses::total 498 # number of ReadReq misses
122 system.cpu.dcache.WriteReq_misses::cpu.data 1077 # number of WriteReq misses
123 system.cpu.dcache.WriteReq_misses::total 1077 # number of WriteReq misses
124 system.cpu.dcache.SwapReq_misses::cpu.data 1 # number of SwapReq misses
125 system.cpu.dcache.SwapReq_misses::total 1 # number of SwapReq misses
126 system.cpu.dcache.demand_misses::cpu.data 1575 # number of demand (read+write) misses
127 system.cpu.dcache.demand_misses::total 1575 # number of demand (read+write) misses
128 system.cpu.dcache.overall_misses::cpu.data 1575 # number of overall misses
129 system.cpu.dcache.overall_misses::total 1575 # number of overall misses
130 system.cpu.dcache.ReadReq_miss_latency::cpu.data 30877500 # number of ReadReq miss cycles
131 system.cpu.dcache.ReadReq_miss_latency::total 30877500 # number of ReadReq miss cycles
132 system.cpu.dcache.WriteReq_miss_latency::cpu.data 66775000 # number of WriteReq miss cycles
133 system.cpu.dcache.WriteReq_miss_latency::total 66775000 # number of WriteReq miss cycles
134 system.cpu.dcache.SwapReq_miss_latency::cpu.data 62000 # number of SwapReq miss cycles
135 system.cpu.dcache.SwapReq_miss_latency::total 62000 # number of SwapReq miss cycles
136 system.cpu.dcache.demand_miss_latency::cpu.data 97652500 # number of demand (read+write) miss cycles
137 system.cpu.dcache.demand_miss_latency::total 97652500 # number of demand (read+write) miss cycles
138 system.cpu.dcache.overall_miss_latency::cpu.data 97652500 # number of overall miss cycles
139 system.cpu.dcache.overall_miss_latency::total 97652500 # number of overall miss cycles
140 system.cpu.dcache.ReadReq_accesses::cpu.data 57735068 # number of ReadReq accesses(hits+misses)
141 system.cpu.dcache.ReadReq_accesses::total 57735068 # number of ReadReq accesses(hits+misses)
142 system.cpu.dcache.WriteReq_accesses::cpu.data 18976439 # number of WriteReq accesses(hits+misses)
143 system.cpu.dcache.WriteReq_accesses::total 18976439 # number of WriteReq accesses(hits+misses)
144 system.cpu.dcache.SwapReq_accesses::cpu.data 22406 # number of SwapReq accesses(hits+misses)
145 system.cpu.dcache.SwapReq_accesses::total 22406 # number of SwapReq accesses(hits+misses)
146 system.cpu.dcache.demand_accesses::cpu.data 76711507 # number of demand (read+write) accesses
147 system.cpu.dcache.demand_accesses::total 76711507 # number of demand (read+write) accesses
148 system.cpu.dcache.overall_accesses::cpu.data 76711507 # number of overall (read+write) accesses
149 system.cpu.dcache.overall_accesses::total 76711507 # number of overall (read+write) accesses
150 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000009 # miss rate for ReadReq accesses
151 system.cpu.dcache.ReadReq_miss_rate::total 0.000009 # miss rate for ReadReq accesses
152 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000057 # miss rate for WriteReq accesses
153 system.cpu.dcache.WriteReq_miss_rate::total 0.000057 # miss rate for WriteReq accesses
154 system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.000045 # miss rate for SwapReq accesses
155 system.cpu.dcache.SwapReq_miss_rate::total 0.000045 # miss rate for SwapReq accesses
156 system.cpu.dcache.demand_miss_rate::cpu.data 0.000021 # miss rate for demand accesses
157 system.cpu.dcache.demand_miss_rate::total 0.000021 # miss rate for demand accesses
158 system.cpu.dcache.overall_miss_rate::cpu.data 0.000021 # miss rate for overall accesses
159 system.cpu.dcache.overall_miss_rate::total 0.000021 # miss rate for overall accesses
160 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62003.012048 # average ReadReq miss latency
161 system.cpu.dcache.ReadReq_avg_miss_latency::total 62003.012048 # average ReadReq miss latency
162 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62000.928505 # average WriteReq miss latency
163 system.cpu.dcache.WriteReq_avg_miss_latency::total 62000.928505 # average WriteReq miss latency
164 system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 62000 # average SwapReq miss latency
165 system.cpu.dcache.SwapReq_avg_miss_latency::total 62000 # average SwapReq miss latency
166 system.cpu.dcache.demand_avg_miss_latency::cpu.data 62001.587302 # average overall miss latency
167 system.cpu.dcache.demand_avg_miss_latency::total 62001.587302 # average overall miss latency
168 system.cpu.dcache.overall_avg_miss_latency::cpu.data 62001.587302 # average overall miss latency
169 system.cpu.dcache.overall_avg_miss_latency::total 62001.587302 # average overall miss latency
170 system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
171 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
172 system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
173 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
174 system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
175 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
176 system.cpu.dcache.fast_writes 0 # number of fast writes performed
177 system.cpu.dcache.cache_copies 0 # number of cache copies performed
178 system.cpu.dcache.writebacks::writebacks 2 # number of writebacks
179 system.cpu.dcache.writebacks::total 2 # number of writebacks
180 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 498 # number of ReadReq MSHR misses
181 system.cpu.dcache.ReadReq_mshr_misses::total 498 # number of ReadReq MSHR misses
182 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1077 # number of WriteReq MSHR misses
183 system.cpu.dcache.WriteReq_mshr_misses::total 1077 # number of WriteReq MSHR misses
184 system.cpu.dcache.SwapReq_mshr_misses::cpu.data 1 # number of SwapReq MSHR misses
185 system.cpu.dcache.SwapReq_mshr_misses::total 1 # number of SwapReq MSHR misses
186 system.cpu.dcache.demand_mshr_misses::cpu.data 1575 # number of demand (read+write) MSHR misses
187 system.cpu.dcache.demand_mshr_misses::total 1575 # number of demand (read+write) MSHR misses
188 system.cpu.dcache.overall_mshr_misses::cpu.data 1575 # number of overall MSHR misses
189 system.cpu.dcache.overall_mshr_misses::total 1575 # number of overall MSHR misses
190 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30379500 # number of ReadReq MSHR miss cycles
191 system.cpu.dcache.ReadReq_mshr_miss_latency::total 30379500 # number of ReadReq MSHR miss cycles
192 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 65698000 # number of WriteReq MSHR miss cycles
193 system.cpu.dcache.WriteReq_mshr_miss_latency::total 65698000 # number of WriteReq MSHR miss cycles
194 system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 61000 # number of SwapReq MSHR miss cycles
195 system.cpu.dcache.SwapReq_mshr_miss_latency::total 61000 # number of SwapReq MSHR miss cycles
196 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 96077500 # number of demand (read+write) MSHR miss cycles
197 system.cpu.dcache.demand_mshr_miss_latency::total 96077500 # number of demand (read+write) MSHR miss cycles
198 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 96077500 # number of overall MSHR miss cycles
199 system.cpu.dcache.overall_mshr_miss_latency::total 96077500 # number of overall MSHR miss cycles
200 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for ReadReq accesses
201 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses
202 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000057 # mshr miss rate for WriteReq accesses
203 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000057 # mshr miss rate for WriteReq accesses
204 system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.000045 # mshr miss rate for SwapReq accesses
205 system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.000045 # mshr miss rate for SwapReq accesses
206 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000021 # mshr miss rate for demand accesses
207 system.cpu.dcache.demand_mshr_miss_rate::total 0.000021 # mshr miss rate for demand accesses
208 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000021 # mshr miss rate for overall accesses
209 system.cpu.dcache.overall_mshr_miss_rate::total 0.000021 # mshr miss rate for overall accesses
210 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61003.012048 # average ReadReq mshr miss latency
211 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61003.012048 # average ReadReq mshr miss latency
212 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000.928505 # average WriteReq mshr miss latency
213 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000.928505 # average WriteReq mshr miss latency
214 system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 61000 # average SwapReq mshr miss latency
215 system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 61000 # average SwapReq mshr miss latency
216 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61001.587302 # average overall mshr miss latency
217 system.cpu.dcache.demand_avg_mshr_miss_latency::total 61001.587302 # average overall mshr miss latency
218 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61001.587302 # average overall mshr miss latency
219 system.cpu.dcache.overall_avg_mshr_miss_latency::total 61001.587302 # average overall mshr miss latency
220 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
221 system.cpu.icache.tags.replacements 10362 # number of replacements
222 system.cpu.icache.tags.tagsinuse 1591.528232 # Cycle average of tags in use
223 system.cpu.icache.tags.total_refs 193433248 # Total number of references to valid blocks.
224 system.cpu.icache.tags.sampled_refs 12288 # Sample count of references to valid blocks.
225 system.cpu.icache.tags.avg_refs 15741.638021 # Average number of references to valid blocks.
226 system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
227 system.cpu.icache.tags.occ_blocks::cpu.inst 1591.528232 # Average occupied blocks per requestor
228 system.cpu.icache.tags.occ_percent::cpu.inst 0.777113 # Average percentage of cache occupancy
229 system.cpu.icache.tags.occ_percent::total 0.777113 # Average percentage of cache occupancy
230 system.cpu.icache.tags.occ_task_id_blocks::1024 1926 # Occupied blocks per task id
231 system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id
232 system.cpu.icache.tags.age_task_id_blocks_1024::1 50 # Occupied blocks per task id
233 system.cpu.icache.tags.age_task_id_blocks_1024::2 624 # Occupied blocks per task id
234 system.cpu.icache.tags.age_task_id_blocks_1024::3 514 # Occupied blocks per task id
235 system.cpu.icache.tags.age_task_id_blocks_1024::4 687 # Occupied blocks per task id
236 system.cpu.icache.tags.occ_task_id_percent::1024 0.940430 # Percentage of cache occupancy per task id
237 system.cpu.icache.tags.tag_accesses 386903360 # Number of tag accesses
238 system.cpu.icache.tags.data_accesses 386903360 # Number of data accesses
239 system.cpu.icache.ReadReq_hits::cpu.inst 193433248 # number of ReadReq hits
240 system.cpu.icache.ReadReq_hits::total 193433248 # number of ReadReq hits
241 system.cpu.icache.demand_hits::cpu.inst 193433248 # number of demand (read+write) hits
242 system.cpu.icache.demand_hits::total 193433248 # number of demand (read+write) hits
243 system.cpu.icache.overall_hits::cpu.inst 193433248 # number of overall hits
244 system.cpu.icache.overall_hits::total 193433248 # number of overall hits
245 system.cpu.icache.ReadReq_misses::cpu.inst 12288 # number of ReadReq misses
246 system.cpu.icache.ReadReq_misses::total 12288 # number of ReadReq misses
247 system.cpu.icache.demand_misses::cpu.inst 12288 # number of demand (read+write) misses
248 system.cpu.icache.demand_misses::total 12288 # number of demand (read+write) misses
249 system.cpu.icache.overall_misses::cpu.inst 12288 # number of overall misses
250 system.cpu.icache.overall_misses::total 12288 # number of overall misses
251 system.cpu.icache.ReadReq_miss_latency::cpu.inst 336231000 # number of ReadReq miss cycles
252 system.cpu.icache.ReadReq_miss_latency::total 336231000 # number of ReadReq miss cycles
253 system.cpu.icache.demand_miss_latency::cpu.inst 336231000 # number of demand (read+write) miss cycles
254 system.cpu.icache.demand_miss_latency::total 336231000 # number of demand (read+write) miss cycles
255 system.cpu.icache.overall_miss_latency::cpu.inst 336231000 # number of overall miss cycles
256 system.cpu.icache.overall_miss_latency::total 336231000 # number of overall miss cycles
257 system.cpu.icache.ReadReq_accesses::cpu.inst 193445536 # number of ReadReq accesses(hits+misses)
258 system.cpu.icache.ReadReq_accesses::total 193445536 # number of ReadReq accesses(hits+misses)
259 system.cpu.icache.demand_accesses::cpu.inst 193445536 # number of demand (read+write) accesses
260 system.cpu.icache.demand_accesses::total 193445536 # number of demand (read+write) accesses
261 system.cpu.icache.overall_accesses::cpu.inst 193445536 # number of overall (read+write) accesses
262 system.cpu.icache.overall_accesses::total 193445536 # number of overall (read+write) accesses
263 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000064 # miss rate for ReadReq accesses
264 system.cpu.icache.ReadReq_miss_rate::total 0.000064 # miss rate for ReadReq accesses
265 system.cpu.icache.demand_miss_rate::cpu.inst 0.000064 # miss rate for demand accesses
266 system.cpu.icache.demand_miss_rate::total 0.000064 # miss rate for demand accesses
267 system.cpu.icache.overall_miss_rate::cpu.inst 0.000064 # miss rate for overall accesses
268 system.cpu.icache.overall_miss_rate::total 0.000064 # miss rate for overall accesses
269 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27362.548828 # average ReadReq miss latency
270 system.cpu.icache.ReadReq_avg_miss_latency::total 27362.548828 # average ReadReq miss latency
271 system.cpu.icache.demand_avg_miss_latency::cpu.inst 27362.548828 # average overall miss latency
272 system.cpu.icache.demand_avg_miss_latency::total 27362.548828 # average overall miss latency
273 system.cpu.icache.overall_avg_miss_latency::cpu.inst 27362.548828 # average overall miss latency
274 system.cpu.icache.overall_avg_miss_latency::total 27362.548828 # average overall miss latency
275 system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
276 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
277 system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
278 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
279 system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
280 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
281 system.cpu.icache.fast_writes 0 # number of fast writes performed
282 system.cpu.icache.cache_copies 0 # number of cache copies performed
283 system.cpu.icache.writebacks::writebacks 10362 # number of writebacks
284 system.cpu.icache.writebacks::total 10362 # number of writebacks
285 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 12288 # number of ReadReq MSHR misses
286 system.cpu.icache.ReadReq_mshr_misses::total 12288 # number of ReadReq MSHR misses
287 system.cpu.icache.demand_mshr_misses::cpu.inst 12288 # number of demand (read+write) MSHR misses
288 system.cpu.icache.demand_mshr_misses::total 12288 # number of demand (read+write) MSHR misses
289 system.cpu.icache.overall_mshr_misses::cpu.inst 12288 # number of overall MSHR misses
290 system.cpu.icache.overall_mshr_misses::total 12288 # number of overall MSHR misses
291 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 323943000 # number of ReadReq MSHR miss cycles
292 system.cpu.icache.ReadReq_mshr_miss_latency::total 323943000 # number of ReadReq MSHR miss cycles
293 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 323943000 # number of demand (read+write) MSHR miss cycles
294 system.cpu.icache.demand_mshr_miss_latency::total 323943000 # number of demand (read+write) MSHR miss cycles
295 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 323943000 # number of overall MSHR miss cycles
296 system.cpu.icache.overall_mshr_miss_latency::total 323943000 # number of overall MSHR miss cycles
297 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for ReadReq accesses
298 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000064 # mshr miss rate for ReadReq accesses
299 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for demand accesses
300 system.cpu.icache.demand_mshr_miss_rate::total 0.000064 # mshr miss rate for demand accesses
301 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for overall accesses
302 system.cpu.icache.overall_mshr_miss_rate::total 0.000064 # mshr miss rate for overall accesses
303 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26362.548828 # average ReadReq mshr miss latency
304 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26362.548828 # average ReadReq mshr miss latency
305 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26362.548828 # average overall mshr miss latency
306 system.cpu.icache.demand_avg_mshr_miss_latency::total 26362.548828 # average overall mshr miss latency
307 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26362.548828 # average overall mshr miss latency
308 system.cpu.icache.overall_avg_mshr_miss_latency::total 26362.548828 # average overall mshr miss latency
309 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
310 system.cpu.l2cache.tags.replacements 0 # number of replacements
311 system.cpu.l2cache.tags.tagsinuse 2678.246108 # Cycle average of tags in use
312 system.cpu.l2cache.tags.total_refs 19053 # Total number of references to valid blocks.
313 system.cpu.l2cache.tags.sampled_refs 4097 # Sample count of references to valid blocks.
314 system.cpu.l2cache.tags.avg_refs 4.650476 # Average number of references to valid blocks.
315 system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
316 system.cpu.l2cache.tags.occ_blocks::writebacks 0.000456 # Average occupied blocks per requestor
317 system.cpu.l2cache.tags.occ_blocks::cpu.inst 2275.203530 # Average occupied blocks per requestor
318 system.cpu.l2cache.tags.occ_blocks::cpu.data 403.042121 # Average occupied blocks per requestor
319 system.cpu.l2cache.tags.occ_percent::writebacks 0.000000 # Average percentage of cache occupancy
320 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.069434 # Average percentage of cache occupancy
321 system.cpu.l2cache.tags.occ_percent::cpu.data 0.012300 # Average percentage of cache occupancy
322 system.cpu.l2cache.tags.occ_percent::total 0.081734 # Average percentage of cache occupancy
323 system.cpu.l2cache.tags.occ_task_id_blocks::1024 4097 # Occupied blocks per task id
324 system.cpu.l2cache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id
325 system.cpu.l2cache.tags.age_task_id_blocks_1024::1 40 # Occupied blocks per task id
326 system.cpu.l2cache.tags.age_task_id_blocks_1024::2 700 # Occupied blocks per task id
327 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 625 # Occupied blocks per task id
328 system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2688 # Occupied blocks per task id
329 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.125031 # Percentage of cache occupancy per task id
330 system.cpu.l2cache.tags.tag_accesses 198999 # Number of tag accesses
331 system.cpu.l2cache.tags.data_accesses 198999 # Number of data accesses
332 system.cpu.l2cache.WritebackDirty_hits::writebacks 2 # number of WritebackDirty hits
333 system.cpu.l2cache.WritebackDirty_hits::total 2 # number of WritebackDirty hits
334 system.cpu.l2cache.WritebackClean_hits::writebacks 10362 # number of WritebackClean hits
335 system.cpu.l2cache.WritebackClean_hits::total 10362 # number of WritebackClean hits
336 system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 8691 # number of ReadCleanReq hits
337 system.cpu.l2cache.ReadCleanReq_hits::total 8691 # number of ReadCleanReq hits
338 system.cpu.l2cache.demand_hits::cpu.inst 8691 # number of demand (read+write) hits
339 system.cpu.l2cache.demand_hits::total 8691 # number of demand (read+write) hits
340 system.cpu.l2cache.overall_hits::cpu.inst 8691 # number of overall hits
341 system.cpu.l2cache.overall_hits::total 8691 # number of overall hits
342 system.cpu.l2cache.ReadExReq_misses::cpu.data 1078 # number of ReadExReq misses
343 system.cpu.l2cache.ReadExReq_misses::total 1078 # number of ReadExReq misses
344 system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3597 # number of ReadCleanReq misses
345 system.cpu.l2cache.ReadCleanReq_misses::total 3597 # number of ReadCleanReq misses
346 system.cpu.l2cache.ReadSharedReq_misses::cpu.data 498 # number of ReadSharedReq misses
347 system.cpu.l2cache.ReadSharedReq_misses::total 498 # number of ReadSharedReq misses
348 system.cpu.l2cache.demand_misses::cpu.inst 3597 # number of demand (read+write) misses
349 system.cpu.l2cache.demand_misses::cpu.data 1576 # number of demand (read+write) misses
350 system.cpu.l2cache.demand_misses::total 5173 # number of demand (read+write) misses
351 system.cpu.l2cache.overall_misses::cpu.inst 3597 # number of overall misses
352 system.cpu.l2cache.overall_misses::cpu.data 1576 # number of overall misses
353 system.cpu.l2cache.overall_misses::total 5173 # number of overall misses
354 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 64142000 # number of ReadExReq miss cycles
355 system.cpu.l2cache.ReadExReq_miss_latency::total 64142000 # number of ReadExReq miss cycles
356 system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 214049500 # number of ReadCleanReq miss cycles
357 system.cpu.l2cache.ReadCleanReq_miss_latency::total 214049500 # number of ReadCleanReq miss cycles
358 system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 29632000 # number of ReadSharedReq miss cycles
359 system.cpu.l2cache.ReadSharedReq_miss_latency::total 29632000 # number of ReadSharedReq miss cycles
360 system.cpu.l2cache.demand_miss_latency::cpu.inst 214049500 # number of demand (read+write) miss cycles
361 system.cpu.l2cache.demand_miss_latency::cpu.data 93774000 # number of demand (read+write) miss cycles
362 system.cpu.l2cache.demand_miss_latency::total 307823500 # number of demand (read+write) miss cycles
363 system.cpu.l2cache.overall_miss_latency::cpu.inst 214049500 # number of overall miss cycles
364 system.cpu.l2cache.overall_miss_latency::cpu.data 93774000 # number of overall miss cycles
365 system.cpu.l2cache.overall_miss_latency::total 307823500 # number of overall miss cycles
366 system.cpu.l2cache.WritebackDirty_accesses::writebacks 2 # number of WritebackDirty accesses(hits+misses)
367 system.cpu.l2cache.WritebackDirty_accesses::total 2 # number of WritebackDirty accesses(hits+misses)
368 system.cpu.l2cache.WritebackClean_accesses::writebacks 10362 # number of WritebackClean accesses(hits+misses)
369 system.cpu.l2cache.WritebackClean_accesses::total 10362 # number of WritebackClean accesses(hits+misses)
370 system.cpu.l2cache.ReadExReq_accesses::cpu.data 1078 # number of ReadExReq accesses(hits+misses)
371 system.cpu.l2cache.ReadExReq_accesses::total 1078 # number of ReadExReq accesses(hits+misses)
372 system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 12288 # number of ReadCleanReq accesses(hits+misses)
373 system.cpu.l2cache.ReadCleanReq_accesses::total 12288 # number of ReadCleanReq accesses(hits+misses)
374 system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 498 # number of ReadSharedReq accesses(hits+misses)
375 system.cpu.l2cache.ReadSharedReq_accesses::total 498 # number of ReadSharedReq accesses(hits+misses)
376 system.cpu.l2cache.demand_accesses::cpu.inst 12288 # number of demand (read+write) accesses
377 system.cpu.l2cache.demand_accesses::cpu.data 1576 # number of demand (read+write) accesses
378 system.cpu.l2cache.demand_accesses::total 13864 # number of demand (read+write) accesses
379 system.cpu.l2cache.overall_accesses::cpu.inst 12288 # number of overall (read+write) accesses
380 system.cpu.l2cache.overall_accesses::cpu.data 1576 # number of overall (read+write) accesses
381 system.cpu.l2cache.overall_accesses::total 13864 # number of overall (read+write) accesses
382 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
383 system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
384 system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.292725 # miss rate for ReadCleanReq accesses
385 system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.292725 # miss rate for ReadCleanReq accesses
386 system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses
387 system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses
388 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.292725 # miss rate for demand accesses
389 system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
390 system.cpu.l2cache.demand_miss_rate::total 0.373125 # miss rate for demand accesses
391 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.292725 # miss rate for overall accesses
392 system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
393 system.cpu.l2cache.overall_miss_rate::total 0.373125 # miss rate for overall accesses
394 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.927644 # average ReadExReq miss latency
395 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.927644 # average ReadExReq miss latency
396 system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59507.784265 # average ReadCleanReq miss latency
397 system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59507.784265 # average ReadCleanReq miss latency
398 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59502.008032 # average ReadSharedReq miss latency
399 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59502.008032 # average ReadSharedReq miss latency
400 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59507.784265 # average overall miss latency
401 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59501.269036 # average overall miss latency
402 system.cpu.l2cache.demand_avg_miss_latency::total 59505.799343 # average overall miss latency
403 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59507.784265 # average overall miss latency
404 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59501.269036 # average overall miss latency
405 system.cpu.l2cache.overall_avg_miss_latency::total 59505.799343 # average overall miss latency
406 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
407 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
408 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
409 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
410 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
411 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
412 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
413 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
414 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1078 # number of ReadExReq MSHR misses
415 system.cpu.l2cache.ReadExReq_mshr_misses::total 1078 # number of ReadExReq MSHR misses
416 system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3597 # number of ReadCleanReq MSHR misses
417 system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3597 # number of ReadCleanReq MSHR misses
418 system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 498 # number of ReadSharedReq MSHR misses
419 system.cpu.l2cache.ReadSharedReq_mshr_misses::total 498 # number of ReadSharedReq MSHR misses
420 system.cpu.l2cache.demand_mshr_misses::cpu.inst 3597 # number of demand (read+write) MSHR misses
421 system.cpu.l2cache.demand_mshr_misses::cpu.data 1576 # number of demand (read+write) MSHR misses
422 system.cpu.l2cache.demand_mshr_misses::total 5173 # number of demand (read+write) MSHR misses
423 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3597 # number of overall MSHR misses
424 system.cpu.l2cache.overall_mshr_misses::cpu.data 1576 # number of overall MSHR misses
425 system.cpu.l2cache.overall_mshr_misses::total 5173 # number of overall MSHR misses
426 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 53362000 # number of ReadExReq MSHR miss cycles
427 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 53362000 # number of ReadExReq MSHR miss cycles
428 system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 178079500 # number of ReadCleanReq MSHR miss cycles
429 system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 178079500 # number of ReadCleanReq MSHR miss cycles
430 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 24652000 # number of ReadSharedReq MSHR miss cycles
431 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 24652000 # number of ReadSharedReq MSHR miss cycles
432 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 178079500 # number of demand (read+write) MSHR miss cycles
433 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 78014000 # number of demand (read+write) MSHR miss cycles
434 system.cpu.l2cache.demand_mshr_miss_latency::total 256093500 # number of demand (read+write) MSHR miss cycles
435 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 178079500 # number of overall MSHR miss cycles
436 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 78014000 # number of overall MSHR miss cycles
437 system.cpu.l2cache.overall_mshr_miss_latency::total 256093500 # number of overall MSHR miss cycles
438 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
439 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
440 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.292725 # mshr miss rate for ReadCleanReq accesses
441 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.292725 # mshr miss rate for ReadCleanReq accesses
442 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses
443 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses
444 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.292725 # mshr miss rate for demand accesses
445 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
446 system.cpu.l2cache.demand_mshr_miss_rate::total 0.373125 # mshr miss rate for demand accesses
447 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.292725 # mshr miss rate for overall accesses
448 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
449 system.cpu.l2cache.overall_mshr_miss_rate::total 0.373125 # mshr miss rate for overall accesses
450 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.927644 # average ReadExReq mshr miss latency
451 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.927644 # average ReadExReq mshr miss latency
452 system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49507.784265 # average ReadCleanReq mshr miss latency
453 system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49507.784265 # average ReadCleanReq mshr miss latency
454 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49502.008032 # average ReadSharedReq mshr miss latency
455 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49502.008032 # average ReadSharedReq mshr miss latency
456 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49507.784265 # average overall mshr miss latency
457 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49501.269036 # average overall mshr miss latency
458 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49505.799343 # average overall mshr miss latency
459 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49507.784265 # average overall mshr miss latency
460 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49501.269036 # average overall mshr miss latency
461 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49505.799343 # average overall mshr miss latency
462 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
463 system.cpu.toL2Bus.snoop_filter.tot_requests 24228 # Total number of requests made to the snoop filter.
464 system.cpu.toL2Bus.snoop_filter.hit_single_requests 10365 # Number of requests hitting in the snoop filter with a single holder of the requested data.
465 system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
466 system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
467 system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
468 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
469 system.cpu.toL2Bus.trans_dist::ReadResp 12786 # Transaction distribution
470 system.cpu.toL2Bus.trans_dist::WritebackDirty 2 # Transaction distribution
471 system.cpu.toL2Bus.trans_dist::WritebackClean 10362 # Transaction distribution
472 system.cpu.toL2Bus.trans_dist::ReadExReq 1078 # Transaction distribution
473 system.cpu.toL2Bus.trans_dist::ReadExResp 1078 # Transaction distribution
474 system.cpu.toL2Bus.trans_dist::ReadCleanReq 12288 # Transaction distribution
475 system.cpu.toL2Bus.trans_dist::ReadSharedReq 498 # Transaction distribution
476 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 34938 # Packet count per connected master and slave (bytes)
477 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3154 # Packet count per connected master and slave (bytes)
478 system.cpu.toL2Bus.pkt_count::total 38092 # Packet count per connected master and slave (bytes)
479 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1449600 # Cumulative packet size per connected master and slave (bytes)
480 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 100992 # Cumulative packet size per connected master and slave (bytes)
481 system.cpu.toL2Bus.pkt_size::total 1550592 # Cumulative packet size per connected master and slave (bytes)
482 system.cpu.toL2Bus.snoops 0 # Total snoops (count)
483 system.cpu.toL2Bus.snoop_fanout::samples 13864 # Request fanout histogram
484 system.cpu.toL2Bus.snoop_fanout::mean 0.000072 # Request fanout histogram
485 system.cpu.toL2Bus.snoop_fanout::stdev 0.008493 # Request fanout histogram
486 system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
487 system.cpu.toL2Bus.snoop_fanout::0 13863 99.99% 99.99% # Request fanout histogram
488 system.cpu.toL2Bus.snoop_fanout::1 1 0.01% 100.00% # Request fanout histogram
489 system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
490 system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
491 system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
492 system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
493 system.cpu.toL2Bus.snoop_fanout::total 13864 # Request fanout histogram
494 system.cpu.toL2Bus.reqLayer0.occupancy 22478000 # Layer occupancy (ticks)
495 system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
496 system.cpu.toL2Bus.respLayer0.occupancy 18432000 # Layer occupancy (ticks)
497 system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
498 system.cpu.toL2Bus.respLayer1.occupancy 2364000 # Layer occupancy (ticks)
499 system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
500 system.membus.trans_dist::ReadResp 4095 # Transaction distribution
501 system.membus.trans_dist::ReadExReq 1078 # Transaction distribution
502 system.membus.trans_dist::ReadExResp 1078 # Transaction distribution
503 system.membus.trans_dist::ReadSharedReq 4095 # Transaction distribution
504 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10346 # Packet count per connected master and slave (bytes)
505 system.membus.pkt_count::total 10346 # Packet count per connected master and slave (bytes)
506 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 331072 # Cumulative packet size per connected master and slave (bytes)
507 system.membus.pkt_size::total 331072 # Cumulative packet size per connected master and slave (bytes)
508 system.membus.snoops 0 # Total snoops (count)
509 system.membus.snoop_fanout::samples 5173 # Request fanout histogram
510 system.membus.snoop_fanout::mean 0 # Request fanout histogram
511 system.membus.snoop_fanout::stdev 0 # Request fanout histogram
512 system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
513 system.membus.snoop_fanout::0 5173 100.00% 100.00% # Request fanout histogram
514 system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
515 system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
516 system.membus.snoop_fanout::min_value 0 # Request fanout histogram
517 system.membus.snoop_fanout::max_value 0 # Request fanout histogram
518 system.membus.snoop_fanout::total 5173 # Request fanout histogram
519 system.membus.reqLayer0.occupancy 5203000 # Layer occupancy (ticks)
520 system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
521 system.membus.respLayer1.occupancy 25865000 # Layer occupancy (ticks)
522 system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
524 ---------- End Simulation Statistics ----------
projects / gem5.git / blob