2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.250992 # Number of seconds simulated
4 sim_ticks 250991873500 # Number of ticks simulated
5 final_tick 250991873500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 1067110 # Simulator instruction rate (inst/s)
8 host_op_rate 1788574 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 2027966293 # Simulator tick rate (ticks/s)
10 host_mem_usage 298984 # Number of bytes of host memory used
11 host_seconds 123.77 # Real time elapsed on the host
12 sim_insts 132071193 # Number of instructions simulated
13 sim_ops 221363385 # Number of ops (including micro ops) simulated
14 system.voltage_domain.voltage 1 # Voltage in Volts
15 system.clk_domain.clock 1000 # Clock period in ticks
16 system.physmem.pwrStateResidencyTicks::UNDEFINED 250991873500 # Cumulative time (in ticks) in various power states
17 system.physmem.bytes_read::cpu.inst 181760 # Number of bytes read from this memory
18 system.physmem.bytes_read::cpu.data 121280 # Number of bytes read from this memory
19 system.physmem.bytes_read::total 303040 # Number of bytes read from this memory
20 system.physmem.bytes_inst_read::cpu.inst 181760 # Number of instructions bytes read from this memory
21 system.physmem.bytes_inst_read::total 181760 # Number of instructions bytes read from this memory
22 system.physmem.num_reads::cpu.inst 2840 # Number of read requests responded to by this memory
23 system.physmem.num_reads::cpu.data 1895 # Number of read requests responded to by this memory
24 system.physmem.num_reads::total 4735 # Number of read requests responded to by this memory
25 system.physmem.bw_read::cpu.inst 724167 # Total read bandwidth from this memory (bytes/s)
26 system.physmem.bw_read::cpu.data 483203 # Total read bandwidth from this memory (bytes/s)
27 system.physmem.bw_read::total 1207370 # Total read bandwidth from this memory (bytes/s)
28 system.physmem.bw_inst_read::cpu.inst 724167 # Instruction read bandwidth from this memory (bytes/s)
29 system.physmem.bw_inst_read::total 724167 # Instruction read bandwidth from this memory (bytes/s)
30 system.physmem.bw_total::cpu.inst 724167 # Total bandwidth to/from this memory (bytes/s)
31 system.physmem.bw_total::cpu.data 483203 # Total bandwidth to/from this memory (bytes/s)
32 system.physmem.bw_total::total 1207370 # Total bandwidth to/from this memory (bytes/s)
33 system.pwrStateResidencyTicks::UNDEFINED 250991873500 # Cumulative time (in ticks) in various power states
34 system.cpu_clk_domain.clock 500 # Clock period in ticks
35 system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 250991873500 # Cumulative time (in ticks) in various power states
36 system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
37 system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 250991873500 # Cumulative time (in ticks) in various power states
38 system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 250991873500 # Cumulative time (in ticks) in various power states
39 system.cpu.workload.numSyscalls 400 # Number of system calls
40 system.cpu.pwrStateResidencyTicks::ON 250991873500 # Cumulative time (in ticks) in various power states
41 system.cpu.numCycles 501983747 # number of cpu cycles simulated
42 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
43 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
44 system.cpu.committedInsts 132071193 # Number of instructions committed
45 system.cpu.committedOps 221363385 # Number of ops (including micro ops) committed
46 system.cpu.num_int_alu_accesses 219019986 # Number of integer alu accesses
47 system.cpu.num_fp_alu_accesses 2162459 # Number of float alu accesses
48 system.cpu.num_func_calls 1595632 # number of times a function call or return occured
49 system.cpu.num_conditional_control_insts 8268466 # number of instructions that are conditional controls
50 system.cpu.num_int_insts 219019986 # number of integer instructions
51 system.cpu.num_fp_insts 2162459 # number of float instructions
52 system.cpu.num_int_register_reads 519996939 # number of times the integer registers were read
53 system.cpu.num_int_register_writes 201355989 # number of times the integer registers were written
54 system.cpu.num_fp_register_reads 3037165 # number of times the floating registers were read
55 system.cpu.num_fp_register_writes 1831403 # number of times the floating registers were written
56 system.cpu.num_cc_register_reads 96962463 # number of times the CC registers were read
57 system.cpu.num_cc_register_writes 56242058 # number of times the CC registers were written
58 system.cpu.num_mem_refs 77165304 # number of memory refs
59 system.cpu.num_load_insts 56649587 # Number of load instructions
60 system.cpu.num_store_insts 20515717 # Number of store instructions
61 system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
62 system.cpu.num_busy_cycles 501983746.998000 # Number of busy cycles
63 system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
64 system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
65 system.cpu.Branches 12326938 # Number of branches fetched
66 system.cpu.op_class::No_OpClass 1176721 0.53% 0.53% # Class of executed instruction
67 system.cpu.op_class::IntAlu 134111833 60.58% 61.12% # Class of executed instruction
68 system.cpu.op_class::IntMult 772953 0.35% 61.47% # Class of executed instruction
69 system.cpu.op_class::IntDiv 7031501 3.18% 64.64% # Class of executed instruction
70 system.cpu.op_class::FloatAdd 1105073 0.50% 65.14% # Class of executed instruction
71 system.cpu.op_class::FloatCmp 0 0.00% 65.14% # Class of executed instruction
72 system.cpu.op_class::FloatCvt 0 0.00% 65.14% # Class of executed instruction
73 system.cpu.op_class::FloatMult 0 0.00% 65.14% # Class of executed instruction
74 system.cpu.op_class::FloatMultAcc 0 0.00% 65.14% # Class of executed instruction
75 system.cpu.op_class::FloatDiv 0 0.00% 65.14% # Class of executed instruction
76 system.cpu.op_class::FloatMisc 0 0.00% 65.14% # Class of executed instruction
77 system.cpu.op_class::FloatSqrt 0 0.00% 65.14% # Class of executed instruction
78 system.cpu.op_class::SimdAdd 0 0.00% 65.14% # Class of executed instruction
79 system.cpu.op_class::SimdAddAcc 0 0.00% 65.14% # Class of executed instruction
80 system.cpu.op_class::SimdAlu 0 0.00% 65.14% # Class of executed instruction
81 system.cpu.op_class::SimdCmp 0 0.00% 65.14% # Class of executed instruction
82 system.cpu.op_class::SimdCvt 0 0.00% 65.14% # Class of executed instruction
83 system.cpu.op_class::SimdMisc 0 0.00% 65.14% # Class of executed instruction
84 system.cpu.op_class::SimdMult 0 0.00% 65.14% # Class of executed instruction
85 system.cpu.op_class::SimdMultAcc 0 0.00% 65.14% # Class of executed instruction
86 system.cpu.op_class::SimdShift 0 0.00% 65.14% # Class of executed instruction
87 system.cpu.op_class::SimdShiftAcc 0 0.00% 65.14% # Class of executed instruction
88 system.cpu.op_class::SimdSqrt 0 0.00% 65.14% # Class of executed instruction
89 system.cpu.op_class::SimdFloatAdd 0 0.00% 65.14% # Class of executed instruction
90 system.cpu.op_class::SimdFloatAlu 0 0.00% 65.14% # Class of executed instruction
91 system.cpu.op_class::SimdFloatCmp 0 0.00% 65.14% # Class of executed instruction
92 system.cpu.op_class::SimdFloatCvt 0 0.00% 65.14% # Class of executed instruction
93 system.cpu.op_class::SimdFloatDiv 0 0.00% 65.14% # Class of executed instruction
94 system.cpu.op_class::SimdFloatMisc 0 0.00% 65.14% # Class of executed instruction
95 system.cpu.op_class::SimdFloatMult 0 0.00% 65.14% # Class of executed instruction
96 system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.14% # Class of executed instruction
97 system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.14% # Class of executed instruction
98 system.cpu.op_class::MemRead 55945136 25.27% 90.41% # Class of executed instruction
99 system.cpu.op_class::MemWrite 20410230 9.22% 99.63% # Class of executed instruction
100 system.cpu.op_class::FloatMemRead 704451 0.32% 99.95% # Class of executed instruction
101 system.cpu.op_class::FloatMemWrite 105487 0.05% 100.00% # Class of executed instruction
102 system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
103 system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
104 system.cpu.op_class::total 221363385 # Class of executed instruction
105 system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 250991873500 # Cumulative time (in ticks) in various power states
106 system.cpu.dcache.tags.replacements 41 # number of replacements
107 system.cpu.dcache.tags.tagsinuse 1363.408611 # Cycle average of tags in use
108 system.cpu.dcache.tags.total_refs 77195831 # Total number of references to valid blocks.
109 system.cpu.dcache.tags.sampled_refs 1905 # Sample count of references to valid blocks.
110 system.cpu.dcache.tags.avg_refs 40522.745932 # Average number of references to valid blocks.
111 system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
112 system.cpu.dcache.tags.occ_blocks::cpu.data 1363.408611 # Average occupied blocks per requestor
113 system.cpu.dcache.tags.occ_percent::cpu.data 0.332863 # Average percentage of cache occupancy
114 system.cpu.dcache.tags.occ_percent::total 0.332863 # Average percentage of cache occupancy
115 system.cpu.dcache.tags.occ_task_id_blocks::1024 1864 # Occupied blocks per task id
116 system.cpu.dcache.tags.age_task_id_blocks_1024::0 7 # Occupied blocks per task id
117 system.cpu.dcache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id
118 system.cpu.dcache.tags.age_task_id_blocks_1024::2 43 # Occupied blocks per task id
119 system.cpu.dcache.tags.age_task_id_blocks_1024::3 472 # Occupied blocks per task id
120 system.cpu.dcache.tags.age_task_id_blocks_1024::4 1328 # Occupied blocks per task id
121 system.cpu.dcache.tags.occ_task_id_percent::1024 0.455078 # Percentage of cache occupancy per task id
122 system.cpu.dcache.tags.tag_accesses 154397377 # Number of tag accesses
123 system.cpu.dcache.tags.data_accesses 154397377 # Number of data accesses
124 system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 250991873500 # Cumulative time (in ticks) in various power states
125 system.cpu.dcache.ReadReq_hits::cpu.data 56681678 # number of ReadReq hits
126 system.cpu.dcache.ReadReq_hits::total 56681678 # number of ReadReq hits
127 system.cpu.dcache.WriteReq_hits::cpu.data 20514153 # number of WriteReq hits
128 system.cpu.dcache.WriteReq_hits::total 20514153 # number of WriteReq hits
129 system.cpu.dcache.demand_hits::cpu.data 77195831 # number of demand (read+write) hits
130 system.cpu.dcache.demand_hits::total 77195831 # number of demand (read+write) hits
131 system.cpu.dcache.overall_hits::cpu.data 77195831 # number of overall hits
132 system.cpu.dcache.overall_hits::total 77195831 # number of overall hits
133 system.cpu.dcache.ReadReq_misses::cpu.data 327 # number of ReadReq misses
134 system.cpu.dcache.ReadReq_misses::total 327 # number of ReadReq misses
135 system.cpu.dcache.WriteReq_misses::cpu.data 1578 # number of WriteReq misses
136 system.cpu.dcache.WriteReq_misses::total 1578 # number of WriteReq misses
137 system.cpu.dcache.demand_misses::cpu.data 1905 # number of demand (read+write) misses
138 system.cpu.dcache.demand_misses::total 1905 # number of demand (read+write) misses
139 system.cpu.dcache.overall_misses::cpu.data 1905 # number of overall misses
140 system.cpu.dcache.overall_misses::total 1905 # number of overall misses
141 system.cpu.dcache.ReadReq_miss_latency::cpu.data 20253500 # number of ReadReq miss cycles
142 system.cpu.dcache.ReadReq_miss_latency::total 20253500 # number of ReadReq miss cycles
143 system.cpu.dcache.WriteReq_miss_latency::cpu.data 99266000 # number of WriteReq miss cycles
144 system.cpu.dcache.WriteReq_miss_latency::total 99266000 # number of WriteReq miss cycles
145 system.cpu.dcache.demand_miss_latency::cpu.data 119519500 # number of demand (read+write) miss cycles
146 system.cpu.dcache.demand_miss_latency::total 119519500 # number of demand (read+write) miss cycles
147 system.cpu.dcache.overall_miss_latency::cpu.data 119519500 # number of overall miss cycles
148 system.cpu.dcache.overall_miss_latency::total 119519500 # number of overall miss cycles
149 system.cpu.dcache.ReadReq_accesses::cpu.data 56682005 # number of ReadReq accesses(hits+misses)
150 system.cpu.dcache.ReadReq_accesses::total 56682005 # number of ReadReq accesses(hits+misses)
151 system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses)
152 system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses)
153 system.cpu.dcache.demand_accesses::cpu.data 77197736 # number of demand (read+write) accesses
154 system.cpu.dcache.demand_accesses::total 77197736 # number of demand (read+write) accesses
155 system.cpu.dcache.overall_accesses::cpu.data 77197736 # number of overall (read+write) accesses
156 system.cpu.dcache.overall_accesses::total 77197736 # number of overall (read+write) accesses
157 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000006 # miss rate for ReadReq accesses
158 system.cpu.dcache.ReadReq_miss_rate::total 0.000006 # miss rate for ReadReq accesses
159 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000077 # miss rate for WriteReq accesses
160 system.cpu.dcache.WriteReq_miss_rate::total 0.000077 # miss rate for WriteReq accesses
161 system.cpu.dcache.demand_miss_rate::cpu.data 0.000025 # miss rate for demand accesses
162 system.cpu.dcache.demand_miss_rate::total 0.000025 # miss rate for demand accesses
163 system.cpu.dcache.overall_miss_rate::cpu.data 0.000025 # miss rate for overall accesses
164 system.cpu.dcache.overall_miss_rate::total 0.000025 # miss rate for overall accesses
165 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 61937.308869 # average ReadReq miss latency
166 system.cpu.dcache.ReadReq_avg_miss_latency::total 61937.308869 # average ReadReq miss latency
167 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62906.210393 # average WriteReq miss latency
168 system.cpu.dcache.WriteReq_avg_miss_latency::total 62906.210393 # average WriteReq miss latency
169 system.cpu.dcache.demand_avg_miss_latency::cpu.data 62739.895013 # average overall miss latency
170 system.cpu.dcache.demand_avg_miss_latency::total 62739.895013 # average overall miss latency
171 system.cpu.dcache.overall_avg_miss_latency::cpu.data 62739.895013 # average overall miss latency
172 system.cpu.dcache.overall_avg_miss_latency::total 62739.895013 # average overall miss latency
173 system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
174 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
175 system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
176 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
177 system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
178 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
179 system.cpu.dcache.writebacks::writebacks 7 # number of writebacks
180 system.cpu.dcache.writebacks::total 7 # number of writebacks
181 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 327 # number of ReadReq MSHR misses
182 system.cpu.dcache.ReadReq_mshr_misses::total 327 # number of ReadReq MSHR misses
183 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1578 # number of WriteReq MSHR misses
184 system.cpu.dcache.WriteReq_mshr_misses::total 1578 # number of WriteReq MSHR misses
185 system.cpu.dcache.demand_mshr_misses::cpu.data 1905 # number of demand (read+write) MSHR misses
186 system.cpu.dcache.demand_mshr_misses::total 1905 # number of demand (read+write) MSHR misses
187 system.cpu.dcache.overall_mshr_misses::cpu.data 1905 # number of overall MSHR misses
188 system.cpu.dcache.overall_mshr_misses::total 1905 # number of overall MSHR misses
189 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 19926500 # number of ReadReq MSHR miss cycles
190 system.cpu.dcache.ReadReq_mshr_miss_latency::total 19926500 # number of ReadReq MSHR miss cycles
191 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 97688000 # number of WriteReq MSHR miss cycles
192 system.cpu.dcache.WriteReq_mshr_miss_latency::total 97688000 # number of WriteReq MSHR miss cycles
193 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 117614500 # number of demand (read+write) MSHR miss cycles
194 system.cpu.dcache.demand_mshr_miss_latency::total 117614500 # number of demand (read+write) MSHR miss cycles
195 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 117614500 # number of overall MSHR miss cycles
196 system.cpu.dcache.overall_mshr_miss_latency::total 117614500 # number of overall MSHR miss cycles
197 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000006 # mshr miss rate for ReadReq accesses
198 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000006 # mshr miss rate for ReadReq accesses
199 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000077 # mshr miss rate for WriteReq accesses
200 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000077 # mshr miss rate for WriteReq accesses
201 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses
202 system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses
203 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses
204 system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses
205 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 60937.308869 # average ReadReq mshr miss latency
206 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60937.308869 # average ReadReq mshr miss latency
207 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61906.210393 # average WriteReq mshr miss latency
208 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61906.210393 # average WriteReq mshr miss latency
209 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61739.895013 # average overall mshr miss latency
210 system.cpu.dcache.demand_avg_mshr_miss_latency::total 61739.895013 # average overall mshr miss latency
211 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61739.895013 # average overall mshr miss latency
212 system.cpu.dcache.overall_avg_mshr_miss_latency::total 61739.895013 # average overall mshr miss latency
213 system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 250991873500 # Cumulative time (in ticks) in various power states
214 system.cpu.icache.tags.replacements 2836 # number of replacements
215 system.cpu.icache.tags.tagsinuse 1455.237724 # Cycle average of tags in use
216 system.cpu.icache.tags.total_refs 173489673 # Total number of references to valid blocks.
217 system.cpu.icache.tags.sampled_refs 4694 # Sample count of references to valid blocks.
218 system.cpu.icache.tags.avg_refs 36959.879207 # Average number of references to valid blocks.
219 system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
220 system.cpu.icache.tags.occ_blocks::cpu.inst 1455.237724 # Average occupied blocks per requestor
221 system.cpu.icache.tags.occ_percent::cpu.inst 0.710565 # Average percentage of cache occupancy
222 system.cpu.icache.tags.occ_percent::total 0.710565 # Average percentage of cache occupancy
223 system.cpu.icache.tags.occ_task_id_blocks::1024 1858 # Occupied blocks per task id
224 system.cpu.icache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id
225 system.cpu.icache.tags.age_task_id_blocks_1024::1 60 # Occupied blocks per task id
226 system.cpu.icache.tags.age_task_id_blocks_1024::2 470 # Occupied blocks per task id
227 system.cpu.icache.tags.age_task_id_blocks_1024::3 422 # Occupied blocks per task id
228 system.cpu.icache.tags.age_task_id_blocks_1024::4 869 # Occupied blocks per task id
229 system.cpu.icache.tags.occ_task_id_percent::1024 0.907227 # Percentage of cache occupancy per task id
230 system.cpu.icache.tags.tag_accesses 346993428 # Number of tag accesses
231 system.cpu.icache.tags.data_accesses 346993428 # Number of data accesses
232 system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 250991873500 # Cumulative time (in ticks) in various power states
233 system.cpu.icache.ReadReq_hits::cpu.inst 173489673 # number of ReadReq hits
234 system.cpu.icache.ReadReq_hits::total 173489673 # number of ReadReq hits
235 system.cpu.icache.demand_hits::cpu.inst 173489673 # number of demand (read+write) hits
236 system.cpu.icache.demand_hits::total 173489673 # number of demand (read+write) hits
237 system.cpu.icache.overall_hits::cpu.inst 173489673 # number of overall hits
238 system.cpu.icache.overall_hits::total 173489673 # number of overall hits
239 system.cpu.icache.ReadReq_misses::cpu.inst 4694 # number of ReadReq misses
240 system.cpu.icache.ReadReq_misses::total 4694 # number of ReadReq misses
241 system.cpu.icache.demand_misses::cpu.inst 4694 # number of demand (read+write) misses
242 system.cpu.icache.demand_misses::total 4694 # number of demand (read+write) misses
243 system.cpu.icache.overall_misses::cpu.inst 4694 # number of overall misses
244 system.cpu.icache.overall_misses::total 4694 # number of overall misses
245 system.cpu.icache.ReadReq_miss_latency::cpu.inst 203072500 # number of ReadReq miss cycles
246 system.cpu.icache.ReadReq_miss_latency::total 203072500 # number of ReadReq miss cycles
247 system.cpu.icache.demand_miss_latency::cpu.inst 203072500 # number of demand (read+write) miss cycles
248 system.cpu.icache.demand_miss_latency::total 203072500 # number of demand (read+write) miss cycles
249 system.cpu.icache.overall_miss_latency::cpu.inst 203072500 # number of overall miss cycles
250 system.cpu.icache.overall_miss_latency::total 203072500 # number of overall miss cycles
251 system.cpu.icache.ReadReq_accesses::cpu.inst 173494367 # number of ReadReq accesses(hits+misses)
252 system.cpu.icache.ReadReq_accesses::total 173494367 # number of ReadReq accesses(hits+misses)
253 system.cpu.icache.demand_accesses::cpu.inst 173494367 # number of demand (read+write) accesses
254 system.cpu.icache.demand_accesses::total 173494367 # number of demand (read+write) accesses
255 system.cpu.icache.overall_accesses::cpu.inst 173494367 # number of overall (read+write) accesses
256 system.cpu.icache.overall_accesses::total 173494367 # number of overall (read+write) accesses
257 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000027 # miss rate for ReadReq accesses
258 system.cpu.icache.ReadReq_miss_rate::total 0.000027 # miss rate for ReadReq accesses
259 system.cpu.icache.demand_miss_rate::cpu.inst 0.000027 # miss rate for demand accesses
260 system.cpu.icache.demand_miss_rate::total 0.000027 # miss rate for demand accesses
261 system.cpu.icache.overall_miss_rate::cpu.inst 0.000027 # miss rate for overall accesses
262 system.cpu.icache.overall_miss_rate::total 0.000027 # miss rate for overall accesses
263 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 43262.143161 # average ReadReq miss latency
264 system.cpu.icache.ReadReq_avg_miss_latency::total 43262.143161 # average ReadReq miss latency
265 system.cpu.icache.demand_avg_miss_latency::cpu.inst 43262.143161 # average overall miss latency
266 system.cpu.icache.demand_avg_miss_latency::total 43262.143161 # average overall miss latency
267 system.cpu.icache.overall_avg_miss_latency::cpu.inst 43262.143161 # average overall miss latency
268 system.cpu.icache.overall_avg_miss_latency::total 43262.143161 # average overall miss latency
269 system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
270 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
271 system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
272 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
273 system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
274 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
275 system.cpu.icache.writebacks::writebacks 2836 # number of writebacks
276 system.cpu.icache.writebacks::total 2836 # number of writebacks
277 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4694 # number of ReadReq MSHR misses
278 system.cpu.icache.ReadReq_mshr_misses::total 4694 # number of ReadReq MSHR misses
279 system.cpu.icache.demand_mshr_misses::cpu.inst 4694 # number of demand (read+write) MSHR misses
280 system.cpu.icache.demand_mshr_misses::total 4694 # number of demand (read+write) MSHR misses
281 system.cpu.icache.overall_mshr_misses::cpu.inst 4694 # number of overall MSHR misses
282 system.cpu.icache.overall_mshr_misses::total 4694 # number of overall MSHR misses
283 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 198378500 # number of ReadReq MSHR miss cycles
284 system.cpu.icache.ReadReq_mshr_miss_latency::total 198378500 # number of ReadReq MSHR miss cycles
285 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 198378500 # number of demand (read+write) MSHR miss cycles
286 system.cpu.icache.demand_mshr_miss_latency::total 198378500 # number of demand (read+write) MSHR miss cycles
287 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 198378500 # number of overall MSHR miss cycles
288 system.cpu.icache.overall_mshr_miss_latency::total 198378500 # number of overall MSHR miss cycles
289 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for ReadReq accesses
290 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000027 # mshr miss rate for ReadReq accesses
291 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for demand accesses
292 system.cpu.icache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses
293 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for overall accesses
294 system.cpu.icache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses
295 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 42262.143161 # average ReadReq mshr miss latency
296 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 42262.143161 # average ReadReq mshr miss latency
297 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 42262.143161 # average overall mshr miss latency
298 system.cpu.icache.demand_avg_mshr_miss_latency::total 42262.143161 # average overall mshr miss latency
299 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 42262.143161 # average overall mshr miss latency
300 system.cpu.icache.overall_avg_mshr_miss_latency::total 42262.143161 # average overall mshr miss latency
301 system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 250991873500 # Cumulative time (in ticks) in various power states
302 system.cpu.l2cache.tags.replacements 0 # number of replacements
303 system.cpu.l2cache.tags.tagsinuse 3195.628328 # Cycle average of tags in use
304 system.cpu.l2cache.tags.total_refs 4741 # Total number of references to valid blocks.
305 system.cpu.l2cache.tags.sampled_refs 4735 # Sample count of references to valid blocks.
306 system.cpu.l2cache.tags.avg_refs 1.001267 # Average number of references to valid blocks.
307 system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
308 system.cpu.l2cache.tags.occ_blocks::cpu.inst 1829.901516 # Average occupied blocks per requestor
309 system.cpu.l2cache.tags.occ_blocks::cpu.data 1365.726812 # Average occupied blocks per requestor
310 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.055844 # Average percentage of cache occupancy
311 system.cpu.l2cache.tags.occ_percent::cpu.data 0.041679 # Average percentage of cache occupancy
312 system.cpu.l2cache.tags.occ_percent::total 0.097523 # Average percentage of cache occupancy
313 system.cpu.l2cache.tags.occ_task_id_blocks::1024 4735 # Occupied blocks per task id
314 system.cpu.l2cache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id
315 system.cpu.l2cache.tags.age_task_id_blocks_1024::1 39 # Occupied blocks per task id
316 system.cpu.l2cache.tags.age_task_id_blocks_1024::2 512 # Occupied blocks per task id
317 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 947 # Occupied blocks per task id
318 system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3200 # Occupied blocks per task id
319 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.144501 # Percentage of cache occupancy per task id
320 system.cpu.l2cache.tags.tag_accesses 80543 # Number of tag accesses
321 system.cpu.l2cache.tags.data_accesses 80543 # Number of data accesses
322 system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 250991873500 # Cumulative time (in ticks) in various power states
323 system.cpu.l2cache.WritebackDirty_hits::writebacks 7 # number of WritebackDirty hits
324 system.cpu.l2cache.WritebackDirty_hits::total 7 # number of WritebackDirty hits
325 system.cpu.l2cache.WritebackClean_hits::writebacks 2836 # number of WritebackClean hits
326 system.cpu.l2cache.WritebackClean_hits::total 2836 # number of WritebackClean hits
327 system.cpu.l2cache.ReadExReq_hits::cpu.data 3 # number of ReadExReq hits
328 system.cpu.l2cache.ReadExReq_hits::total 3 # number of ReadExReq hits
329 system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1854 # number of ReadCleanReq hits
330 system.cpu.l2cache.ReadCleanReq_hits::total 1854 # number of ReadCleanReq hits
331 system.cpu.l2cache.ReadSharedReq_hits::cpu.data 7 # number of ReadSharedReq hits
332 system.cpu.l2cache.ReadSharedReq_hits::total 7 # number of ReadSharedReq hits
333 system.cpu.l2cache.demand_hits::cpu.inst 1854 # number of demand (read+write) hits
334 system.cpu.l2cache.demand_hits::cpu.data 10 # number of demand (read+write) hits
335 system.cpu.l2cache.demand_hits::total 1864 # number of demand (read+write) hits
336 system.cpu.l2cache.overall_hits::cpu.inst 1854 # number of overall hits
337 system.cpu.l2cache.overall_hits::cpu.data 10 # number of overall hits
338 system.cpu.l2cache.overall_hits::total 1864 # number of overall hits
339 system.cpu.l2cache.ReadExReq_misses::cpu.data 1575 # number of ReadExReq misses
340 system.cpu.l2cache.ReadExReq_misses::total 1575 # number of ReadExReq misses
341 system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2840 # number of ReadCleanReq misses
342 system.cpu.l2cache.ReadCleanReq_misses::total 2840 # number of ReadCleanReq misses
343 system.cpu.l2cache.ReadSharedReq_misses::cpu.data 320 # number of ReadSharedReq misses
344 system.cpu.l2cache.ReadSharedReq_misses::total 320 # number of ReadSharedReq misses
345 system.cpu.l2cache.demand_misses::cpu.inst 2840 # number of demand (read+write) misses
346 system.cpu.l2cache.demand_misses::cpu.data 1895 # number of demand (read+write) misses
347 system.cpu.l2cache.demand_misses::total 4735 # number of demand (read+write) misses
348 system.cpu.l2cache.overall_misses::cpu.inst 2840 # number of overall misses
349 system.cpu.l2cache.overall_misses::cpu.data 1895 # number of overall misses
350 system.cpu.l2cache.overall_misses::total 4735 # number of overall misses
351 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 95288500 # number of ReadExReq miss cycles
352 system.cpu.l2cache.ReadExReq_miss_latency::total 95288500 # number of ReadExReq miss cycles
353 system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 171853000 # number of ReadCleanReq miss cycles
354 system.cpu.l2cache.ReadCleanReq_miss_latency::total 171853000 # number of ReadCleanReq miss cycles
355 system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 19362000 # number of ReadSharedReq miss cycles
356 system.cpu.l2cache.ReadSharedReq_miss_latency::total 19362000 # number of ReadSharedReq miss cycles
357 system.cpu.l2cache.demand_miss_latency::cpu.inst 171853000 # number of demand (read+write) miss cycles
358 system.cpu.l2cache.demand_miss_latency::cpu.data 114650500 # number of demand (read+write) miss cycles
359 system.cpu.l2cache.demand_miss_latency::total 286503500 # number of demand (read+write) miss cycles
360 system.cpu.l2cache.overall_miss_latency::cpu.inst 171853000 # number of overall miss cycles
361 system.cpu.l2cache.overall_miss_latency::cpu.data 114650500 # number of overall miss cycles
362 system.cpu.l2cache.overall_miss_latency::total 286503500 # number of overall miss cycles
363 system.cpu.l2cache.WritebackDirty_accesses::writebacks 7 # number of WritebackDirty accesses(hits+misses)
364 system.cpu.l2cache.WritebackDirty_accesses::total 7 # number of WritebackDirty accesses(hits+misses)
365 system.cpu.l2cache.WritebackClean_accesses::writebacks 2836 # number of WritebackClean accesses(hits+misses)
366 system.cpu.l2cache.WritebackClean_accesses::total 2836 # number of WritebackClean accesses(hits+misses)
367 system.cpu.l2cache.ReadExReq_accesses::cpu.data 1578 # number of ReadExReq accesses(hits+misses)
368 system.cpu.l2cache.ReadExReq_accesses::total 1578 # number of ReadExReq accesses(hits+misses)
369 system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 4694 # number of ReadCleanReq accesses(hits+misses)
370 system.cpu.l2cache.ReadCleanReq_accesses::total 4694 # number of ReadCleanReq accesses(hits+misses)
371 system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 327 # number of ReadSharedReq accesses(hits+misses)
372 system.cpu.l2cache.ReadSharedReq_accesses::total 327 # number of ReadSharedReq accesses(hits+misses)
373 system.cpu.l2cache.demand_accesses::cpu.inst 4694 # number of demand (read+write) accesses
374 system.cpu.l2cache.demand_accesses::cpu.data 1905 # number of demand (read+write) accesses
375 system.cpu.l2cache.demand_accesses::total 6599 # number of demand (read+write) accesses
376 system.cpu.l2cache.overall_accesses::cpu.inst 4694 # number of overall (read+write) accesses
377 system.cpu.l2cache.overall_accesses::cpu.data 1905 # number of overall (read+write) accesses
378 system.cpu.l2cache.overall_accesses::total 6599 # number of overall (read+write) accesses
379 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.998099 # miss rate for ReadExReq accesses
380 system.cpu.l2cache.ReadExReq_miss_rate::total 0.998099 # miss rate for ReadExReq accesses
381 system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.605028 # miss rate for ReadCleanReq accesses
382 system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.605028 # miss rate for ReadCleanReq accesses
383 system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.978593 # miss rate for ReadSharedReq accesses
384 system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.978593 # miss rate for ReadSharedReq accesses
385 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.605028 # miss rate for demand accesses
386 system.cpu.l2cache.demand_miss_rate::cpu.data 0.994751 # miss rate for demand accesses
387 system.cpu.l2cache.demand_miss_rate::total 0.717533 # miss rate for demand accesses
388 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.605028 # miss rate for overall accesses
389 system.cpu.l2cache.overall_miss_rate::cpu.data 0.994751 # miss rate for overall accesses
390 system.cpu.l2cache.overall_miss_rate::total 0.717533 # miss rate for overall accesses
391 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500.634921 # average ReadExReq miss latency
392 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500.634921 # average ReadExReq miss latency
393 system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60511.619718 # average ReadCleanReq miss latency
394 system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60511.619718 # average ReadCleanReq miss latency
395 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60506.250000 # average ReadSharedReq miss latency
396 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60506.250000 # average ReadSharedReq miss latency
397 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60511.619718 # average overall miss latency
398 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60501.583113 # average overall miss latency
399 system.cpu.l2cache.demand_avg_miss_latency::total 60507.602957 # average overall miss latency
400 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60511.619718 # average overall miss latency
401 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60501.583113 # average overall miss latency
402 system.cpu.l2cache.overall_avg_miss_latency::total 60507.602957 # average overall miss latency
403 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
404 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
405 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
406 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
407 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
408 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
409 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1575 # number of ReadExReq MSHR misses
410 system.cpu.l2cache.ReadExReq_mshr_misses::total 1575 # number of ReadExReq MSHR misses
411 system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2840 # number of ReadCleanReq MSHR misses
412 system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2840 # number of ReadCleanReq MSHR misses
413 system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 320 # number of ReadSharedReq MSHR misses
414 system.cpu.l2cache.ReadSharedReq_mshr_misses::total 320 # number of ReadSharedReq MSHR misses
415 system.cpu.l2cache.demand_mshr_misses::cpu.inst 2840 # number of demand (read+write) MSHR misses
416 system.cpu.l2cache.demand_mshr_misses::cpu.data 1895 # number of demand (read+write) MSHR misses
417 system.cpu.l2cache.demand_mshr_misses::total 4735 # number of demand (read+write) MSHR misses
418 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2840 # number of overall MSHR misses
419 system.cpu.l2cache.overall_mshr_misses::cpu.data 1895 # number of overall MSHR misses
420 system.cpu.l2cache.overall_mshr_misses::total 4735 # number of overall MSHR misses
421 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 79538500 # number of ReadExReq MSHR miss cycles
422 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 79538500 # number of ReadExReq MSHR miss cycles
423 system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 143453000 # number of ReadCleanReq MSHR miss cycles
424 system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 143453000 # number of ReadCleanReq MSHR miss cycles
425 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 16162000 # number of ReadSharedReq MSHR miss cycles
426 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 16162000 # number of ReadSharedReq MSHR miss cycles
427 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 143453000 # number of demand (read+write) MSHR miss cycles
428 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 95700500 # number of demand (read+write) MSHR miss cycles
429 system.cpu.l2cache.demand_mshr_miss_latency::total 239153500 # number of demand (read+write) MSHR miss cycles
430 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 143453000 # number of overall MSHR miss cycles
431 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 95700500 # number of overall MSHR miss cycles
432 system.cpu.l2cache.overall_mshr_miss_latency::total 239153500 # number of overall MSHR miss cycles
433 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.998099 # mshr miss rate for ReadExReq accesses
434 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.998099 # mshr miss rate for ReadExReq accesses
435 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.605028 # mshr miss rate for ReadCleanReq accesses
436 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.605028 # mshr miss rate for ReadCleanReq accesses
437 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.978593 # mshr miss rate for ReadSharedReq accesses
438 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.978593 # mshr miss rate for ReadSharedReq accesses
439 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.605028 # mshr miss rate for demand accesses
440 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.994751 # mshr miss rate for demand accesses
441 system.cpu.l2cache.demand_mshr_miss_rate::total 0.717533 # mshr miss rate for demand accesses
442 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.605028 # mshr miss rate for overall accesses
443 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.994751 # mshr miss rate for overall accesses
444 system.cpu.l2cache.overall_mshr_miss_rate::total 0.717533 # mshr miss rate for overall accesses
445 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500.634921 # average ReadExReq mshr miss latency
446 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500.634921 # average ReadExReq mshr miss latency
447 system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50511.619718 # average ReadCleanReq mshr miss latency
448 system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50511.619718 # average ReadCleanReq mshr miss latency
449 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50506.250000 # average ReadSharedReq mshr miss latency
450 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50506.250000 # average ReadSharedReq mshr miss latency
451 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50511.619718 # average overall mshr miss latency
452 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50501.583113 # average overall mshr miss latency
453 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50507.602957 # average overall mshr miss latency
454 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50511.619718 # average overall mshr miss latency
455 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50501.583113 # average overall mshr miss latency
456 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50507.602957 # average overall mshr miss latency
457 system.cpu.toL2Bus.snoop_filter.tot_requests 9476 # Total number of requests made to the snoop filter.
458 system.cpu.toL2Bus.snoop_filter.hit_single_requests 2878 # Number of requests hitting in the snoop filter with a single holder of the requested data.
459 system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
460 system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
461 system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
462 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
463 system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 250991873500 # Cumulative time (in ticks) in various power states
464 system.cpu.toL2Bus.trans_dist::ReadResp 5021 # Transaction distribution
465 system.cpu.toL2Bus.trans_dist::WritebackDirty 7 # Transaction distribution
466 system.cpu.toL2Bus.trans_dist::WritebackClean 2836 # Transaction distribution
467 system.cpu.toL2Bus.trans_dist::CleanEvict 34 # Transaction distribution
468 system.cpu.toL2Bus.trans_dist::ReadExReq 1578 # Transaction distribution
469 system.cpu.toL2Bus.trans_dist::ReadExResp 1578 # Transaction distribution
470 system.cpu.toL2Bus.trans_dist::ReadCleanReq 4694 # Transaction distribution
471 system.cpu.toL2Bus.trans_dist::ReadSharedReq 327 # Transaction distribution
472 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 12224 # Packet count per connected master and slave (bytes)
473 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3851 # Packet count per connected master and slave (bytes)
474 system.cpu.toL2Bus.pkt_count::total 16075 # Packet count per connected master and slave (bytes)
475 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 481920 # Cumulative packet size per connected master and slave (bytes)
476 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 122368 # Cumulative packet size per connected master and slave (bytes)
477 system.cpu.toL2Bus.pkt_size::total 604288 # Cumulative packet size per connected master and slave (bytes)
478 system.cpu.toL2Bus.snoops 0 # Total snoops (count)
479 system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes)
480 system.cpu.toL2Bus.snoop_fanout::samples 6599 # Request fanout histogram
481 system.cpu.toL2Bus.snoop_fanout::mean 0.000152 # Request fanout histogram
482 system.cpu.toL2Bus.snoop_fanout::stdev 0.012310 # Request fanout histogram
483 system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
484 system.cpu.toL2Bus.snoop_fanout::0 6598 99.98% 99.98% # Request fanout histogram
485 system.cpu.toL2Bus.snoop_fanout::1 1 0.02% 100.00% # Request fanout histogram
486 system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
487 system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
488 system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
489 system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
490 system.cpu.toL2Bus.snoop_fanout::total 6599 # Request fanout histogram
491 system.cpu.toL2Bus.reqLayer0.occupancy 7581000 # Layer occupancy (ticks)
492 system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
493 system.cpu.toL2Bus.respLayer0.occupancy 7041000 # Layer occupancy (ticks)
494 system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
495 system.cpu.toL2Bus.respLayer1.occupancy 2857500 # Layer occupancy (ticks)
496 system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
497 system.membus.snoop_filter.tot_requests 4735 # Total number of requests made to the snoop filter.
498 system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
499 system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
500 system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
501 system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
502 system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
503 system.membus.pwrStateResidencyTicks::UNDEFINED 250991873500 # Cumulative time (in ticks) in various power states
504 system.membus.trans_dist::ReadResp 3160 # Transaction distribution
505 system.membus.trans_dist::ReadExReq 1575 # Transaction distribution
506 system.membus.trans_dist::ReadExResp 1575 # Transaction distribution
507 system.membus.trans_dist::ReadSharedReq 3160 # Transaction distribution
508 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 9470 # Packet count per connected master and slave (bytes)
509 system.membus.pkt_count_system.cpu.l2cache.mem_side::total 9470 # Packet count per connected master and slave (bytes)
510 system.membus.pkt_count::total 9470 # Packet count per connected master and slave (bytes)
511 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 303040 # Cumulative packet size per connected master and slave (bytes)
512 system.membus.pkt_size_system.cpu.l2cache.mem_side::total 303040 # Cumulative packet size per connected master and slave (bytes)
513 system.membus.pkt_size::total 303040 # Cumulative packet size per connected master and slave (bytes)
514 system.membus.snoops 0 # Total snoops (count)
515 system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
516 system.membus.snoop_fanout::samples 4735 # Request fanout histogram
517 system.membus.snoop_fanout::mean 0 # Request fanout histogram
518 system.membus.snoop_fanout::stdev 0 # Request fanout histogram
519 system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
520 system.membus.snoop_fanout::0 4735 100.00% 100.00% # Request fanout histogram
521 system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
522 system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
523 system.membus.snoop_fanout::min_value 0 # Request fanout histogram
524 system.membus.snoop_fanout::max_value 0 # Request fanout histogram
525 system.membus.snoop_fanout::total 4735 # Request fanout histogram
526 system.membus.reqLayer0.occupancy 4771000 # Layer occupancy (ticks)
527 system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
528 system.membus.respLayer1.occupancy 23675000 # Layer occupancy (ticks)
529 system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
531 ---------- End Simulation Statistics ----------
projects / gem5.git / blob