2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.250987 # Number of seconds simulated
4 sim_ticks 250987138500 # Number of ticks simulated
5 final_tick 250987138500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 309334 # Simulator instruction rate (inst/s)
8 host_op_rate 518472 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 587856087 # Simulator tick rate (ticks/s)
10 host_mem_usage 279244 # Number of bytes of host memory used
11 host_seconds 426.95 # Real time elapsed on the host
12 sim_insts 132071193 # Number of instructions simulated
13 sim_ops 221363385 # Number of ops (including micro ops) simulated
14 system.voltage_domain.voltage 1 # Voltage in Volts
15 system.clk_domain.clock 1000 # Clock period in ticks
16 system.physmem.bytes_read::cpu.inst 181760 # Number of bytes read from this memory
17 system.physmem.bytes_read::cpu.data 121280 # Number of bytes read from this memory
18 system.physmem.bytes_read::total 303040 # Number of bytes read from this memory
19 system.physmem.bytes_inst_read::cpu.inst 181760 # Number of instructions bytes read from this memory
20 system.physmem.bytes_inst_read::total 181760 # Number of instructions bytes read from this memory
21 system.physmem.num_reads::cpu.inst 2840 # Number of read requests responded to by this memory
22 system.physmem.num_reads::cpu.data 1895 # Number of read requests responded to by this memory
23 system.physmem.num_reads::total 4735 # Number of read requests responded to by this memory
24 system.physmem.bw_read::cpu.inst 724181 # Total read bandwidth from this memory (bytes/s)
25 system.physmem.bw_read::cpu.data 483212 # Total read bandwidth from this memory (bytes/s)
26 system.physmem.bw_read::total 1207393 # Total read bandwidth from this memory (bytes/s)
27 system.physmem.bw_inst_read::cpu.inst 724181 # Instruction read bandwidth from this memory (bytes/s)
28 system.physmem.bw_inst_read::total 724181 # Instruction read bandwidth from this memory (bytes/s)
29 system.physmem.bw_total::cpu.inst 724181 # Total bandwidth to/from this memory (bytes/s)
30 system.physmem.bw_total::cpu.data 483212 # Total bandwidth to/from this memory (bytes/s)
31 system.physmem.bw_total::total 1207393 # Total bandwidth to/from this memory (bytes/s)
32 system.cpu_clk_domain.clock 500 # Clock period in ticks
33 system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
34 system.cpu.workload.num_syscalls 400 # Number of system calls
35 system.cpu.numCycles 501974277 # number of cpu cycles simulated
36 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
37 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
38 system.cpu.committedInsts 132071193 # Number of instructions committed
39 system.cpu.committedOps 221363385 # Number of ops (including micro ops) committed
40 system.cpu.num_int_alu_accesses 219019986 # Number of integer alu accesses
41 system.cpu.num_fp_alu_accesses 2162459 # Number of float alu accesses
42 system.cpu.num_func_calls 1595632 # number of times a function call or return occured
43 system.cpu.num_conditional_control_insts 8268466 # number of instructions that are conditional controls
44 system.cpu.num_int_insts 219019986 # number of integer instructions
45 system.cpu.num_fp_insts 2162459 # number of float instructions
46 system.cpu.num_int_register_reads 519996939 # number of times the integer registers were read
47 system.cpu.num_int_register_writes 201355989 # number of times the integer registers were written
48 system.cpu.num_fp_register_reads 3037165 # number of times the floating registers were read
49 system.cpu.num_fp_register_writes 1831403 # number of times the floating registers were written
50 system.cpu.num_cc_register_reads 96962463 # number of times the CC registers were read
51 system.cpu.num_cc_register_writes 56242058 # number of times the CC registers were written
52 system.cpu.num_mem_refs 77165304 # number of memory refs
53 system.cpu.num_load_insts 56649587 # Number of load instructions
54 system.cpu.num_store_insts 20515717 # Number of store instructions
55 system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
56 system.cpu.num_busy_cycles 501974276.998000 # Number of busy cycles
57 system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
58 system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
59 system.cpu.Branches 12326938 # Number of branches fetched
60 system.cpu.op_class::No_OpClass 1176721 0.53% 0.53% # Class of executed instruction
61 system.cpu.op_class::IntAlu 134111833 60.58% 61.12% # Class of executed instruction
62 system.cpu.op_class::IntMult 772953 0.35% 61.47% # Class of executed instruction
63 system.cpu.op_class::IntDiv 7031501 3.18% 64.64% # Class of executed instruction
64 system.cpu.op_class::FloatAdd 1105073 0.50% 65.14% # Class of executed instruction
65 system.cpu.op_class::FloatCmp 0 0.00% 65.14% # Class of executed instruction
66 system.cpu.op_class::FloatCvt 0 0.00% 65.14% # Class of executed instruction
67 system.cpu.op_class::FloatMult 0 0.00% 65.14% # Class of executed instruction
68 system.cpu.op_class::FloatDiv 0 0.00% 65.14% # Class of executed instruction
69 system.cpu.op_class::FloatSqrt 0 0.00% 65.14% # Class of executed instruction
70 system.cpu.op_class::SimdAdd 0 0.00% 65.14% # Class of executed instruction
71 system.cpu.op_class::SimdAddAcc 0 0.00% 65.14% # Class of executed instruction
72 system.cpu.op_class::SimdAlu 0 0.00% 65.14% # Class of executed instruction
73 system.cpu.op_class::SimdCmp 0 0.00% 65.14% # Class of executed instruction
74 system.cpu.op_class::SimdCvt 0 0.00% 65.14% # Class of executed instruction
75 system.cpu.op_class::SimdMisc 0 0.00% 65.14% # Class of executed instruction
76 system.cpu.op_class::SimdMult 0 0.00% 65.14% # Class of executed instruction
77 system.cpu.op_class::SimdMultAcc 0 0.00% 65.14% # Class of executed instruction
78 system.cpu.op_class::SimdShift 0 0.00% 65.14% # Class of executed instruction
79 system.cpu.op_class::SimdShiftAcc 0 0.00% 65.14% # Class of executed instruction
80 system.cpu.op_class::SimdSqrt 0 0.00% 65.14% # Class of executed instruction
81 system.cpu.op_class::SimdFloatAdd 0 0.00% 65.14% # Class of executed instruction
82 system.cpu.op_class::SimdFloatAlu 0 0.00% 65.14% # Class of executed instruction
83 system.cpu.op_class::SimdFloatCmp 0 0.00% 65.14% # Class of executed instruction
84 system.cpu.op_class::SimdFloatCvt 0 0.00% 65.14% # Class of executed instruction
85 system.cpu.op_class::SimdFloatDiv 0 0.00% 65.14% # Class of executed instruction
86 system.cpu.op_class::SimdFloatMisc 0 0.00% 65.14% # Class of executed instruction
87 system.cpu.op_class::SimdFloatMult 0 0.00% 65.14% # Class of executed instruction
88 system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.14% # Class of executed instruction
89 system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.14% # Class of executed instruction
90 system.cpu.op_class::MemRead 56649587 25.59% 90.73% # Class of executed instruction
91 system.cpu.op_class::MemWrite 20515717 9.27% 100.00% # Class of executed instruction
92 system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
93 system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
94 system.cpu.op_class::total 221363385 # Class of executed instruction
95 system.cpu.dcache.tags.replacements 41 # number of replacements
96 system.cpu.dcache.tags.tagsinuse 1363.414730 # Cycle average of tags in use
97 system.cpu.dcache.tags.total_refs 77195831 # Total number of references to valid blocks.
98 system.cpu.dcache.tags.sampled_refs 1905 # Sample count of references to valid blocks.
99 system.cpu.dcache.tags.avg_refs 40522.745932 # Average number of references to valid blocks.
100 system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
101 system.cpu.dcache.tags.occ_blocks::cpu.data 1363.414730 # Average occupied blocks per requestor
102 system.cpu.dcache.tags.occ_percent::cpu.data 0.332865 # Average percentage of cache occupancy
103 system.cpu.dcache.tags.occ_percent::total 0.332865 # Average percentage of cache occupancy
104 system.cpu.dcache.tags.occ_task_id_blocks::1024 1864 # Occupied blocks per task id
105 system.cpu.dcache.tags.age_task_id_blocks_1024::0 7 # Occupied blocks per task id
106 system.cpu.dcache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id
107 system.cpu.dcache.tags.age_task_id_blocks_1024::2 43 # Occupied blocks per task id
108 system.cpu.dcache.tags.age_task_id_blocks_1024::3 472 # Occupied blocks per task id
109 system.cpu.dcache.tags.age_task_id_blocks_1024::4 1328 # Occupied blocks per task id
110 system.cpu.dcache.tags.occ_task_id_percent::1024 0.455078 # Percentage of cache occupancy per task id
111 system.cpu.dcache.tags.tag_accesses 154397377 # Number of tag accesses
112 system.cpu.dcache.tags.data_accesses 154397377 # Number of data accesses
113 system.cpu.dcache.ReadReq_hits::cpu.data 56681678 # number of ReadReq hits
114 system.cpu.dcache.ReadReq_hits::total 56681678 # number of ReadReq hits
115 system.cpu.dcache.WriteReq_hits::cpu.data 20514153 # number of WriteReq hits
116 system.cpu.dcache.WriteReq_hits::total 20514153 # number of WriteReq hits
117 system.cpu.dcache.demand_hits::cpu.data 77195831 # number of demand (read+write) hits
118 system.cpu.dcache.demand_hits::total 77195831 # number of demand (read+write) hits
119 system.cpu.dcache.overall_hits::cpu.data 77195831 # number of overall hits
120 system.cpu.dcache.overall_hits::total 77195831 # number of overall hits
121 system.cpu.dcache.ReadReq_misses::cpu.data 327 # number of ReadReq misses
122 system.cpu.dcache.ReadReq_misses::total 327 # number of ReadReq misses
123 system.cpu.dcache.WriteReq_misses::cpu.data 1578 # number of WriteReq misses
124 system.cpu.dcache.WriteReq_misses::total 1578 # number of WriteReq misses
125 system.cpu.dcache.demand_misses::cpu.data 1905 # number of demand (read+write) misses
126 system.cpu.dcache.demand_misses::total 1905 # number of demand (read+write) misses
127 system.cpu.dcache.overall_misses::cpu.data 1905 # number of overall misses
128 system.cpu.dcache.overall_misses::total 1905 # number of overall misses
129 system.cpu.dcache.ReadReq_miss_latency::cpu.data 19933500 # number of ReadReq miss cycles
130 system.cpu.dcache.ReadReq_miss_latency::total 19933500 # number of ReadReq miss cycles
131 system.cpu.dcache.WriteReq_miss_latency::cpu.data 97691000 # number of WriteReq miss cycles
132 system.cpu.dcache.WriteReq_miss_latency::total 97691000 # number of WriteReq miss cycles
133 system.cpu.dcache.demand_miss_latency::cpu.data 117624500 # number of demand (read+write) miss cycles
134 system.cpu.dcache.demand_miss_latency::total 117624500 # number of demand (read+write) miss cycles
135 system.cpu.dcache.overall_miss_latency::cpu.data 117624500 # number of overall miss cycles
136 system.cpu.dcache.overall_miss_latency::total 117624500 # number of overall miss cycles
137 system.cpu.dcache.ReadReq_accesses::cpu.data 56682005 # number of ReadReq accesses(hits+misses)
138 system.cpu.dcache.ReadReq_accesses::total 56682005 # number of ReadReq accesses(hits+misses)
139 system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses)
140 system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses)
141 system.cpu.dcache.demand_accesses::cpu.data 77197736 # number of demand (read+write) accesses
142 system.cpu.dcache.demand_accesses::total 77197736 # number of demand (read+write) accesses
143 system.cpu.dcache.overall_accesses::cpu.data 77197736 # number of overall (read+write) accesses
144 system.cpu.dcache.overall_accesses::total 77197736 # number of overall (read+write) accesses
145 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000006 # miss rate for ReadReq accesses
146 system.cpu.dcache.ReadReq_miss_rate::total 0.000006 # miss rate for ReadReq accesses
147 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000077 # miss rate for WriteReq accesses
148 system.cpu.dcache.WriteReq_miss_rate::total 0.000077 # miss rate for WriteReq accesses
149 system.cpu.dcache.demand_miss_rate::cpu.data 0.000025 # miss rate for demand accesses
150 system.cpu.dcache.demand_miss_rate::total 0.000025 # miss rate for demand accesses
151 system.cpu.dcache.overall_miss_rate::cpu.data 0.000025 # miss rate for overall accesses
152 system.cpu.dcache.overall_miss_rate::total 0.000025 # miss rate for overall accesses
153 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60958.715596 # average ReadReq miss latency
154 system.cpu.dcache.ReadReq_avg_miss_latency::total 60958.715596 # average ReadReq miss latency
155 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61908.111534 # average WriteReq miss latency
156 system.cpu.dcache.WriteReq_avg_miss_latency::total 61908.111534 # average WriteReq miss latency
157 system.cpu.dcache.demand_avg_miss_latency::cpu.data 61745.144357 # average overall miss latency
158 system.cpu.dcache.demand_avg_miss_latency::total 61745.144357 # average overall miss latency
159 system.cpu.dcache.overall_avg_miss_latency::cpu.data 61745.144357 # average overall miss latency
160 system.cpu.dcache.overall_avg_miss_latency::total 61745.144357 # average overall miss latency
161 system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
162 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
163 system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
164 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
165 system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
166 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
167 system.cpu.dcache.fast_writes 0 # number of fast writes performed
168 system.cpu.dcache.cache_copies 0 # number of cache copies performed
169 system.cpu.dcache.writebacks::writebacks 7 # number of writebacks
170 system.cpu.dcache.writebacks::total 7 # number of writebacks
171 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 327 # number of ReadReq MSHR misses
172 system.cpu.dcache.ReadReq_mshr_misses::total 327 # number of ReadReq MSHR misses
173 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1578 # number of WriteReq MSHR misses
174 system.cpu.dcache.WriteReq_mshr_misses::total 1578 # number of WriteReq MSHR misses
175 system.cpu.dcache.demand_mshr_misses::cpu.data 1905 # number of demand (read+write) MSHR misses
176 system.cpu.dcache.demand_mshr_misses::total 1905 # number of demand (read+write) MSHR misses
177 system.cpu.dcache.overall_mshr_misses::cpu.data 1905 # number of overall MSHR misses
178 system.cpu.dcache.overall_mshr_misses::total 1905 # number of overall MSHR misses
179 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 19606500 # number of ReadReq MSHR miss cycles
180 system.cpu.dcache.ReadReq_mshr_miss_latency::total 19606500 # number of ReadReq MSHR miss cycles
181 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 96113000 # number of WriteReq MSHR miss cycles
182 system.cpu.dcache.WriteReq_mshr_miss_latency::total 96113000 # number of WriteReq MSHR miss cycles
183 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 115719500 # number of demand (read+write) MSHR miss cycles
184 system.cpu.dcache.demand_mshr_miss_latency::total 115719500 # number of demand (read+write) MSHR miss cycles
185 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 115719500 # number of overall MSHR miss cycles
186 system.cpu.dcache.overall_mshr_miss_latency::total 115719500 # number of overall MSHR miss cycles
187 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000006 # mshr miss rate for ReadReq accesses
188 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000006 # mshr miss rate for ReadReq accesses
189 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000077 # mshr miss rate for WriteReq accesses
190 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000077 # mshr miss rate for WriteReq accesses
191 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses
192 system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses
193 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses
194 system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses
195 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 59958.715596 # average ReadReq mshr miss latency
196 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 59958.715596 # average ReadReq mshr miss latency
197 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60908.111534 # average WriteReq mshr miss latency
198 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60908.111534 # average WriteReq mshr miss latency
199 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 60745.144357 # average overall mshr miss latency
200 system.cpu.dcache.demand_avg_mshr_miss_latency::total 60745.144357 # average overall mshr miss latency
201 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 60745.144357 # average overall mshr miss latency
202 system.cpu.dcache.overall_avg_mshr_miss_latency::total 60745.144357 # average overall mshr miss latency
203 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
204 system.cpu.icache.tags.replacements 2836 # number of replacements
205 system.cpu.icache.tags.tagsinuse 1455.245085 # Cycle average of tags in use
206 system.cpu.icache.tags.total_refs 173489673 # Total number of references to valid blocks.
207 system.cpu.icache.tags.sampled_refs 4694 # Sample count of references to valid blocks.
208 system.cpu.icache.tags.avg_refs 36959.879207 # Average number of references to valid blocks.
209 system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
210 system.cpu.icache.tags.occ_blocks::cpu.inst 1455.245085 # Average occupied blocks per requestor
211 system.cpu.icache.tags.occ_percent::cpu.inst 0.710569 # Average percentage of cache occupancy
212 system.cpu.icache.tags.occ_percent::total 0.710569 # Average percentage of cache occupancy
213 system.cpu.icache.tags.occ_task_id_blocks::1024 1858 # Occupied blocks per task id
214 system.cpu.icache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id
215 system.cpu.icache.tags.age_task_id_blocks_1024::1 60 # Occupied blocks per task id
216 system.cpu.icache.tags.age_task_id_blocks_1024::2 477 # Occupied blocks per task id
217 system.cpu.icache.tags.age_task_id_blocks_1024::3 415 # Occupied blocks per task id
218 system.cpu.icache.tags.age_task_id_blocks_1024::4 869 # Occupied blocks per task id
219 system.cpu.icache.tags.occ_task_id_percent::1024 0.907227 # Percentage of cache occupancy per task id
220 system.cpu.icache.tags.tag_accesses 346993428 # Number of tag accesses
221 system.cpu.icache.tags.data_accesses 346993428 # Number of data accesses
222 system.cpu.icache.ReadReq_hits::cpu.inst 173489673 # number of ReadReq hits
223 system.cpu.icache.ReadReq_hits::total 173489673 # number of ReadReq hits
224 system.cpu.icache.demand_hits::cpu.inst 173489673 # number of demand (read+write) hits
225 system.cpu.icache.demand_hits::total 173489673 # number of demand (read+write) hits
226 system.cpu.icache.overall_hits::cpu.inst 173489673 # number of overall hits
227 system.cpu.icache.overall_hits::total 173489673 # number of overall hits
228 system.cpu.icache.ReadReq_misses::cpu.inst 4694 # number of ReadReq misses
229 system.cpu.icache.ReadReq_misses::total 4694 # number of ReadReq misses
230 system.cpu.icache.demand_misses::cpu.inst 4694 # number of demand (read+write) misses
231 system.cpu.icache.demand_misses::total 4694 # number of demand (read+write) misses
232 system.cpu.icache.overall_misses::cpu.inst 4694 # number of overall misses
233 system.cpu.icache.overall_misses::total 4694 # number of overall misses
234 system.cpu.icache.ReadReq_miss_latency::cpu.inst 200232500 # number of ReadReq miss cycles
235 system.cpu.icache.ReadReq_miss_latency::total 200232500 # number of ReadReq miss cycles
236 system.cpu.icache.demand_miss_latency::cpu.inst 200232500 # number of demand (read+write) miss cycles
237 system.cpu.icache.demand_miss_latency::total 200232500 # number of demand (read+write) miss cycles
238 system.cpu.icache.overall_miss_latency::cpu.inst 200232500 # number of overall miss cycles
239 system.cpu.icache.overall_miss_latency::total 200232500 # number of overall miss cycles
240 system.cpu.icache.ReadReq_accesses::cpu.inst 173494367 # number of ReadReq accesses(hits+misses)
241 system.cpu.icache.ReadReq_accesses::total 173494367 # number of ReadReq accesses(hits+misses)
242 system.cpu.icache.demand_accesses::cpu.inst 173494367 # number of demand (read+write) accesses
243 system.cpu.icache.demand_accesses::total 173494367 # number of demand (read+write) accesses
244 system.cpu.icache.overall_accesses::cpu.inst 173494367 # number of overall (read+write) accesses
245 system.cpu.icache.overall_accesses::total 173494367 # number of overall (read+write) accesses
246 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000027 # miss rate for ReadReq accesses
247 system.cpu.icache.ReadReq_miss_rate::total 0.000027 # miss rate for ReadReq accesses
248 system.cpu.icache.demand_miss_rate::cpu.inst 0.000027 # miss rate for demand accesses
249 system.cpu.icache.demand_miss_rate::total 0.000027 # miss rate for demand accesses
250 system.cpu.icache.overall_miss_rate::cpu.inst 0.000027 # miss rate for overall accesses
251 system.cpu.icache.overall_miss_rate::total 0.000027 # miss rate for overall accesses
252 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42657.115467 # average ReadReq miss latency
253 system.cpu.icache.ReadReq_avg_miss_latency::total 42657.115467 # average ReadReq miss latency
254 system.cpu.icache.demand_avg_miss_latency::cpu.inst 42657.115467 # average overall miss latency
255 system.cpu.icache.demand_avg_miss_latency::total 42657.115467 # average overall miss latency
256 system.cpu.icache.overall_avg_miss_latency::cpu.inst 42657.115467 # average overall miss latency
257 system.cpu.icache.overall_avg_miss_latency::total 42657.115467 # average overall miss latency
258 system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
259 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
260 system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
261 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
262 system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
263 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
264 system.cpu.icache.fast_writes 0 # number of fast writes performed
265 system.cpu.icache.cache_copies 0 # number of cache copies performed
266 system.cpu.icache.writebacks::writebacks 2836 # number of writebacks
267 system.cpu.icache.writebacks::total 2836 # number of writebacks
268 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4694 # number of ReadReq MSHR misses
269 system.cpu.icache.ReadReq_mshr_misses::total 4694 # number of ReadReq MSHR misses
270 system.cpu.icache.demand_mshr_misses::cpu.inst 4694 # number of demand (read+write) MSHR misses
271 system.cpu.icache.demand_mshr_misses::total 4694 # number of demand (read+write) MSHR misses
272 system.cpu.icache.overall_mshr_misses::cpu.inst 4694 # number of overall MSHR misses
273 system.cpu.icache.overall_mshr_misses::total 4694 # number of overall MSHR misses
274 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 195538500 # number of ReadReq MSHR miss cycles
275 system.cpu.icache.ReadReq_mshr_miss_latency::total 195538500 # number of ReadReq MSHR miss cycles
276 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 195538500 # number of demand (read+write) MSHR miss cycles
277 system.cpu.icache.demand_mshr_miss_latency::total 195538500 # number of demand (read+write) MSHR miss cycles
278 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 195538500 # number of overall MSHR miss cycles
279 system.cpu.icache.overall_mshr_miss_latency::total 195538500 # number of overall MSHR miss cycles
280 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for ReadReq accesses
281 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000027 # mshr miss rate for ReadReq accesses
282 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for demand accesses
283 system.cpu.icache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses
284 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for overall accesses
285 system.cpu.icache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses
286 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 41657.115467 # average ReadReq mshr miss latency
287 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 41657.115467 # average ReadReq mshr miss latency
288 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41657.115467 # average overall mshr miss latency
289 system.cpu.icache.demand_avg_mshr_miss_latency::total 41657.115467 # average overall mshr miss latency
290 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41657.115467 # average overall mshr miss latency
291 system.cpu.icache.overall_avg_mshr_miss_latency::total 41657.115467 # average overall mshr miss latency
292 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
293 system.cpu.l2cache.tags.replacements 0 # number of replacements
294 system.cpu.l2cache.tags.tagsinuse 2058.105553 # Cycle average of tags in use
295 system.cpu.l2cache.tags.total_refs 4732 # Total number of references to valid blocks.
296 system.cpu.l2cache.tags.sampled_refs 3164 # Sample count of references to valid blocks.
297 system.cpu.l2cache.tags.avg_refs 1.495575 # Average number of references to valid blocks.
298 system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
299 system.cpu.l2cache.tags.occ_blocks::writebacks 0.021821 # Average occupied blocks per requestor
300 system.cpu.l2cache.tags.occ_blocks::cpu.inst 1829.911143 # Average occupied blocks per requestor
301 system.cpu.l2cache.tags.occ_blocks::cpu.data 228.172589 # Average occupied blocks per requestor
302 system.cpu.l2cache.tags.occ_percent::writebacks 0.000001 # Average percentage of cache occupancy
303 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.055844 # Average percentage of cache occupancy
304 system.cpu.l2cache.tags.occ_percent::cpu.data 0.006963 # Average percentage of cache occupancy
305 system.cpu.l2cache.tags.occ_percent::total 0.062808 # Average percentage of cache occupancy
306 system.cpu.l2cache.tags.occ_task_id_blocks::1024 3164 # Occupied blocks per task id
307 system.cpu.l2cache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id
308 system.cpu.l2cache.tags.age_task_id_blocks_1024::1 33 # Occupied blocks per task id
309 system.cpu.l2cache.tags.age_task_id_blocks_1024::2 497 # Occupied blocks per task id
310 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 532 # Occupied blocks per task id
311 system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2064 # Occupied blocks per task id
312 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.096558 # Percentage of cache occupancy per task id
313 system.cpu.l2cache.tags.tag_accesses 80550 # Number of tag accesses
314 system.cpu.l2cache.tags.data_accesses 80550 # Number of data accesses
315 system.cpu.l2cache.WritebackDirty_hits::writebacks 7 # number of WritebackDirty hits
316 system.cpu.l2cache.WritebackDirty_hits::total 7 # number of WritebackDirty hits
317 system.cpu.l2cache.WritebackClean_hits::writebacks 2836 # number of WritebackClean hits
318 system.cpu.l2cache.WritebackClean_hits::total 2836 # number of WritebackClean hits
319 system.cpu.l2cache.ReadExReq_hits::cpu.data 3 # number of ReadExReq hits
320 system.cpu.l2cache.ReadExReq_hits::total 3 # number of ReadExReq hits
321 system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1854 # number of ReadCleanReq hits
322 system.cpu.l2cache.ReadCleanReq_hits::total 1854 # number of ReadCleanReq hits
323 system.cpu.l2cache.ReadSharedReq_hits::cpu.data 7 # number of ReadSharedReq hits
324 system.cpu.l2cache.ReadSharedReq_hits::total 7 # number of ReadSharedReq hits
325 system.cpu.l2cache.demand_hits::cpu.inst 1854 # number of demand (read+write) hits
326 system.cpu.l2cache.demand_hits::cpu.data 10 # number of demand (read+write) hits
327 system.cpu.l2cache.demand_hits::total 1864 # number of demand (read+write) hits
328 system.cpu.l2cache.overall_hits::cpu.inst 1854 # number of overall hits
329 system.cpu.l2cache.overall_hits::cpu.data 10 # number of overall hits
330 system.cpu.l2cache.overall_hits::total 1864 # number of overall hits
331 system.cpu.l2cache.ReadExReq_misses::cpu.data 1575 # number of ReadExReq misses
332 system.cpu.l2cache.ReadExReq_misses::total 1575 # number of ReadExReq misses
333 system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2840 # number of ReadCleanReq misses
334 system.cpu.l2cache.ReadCleanReq_misses::total 2840 # number of ReadCleanReq misses
335 system.cpu.l2cache.ReadSharedReq_misses::cpu.data 320 # number of ReadSharedReq misses
336 system.cpu.l2cache.ReadSharedReq_misses::total 320 # number of ReadSharedReq misses
337 system.cpu.l2cache.demand_misses::cpu.inst 2840 # number of demand (read+write) misses
338 system.cpu.l2cache.demand_misses::cpu.data 1895 # number of demand (read+write) misses
339 system.cpu.l2cache.demand_misses::total 4735 # number of demand (read+write) misses
340 system.cpu.l2cache.overall_misses::cpu.inst 2840 # number of overall misses
341 system.cpu.l2cache.overall_misses::cpu.data 1895 # number of overall misses
342 system.cpu.l2cache.overall_misses::total 4735 # number of overall misses
343 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 93713500 # number of ReadExReq miss cycles
344 system.cpu.l2cache.ReadExReq_miss_latency::total 93713500 # number of ReadExReq miss cycles
345 system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 169013000 # number of ReadCleanReq miss cycles
346 system.cpu.l2cache.ReadCleanReq_miss_latency::total 169013000 # number of ReadCleanReq miss cycles
347 system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 19042000 # number of ReadSharedReq miss cycles
348 system.cpu.l2cache.ReadSharedReq_miss_latency::total 19042000 # number of ReadSharedReq miss cycles
349 system.cpu.l2cache.demand_miss_latency::cpu.inst 169013000 # number of demand (read+write) miss cycles
350 system.cpu.l2cache.demand_miss_latency::cpu.data 112755500 # number of demand (read+write) miss cycles
351 system.cpu.l2cache.demand_miss_latency::total 281768500 # number of demand (read+write) miss cycles
352 system.cpu.l2cache.overall_miss_latency::cpu.inst 169013000 # number of overall miss cycles
353 system.cpu.l2cache.overall_miss_latency::cpu.data 112755500 # number of overall miss cycles
354 system.cpu.l2cache.overall_miss_latency::total 281768500 # number of overall miss cycles
355 system.cpu.l2cache.WritebackDirty_accesses::writebacks 7 # number of WritebackDirty accesses(hits+misses)
356 system.cpu.l2cache.WritebackDirty_accesses::total 7 # number of WritebackDirty accesses(hits+misses)
357 system.cpu.l2cache.WritebackClean_accesses::writebacks 2836 # number of WritebackClean accesses(hits+misses)
358 system.cpu.l2cache.WritebackClean_accesses::total 2836 # number of WritebackClean accesses(hits+misses)
359 system.cpu.l2cache.ReadExReq_accesses::cpu.data 1578 # number of ReadExReq accesses(hits+misses)
360 system.cpu.l2cache.ReadExReq_accesses::total 1578 # number of ReadExReq accesses(hits+misses)
361 system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 4694 # number of ReadCleanReq accesses(hits+misses)
362 system.cpu.l2cache.ReadCleanReq_accesses::total 4694 # number of ReadCleanReq accesses(hits+misses)
363 system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 327 # number of ReadSharedReq accesses(hits+misses)
364 system.cpu.l2cache.ReadSharedReq_accesses::total 327 # number of ReadSharedReq accesses(hits+misses)
365 system.cpu.l2cache.demand_accesses::cpu.inst 4694 # number of demand (read+write) accesses
366 system.cpu.l2cache.demand_accesses::cpu.data 1905 # number of demand (read+write) accesses
367 system.cpu.l2cache.demand_accesses::total 6599 # number of demand (read+write) accesses
368 system.cpu.l2cache.overall_accesses::cpu.inst 4694 # number of overall (read+write) accesses
369 system.cpu.l2cache.overall_accesses::cpu.data 1905 # number of overall (read+write) accesses
370 system.cpu.l2cache.overall_accesses::total 6599 # number of overall (read+write) accesses
371 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.998099 # miss rate for ReadExReq accesses
372 system.cpu.l2cache.ReadExReq_miss_rate::total 0.998099 # miss rate for ReadExReq accesses
373 system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.605028 # miss rate for ReadCleanReq accesses
374 system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.605028 # miss rate for ReadCleanReq accesses
375 system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.978593 # miss rate for ReadSharedReq accesses
376 system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.978593 # miss rate for ReadSharedReq accesses
377 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.605028 # miss rate for demand accesses
378 system.cpu.l2cache.demand_miss_rate::cpu.data 0.994751 # miss rate for demand accesses
379 system.cpu.l2cache.demand_miss_rate::total 0.717533 # miss rate for demand accesses
380 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.605028 # miss rate for overall accesses
381 system.cpu.l2cache.overall_miss_rate::cpu.data 0.994751 # miss rate for overall accesses
382 system.cpu.l2cache.overall_miss_rate::total 0.717533 # miss rate for overall accesses
383 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.634921 # average ReadExReq miss latency
384 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.634921 # average ReadExReq miss latency
385 system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59511.619718 # average ReadCleanReq miss latency
386 system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59511.619718 # average ReadCleanReq miss latency
387 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59506.250000 # average ReadSharedReq miss latency
388 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59506.250000 # average ReadSharedReq miss latency
389 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59511.619718 # average overall miss latency
390 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59501.583113 # average overall miss latency
391 system.cpu.l2cache.demand_avg_miss_latency::total 59507.602957 # average overall miss latency
392 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59511.619718 # average overall miss latency
393 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59501.583113 # average overall miss latency
394 system.cpu.l2cache.overall_avg_miss_latency::total 59507.602957 # average overall miss latency
395 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
396 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
397 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
398 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
399 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
400 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
401 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
402 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
403 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1575 # number of ReadExReq MSHR misses
404 system.cpu.l2cache.ReadExReq_mshr_misses::total 1575 # number of ReadExReq MSHR misses
405 system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2840 # number of ReadCleanReq MSHR misses
406 system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2840 # number of ReadCleanReq MSHR misses
407 system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 320 # number of ReadSharedReq MSHR misses
408 system.cpu.l2cache.ReadSharedReq_mshr_misses::total 320 # number of ReadSharedReq MSHR misses
409 system.cpu.l2cache.demand_mshr_misses::cpu.inst 2840 # number of demand (read+write) MSHR misses
410 system.cpu.l2cache.demand_mshr_misses::cpu.data 1895 # number of demand (read+write) MSHR misses
411 system.cpu.l2cache.demand_mshr_misses::total 4735 # number of demand (read+write) MSHR misses
412 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2840 # number of overall MSHR misses
413 system.cpu.l2cache.overall_mshr_misses::cpu.data 1895 # number of overall MSHR misses
414 system.cpu.l2cache.overall_mshr_misses::total 4735 # number of overall MSHR misses
415 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 77963500 # number of ReadExReq MSHR miss cycles
416 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 77963500 # number of ReadExReq MSHR miss cycles
417 system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 140613000 # number of ReadCleanReq MSHR miss cycles
418 system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 140613000 # number of ReadCleanReq MSHR miss cycles
419 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 15842000 # number of ReadSharedReq MSHR miss cycles
420 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 15842000 # number of ReadSharedReq MSHR miss cycles
421 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 140613000 # number of demand (read+write) MSHR miss cycles
422 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 93805500 # number of demand (read+write) MSHR miss cycles
423 system.cpu.l2cache.demand_mshr_miss_latency::total 234418500 # number of demand (read+write) MSHR miss cycles
424 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 140613000 # number of overall MSHR miss cycles
425 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 93805500 # number of overall MSHR miss cycles
426 system.cpu.l2cache.overall_mshr_miss_latency::total 234418500 # number of overall MSHR miss cycles
427 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.998099 # mshr miss rate for ReadExReq accesses
428 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.998099 # mshr miss rate for ReadExReq accesses
429 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.605028 # mshr miss rate for ReadCleanReq accesses
430 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.605028 # mshr miss rate for ReadCleanReq accesses
431 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.978593 # mshr miss rate for ReadSharedReq accesses
432 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.978593 # mshr miss rate for ReadSharedReq accesses
433 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.605028 # mshr miss rate for demand accesses
434 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.994751 # mshr miss rate for demand accesses
435 system.cpu.l2cache.demand_mshr_miss_rate::total 0.717533 # mshr miss rate for demand accesses
436 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.605028 # mshr miss rate for overall accesses
437 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.994751 # mshr miss rate for overall accesses
438 system.cpu.l2cache.overall_mshr_miss_rate::total 0.717533 # mshr miss rate for overall accesses
439 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.634921 # average ReadExReq mshr miss latency
440 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.634921 # average ReadExReq mshr miss latency
441 system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49511.619718 # average ReadCleanReq mshr miss latency
442 system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49511.619718 # average ReadCleanReq mshr miss latency
443 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49506.250000 # average ReadSharedReq mshr miss latency
444 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49506.250000 # average ReadSharedReq mshr miss latency
445 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49511.619718 # average overall mshr miss latency
446 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49501.583113 # average overall mshr miss latency
447 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49507.602957 # average overall mshr miss latency
448 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49511.619718 # average overall mshr miss latency
449 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49501.583113 # average overall mshr miss latency
450 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49507.602957 # average overall mshr miss latency
451 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
452 system.cpu.toL2Bus.snoop_filter.tot_requests 9476 # Total number of requests made to the snoop filter.
453 system.cpu.toL2Bus.snoop_filter.hit_single_requests 2878 # Number of requests hitting in the snoop filter with a single holder of the requested data.
454 system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
455 system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
456 system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
457 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
458 system.cpu.toL2Bus.trans_dist::ReadResp 5021 # Transaction distribution
459 system.cpu.toL2Bus.trans_dist::WritebackDirty 7 # Transaction distribution
460 system.cpu.toL2Bus.trans_dist::WritebackClean 2836 # Transaction distribution
461 system.cpu.toL2Bus.trans_dist::CleanEvict 34 # Transaction distribution
462 system.cpu.toL2Bus.trans_dist::ReadExReq 1578 # Transaction distribution
463 system.cpu.toL2Bus.trans_dist::ReadExResp 1578 # Transaction distribution
464 system.cpu.toL2Bus.trans_dist::ReadCleanReq 4694 # Transaction distribution
465 system.cpu.toL2Bus.trans_dist::ReadSharedReq 327 # Transaction distribution
466 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 12224 # Packet count per connected master and slave (bytes)
467 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3851 # Packet count per connected master and slave (bytes)
468 system.cpu.toL2Bus.pkt_count::total 16075 # Packet count per connected master and slave (bytes)
469 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 481920 # Cumulative packet size per connected master and slave (bytes)
470 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 122368 # Cumulative packet size per connected master and slave (bytes)
471 system.cpu.toL2Bus.pkt_size::total 604288 # Cumulative packet size per connected master and slave (bytes)
472 system.cpu.toL2Bus.snoops 0 # Total snoops (count)
473 system.cpu.toL2Bus.snoop_fanout::samples 6599 # Request fanout histogram
474 system.cpu.toL2Bus.snoop_fanout::mean 0.000152 # Request fanout histogram
475 system.cpu.toL2Bus.snoop_fanout::stdev 0.012310 # Request fanout histogram
476 system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
477 system.cpu.toL2Bus.snoop_fanout::0 6598 99.98% 99.98% # Request fanout histogram
478 system.cpu.toL2Bus.snoop_fanout::1 1 0.02% 100.00% # Request fanout histogram
479 system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
480 system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
481 system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
482 system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
483 system.cpu.toL2Bus.snoop_fanout::total 6599 # Request fanout histogram
484 system.cpu.toL2Bus.reqLayer0.occupancy 7581000 # Layer occupancy (ticks)
485 system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
486 system.cpu.toL2Bus.respLayer0.occupancy 7041000 # Layer occupancy (ticks)
487 system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
488 system.cpu.toL2Bus.respLayer1.occupancy 2857500 # Layer occupancy (ticks)
489 system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
490 system.membus.trans_dist::ReadResp 3160 # Transaction distribution
491 system.membus.trans_dist::ReadExReq 1575 # Transaction distribution
492 system.membus.trans_dist::ReadExResp 1575 # Transaction distribution
493 system.membus.trans_dist::ReadSharedReq 3160 # Transaction distribution
494 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 9470 # Packet count per connected master and slave (bytes)
495 system.membus.pkt_count_system.cpu.l2cache.mem_side::total 9470 # Packet count per connected master and slave (bytes)
496 system.membus.pkt_count::total 9470 # Packet count per connected master and slave (bytes)
497 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 303040 # Cumulative packet size per connected master and slave (bytes)
498 system.membus.pkt_size_system.cpu.l2cache.mem_side::total 303040 # Cumulative packet size per connected master and slave (bytes)
499 system.membus.pkt_size::total 303040 # Cumulative packet size per connected master and slave (bytes)
500 system.membus.snoops 0 # Total snoops (count)
501 system.membus.snoop_fanout::samples 4735 # Request fanout histogram
502 system.membus.snoop_fanout::mean 0 # Request fanout histogram
503 system.membus.snoop_fanout::stdev 0 # Request fanout histogram
504 system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
505 system.membus.snoop_fanout::0 4735 100.00% 100.00% # Request fanout histogram
506 system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
507 system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
508 system.membus.snoop_fanout::min_value 0 # Request fanout histogram
509 system.membus.snoop_fanout::max_value 0 # Request fanout histogram
510 system.membus.snoop_fanout::total 4735 # Request fanout histogram
511 system.membus.reqLayer0.occupancy 4771000 # Layer occupancy (ticks)
512 system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
513 system.membus.respLayer1.occupancy 23675000 # Layer occupancy (ticks)
514 system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
516 ---------- End Simulation Statistics ----------
projects / gem5.git / blob