3 from __future__
import division
4 from __future__
import print_function
8 from contextlib
import contextmanager
11 def redirect_stdout(new_target
):
12 old_target
, sys
.stdout
= sys
.stdout
, new_target
16 sys
.stdout
= old_target
18 def random_expression(depth
= 3, maxparam
= 0):
20 return random_expression(depth
= depth
-1, maxparam
= maxparam
)
22 if maxparam
!= 0 and random
.randint(0, 1) != 0:
23 return 'p%02d' % random
.randint(0, maxparam
-1)
24 return random
.choice([ '%e', '%f', '%g' ]) % random
.uniform(-2, +2)
25 if random
.randint(0, 4) == 0:
26 return recursion() + random
.choice([ ' < ', ' <= ', ' == ', ' != ', ' >= ', ' > ' ]) + recursion() + ' ? ' + recursion() + ' : ' + recursion()
27 op_prefix
= [ '+(', '-(' ]
28 op_infix
= [ ' + ', ' - ', ' * ', ' / ' ]
29 op_func1
= [ '$ln', '$log10', '$exp', '$sqrt', '$floor', '$ceil', '$sin', '$cos', '$tan', '$asin', '$acos', '$atan', '$sinh', '$cosh', '$tanh', '$asinh', '$acosh', '$atanh' ]
30 op_func2
= [ '$pow', '$atan2', '$hypot' ]
31 op
= random
.choice(op_prefix
+ op_infix
+ op_func1
+ op_func2
)
33 return op
+ recursion() + ')'
35 return '(' + recursion() + op
+ recursion() + ')'
37 return op
+ '(' + recursion() + ')'
39 return op
+ '(' + recursion() + ', ' + recursion() + ')'
42 for idx
in range(100):
43 with
file('temp/uut_%05d.v' % idx
, 'w') as f
, redirect_stdout(f
):
44 print('module uut_%05d(output [63:0] %s);\n' % (idx
, ', '.join(['y%02d' % i
for i
in range(100)])))
46 print('localparam p%02d = %s;' % (i
, random_expression()))
47 # print('localparam%s p%02d = %s;' % (random.choice(['', ' real', ' integer']), i, random_expression()))
48 for i
in range(30, 60):
49 print('localparam p%02d = %s;' % (i
, random_expression(maxparam
= 30)))
50 # print('localparam%s p%02d = %s;' % (random.choice(['', ' real', ' integer']), i, random_expression(maxparam = 30)))
52 print('assign y%02d = 65536 * (%s);' % (i
, random_expression(maxparam
= 60)))
54 with
file('temp/uut_%05d.ys' % idx
, 'w') as f
, redirect_stdout(f
):
55 print('read_verilog uut_%05d.v' % idx
)
56 print('rename uut_%05d uut_%05d_syn' % (idx
, idx
))
57 print('write_verilog uut_%05d_syn.v' % idx
)
58 with
file('temp/uut_%05d_tb.v' % idx
, 'w') as f
, redirect_stdout(f
):
59 print('module uut_%05d_tb;\n' % idx
)
60 print('wire [63:0] %s;' % (', '.join(['r%02d' % i
for i
in range(100)])))
61 print('wire [63:0] %s;' % (', '.join(['s%02d' % i
for i
in range(100)])))
62 print('uut_%05d ref(%s);' % (idx
, ', '.join(['r%02d' % i
for i
in range(100)])))
63 print('uut_%05d_syn syn(%s);' % (idx
, ', '.join(['s%02d' % i
for i
in range(100)])))
64 print('task compare_ref_syn;')
65 print(' input [7:0] i;')
66 print(' input [63:0] r, s;')
67 print(' reg [64*8-1:0] buffer;')
70 print(' if (-1 <= $signed(r-s) && $signed(r-s) <= +1) begin')
71 print(' // $display("%d: %b %b", i, r, s);')
72 print(' end else if (r === s) begin ')
73 print(' // $display("%d: %b %b", i, r, s);')
74 print(' end else begin ')
75 print(' for (j = 0; j < 64; j = j+1)')
76 print(' buffer[j*8 +: 8] = r[j] !== s[j] ? "^" : " ";')
77 print(' $display("\\n%3d: %b %b", i, r, s);')
78 print(' $display(" %s %s", buffer, buffer);')
82 print('initial begin #1;')
84 print(' compare_ref_syn(%2d, r%02d, s%02d);' % (i
, i
, i
))