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Add gitignore
[riscv-isa-sim.git]
/
tests
/
regs.s
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.global main
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main:
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j main
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write_regs:
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sd x1, 0(a0)
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sd x2, 8(a0)
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sd x3, 16(a0)
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sd x4, 24(a0)
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sd x5, 32(a0)
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sd x6, 40(a0)
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sd x7, 48(a0)
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sd x8, 56(a0)
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sd x9, 64(a0)
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sd x11, 72(a0)
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sd x12, 80(a0)
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sd x13, 88(a0)
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sd x14, 96(a0)
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sd x15, 104(a0)
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sd x16, 112(a0)
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sd x17, 120(a0)
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sd x18, 128(a0)
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sd x19, 136(a0)
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sd x20, 144(a0)
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sd x21, 152(a0)
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sd x22, 160(a0)
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sd x23, 168(a0)
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sd x24, 176(a0)
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sd x25, 184(a0)
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sd x26, 192(a0)
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sd x27, 200(a0)
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sd x28, 208(a0)
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sd x29, 216(a0)
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sd x30, 224(a0)
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sd x31, 232(a0)
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csrr x1, 1 # fflags
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all_done:
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j all_done
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data:
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.fill 64, 8, 0