tests/sat/asserts.v

   1 // http://www.reddit.com/r/yosys/comments/1vljks/new_support_for_systemveriloglike_asserts/
   2 module test(input clk, input rst, output y);
   3 reg [2:0] state;
   4 always @(posedge clk) begin
   5     if (rst || state == 3) begin
   6         state <= 0;
   7     end else begin
   8         assert(state < 3);
   9         state <= state + 1;
  10     end
  11 end
  12 assign y = state[2];
  13 assert property (y !== 1'b1);
  14 endmodule