tests/sat/counters.v

   1
   2 module counter1(clk, rst, ping);
   3         input clk, rst;
   4         output ping;
   5         reg [31:0] count;
   6
   7         always @(posedge clk) begin
   8                 if (rst)
   9                         count <= 0;
  10                 else
  11                         count <= count + 1;
  12         end
  13
  14         assign ping = &count;
  15 endmodule
  16
  17 module counter2(clk, rst, ping);
  18         input clk, rst;
  19         output ping;
  20         reg [31:0] count;
  21
  22         integer i;
  23         reg carry;
  24
  25         always @(posedge clk) begin
  26                 carry = 1;
  27                 for (i = 0; i < 32; i = i+1) begin
  28                         count[i] <= !rst & (count[i] ^ carry);
  29                         carry = count[i] & carry;
  30                 end
  31         end
  32
  33         assign ping = &count;
  34 endmodule
  35