tests/sat/expose_dff.v

   1
   2 module test1(input clk, input [3:0] a, output reg [3:0] y);
   3 always @(posedge clk)
   4         y <= a;
   5 endmodule
   6
   7 module test2(input clk, input [3:0] a, output reg [3:0] y);
   8 wire clk_n = !clk;
   9 always @(negedge clk_n)
  10         y[1:0] <= a[1:0];
  11 always @(negedge clk_n)
  12         y[3:2] <= a[3:2];
  13 endmodule
  14
  15 // -----------------------------------------------------------
  16
  17 module test3(input clk, rst, input [3:0] a, output reg [3:0] y);
  18 always @(posedge clk, posedge rst)
  19         if (rst)
  20                 y <= 12;
  21         else
  22                 y <= |a;
  23 endmodule
  24
  25 module test4(input clk, rst, input [3:0] a, output reg [3:0] y);
  26 wire rst_n = !rst;
  27 always @(posedge clk, negedge rst_n)
  28         if (!rst_n)
  29                 y <= 12;
  30         else
  31                 y <= a != 0;
  32 endmodule
  33