2 module test1(input clk, input [3:0] a, output reg [3:0] y);
7 module test2(input clk, input [3:0] a, output reg [3:0] y);
9 always @(negedge clk_n)
11 always @(negedge clk_n)
15 // -----------------------------------------------------------
17 module test3(input clk, rst, input [3:0] a, output reg [3:0] y);
18 always @(posedge clk, posedge rst)
25 module test4(input clk, rst, input [3:0] a, output reg [3:0] y);
27 always @(posedge clk, negedge rst_n)