Merge pull request #1143 from YosysHQ/clifford/fix1135
[yosys.git] / tests / sat / initval.v
1 module test(input clk, input [3:0] bar, output [3:0] foo);
2 reg [3:0] foo = 0;
3 reg [3:0] last_bar = 0;
4
5 always @*
6 foo[1:0] <= bar[1:0];
7
8 always @(posedge clk)
9 foo[3:2] <= bar[3:2];
10
11 always @(posedge clk)
12 last_bar <= bar;
13
14 assert property (foo == {last_bar[3:2], bar[1:0]});
15 endmodule