tests/sat/share.v

   1 module test_1(
   2         input [7:0] a, b, c,
   3         input s, x,
   4         output [7:0] y1, y2
   5 );
   6         wire [7:0] t1, t2;
   7         assign t1 = s ? a*b : 0, t2 = !s ? b*c : 0;
   8         assign y1 = x ? t2 : t1, y2 = x ? t1 : t2;
   9 endmodule
  10
  11
  12 module test_2(
  13         input s,
  14         input [7:0] a, b, c,
  15         output reg [7:0] y
  16 );
  17         always @* begin
  18                 y <= 'bx;
  19                 if (s) begin
  20                         if (a * b > 8)
  21                                 y <= b / c;
  22                         else
  23                                 y <= c / b;
  24                 end else begin
  25                         if (b * c > 8)
  26                                 y <= a / b;
  27                         else
  28                                 y <= b / a;
  29                 end
  30         end
  31 endmodule
  32