Merge branch 'pr_elab_sys_tasks' of https://github.com/udif/yosys into clifford/pr983
[yosys.git] / tests / sat / sizebits.sv
1 module functions01;
2
3 wire [5:2]x;
4 wire [3:0]y[2:7];
5 wire [3:0]z[7:2][2:9];
6
7 //wire [$size(x)-1:0]x_size;
8 //wire [$size({x, x})-1:0]xx_size;
9 //wire [$size(y)-1:0]y_size;
10 //wire [$size(z)-1:0]z_size;
11
12 assert property ($size(x) == 4);
13 assert property ($size({3{x}}) == 3*4);
14 assert property ($size(y) == 6);
15 assert property ($size(y, 1) == 6);
16 assert property ($size(y, (1+1)) == 4);
17
18 assert property ($size(z) == 6);
19 assert property ($size(z, 1) == 6);
20 assert property ($size(z, 2) == 8);
21 assert property ($size(z, 3) == 4);
22 // This should trigger an error if enabled (it does).
23 //assert property ($size(z, 4) == 4);
24
25 //wire [$bits(x)-1:0]x_bits;
26 //wire [$bits({x, x})-1:0]xx_bits;
27
28 assert property ($bits(x) == 4);
29 assert property ($bits(y) == 4*6);
30 assert property ($bits(z) == 4*6*8);
31
32 endmodule