tests/sat/splice.v

   1 module test(a, b, y);
   2
   3 input [15:0] a, b;
   4 output [15:0] y;
   5
   6 wire [7:0] ah = a[15:8], al = a[7:0];
   7 wire [7:0] bh = b[15:8], bl = b[7:0];
   8
   9 wire [7:0] th = ah + bh, tl = al + bl;
  10 wire [15:0] t = {th, tl}, k = t ^ 16'hcd;
  11
  12 assign y = { k[7:0], k[15:8] };
  13
  14 endmodule