tests/sat/splice.ys

   1 read_verilog splice.v
   2 hierarchy -check; opt
   3 copy test gold
   4
   5 cd test
   6 splice
   7 # show
   8
   9 cd ..
  10 rename test gate
  11 miter -equiv -make_assert -make_outputs gold gate miter
  12
  13 flatten miter
  14 sat -verify -prove-asserts -show-inputs -show-outputs miter