tests/simple/always01.v

   1 module uut_always01(clock, reset, count);
   2
   3 input clock, reset;
   4 output [3:0] count;
   5 reg [3:0] count;
   6
   7 always @(posedge clock)
   8         count <= reset ?  0 : count + 1;
   9
  10 endmodule