tests/simple/always02.v

   1 module uut_always02(clock, reset, count);
   2
   3 input clock, reset;
   4 output [3:0] count;
   5 reg [3:0] count;
   6
   7 always @(posedge clock) begin
   8         count <= count + 1;
   9         if (reset)
  10                 count <= 0;
  11 end
  12
  13 endmodule