tests/simple/always03.v

   1 module uut_always03(clock, in1, in2, in3, in4, in5, in6, in7, out1, out2, out3);
   2
   3 input clock, in1, in2, in3, in4, in5, in6, in7;
   4 output out1, out2, out3;
   5 reg out1, out2, out3;
   6
   7 always @(posedge clock) begin
   8         out1 = in1;
   9         if (in2)
  10                 out1 = !out1;
  11         out2 <= out1;
  12         if (in3)
  13                 out2 <= out2;
  14         if (in4)
  15                 if (in5)
  16                         out3 <= in6;
  17                 else
  18                         out3 <= in7;
  19         out1 = out1 ^ out2;
  20 end
  21
  22 endmodule